Application Note MB Power/Duty Cycle Trade-off. Power-up using external voltage reference. Glitch-free analog output after power-up

Transcription

1 Application Note MB86065 Power/Duty Cycle Trade-off The need to use a high performance DAC, such as the 14-bit 1.3GSa/s MB86065, can be due to one or more reasons including, March 2008 Version 1.0 Power-up using external voltage reference Wide bandwidth signal generation Superior dynamic performance High direct-if generation for easier up-conversion Providing such capability inevitably has implications on the system s power consumption and can present a challenge for battery powered designs. However, in designs where there is non-continuous operation powering down the DAC when it is not required can deliver an optimised solution without compromising its capability, for example to support, Half-duplex radios Burst-mode operation This approach can be extended to support narrow-band legacy air interfaces in multi-mode or combination systems through dynamic reconfiguration. Glitch-free analog output after power-up To implement such a system requires certain design considerations and an understanding of the DAC s behaviour through the power-up and down processes. This is documented in this Application Note. The techniques can equally be applied to the dual channel MB Fujitsu Microelectronics Europe GmbH Production Page 1 of 1

2 1 Overview Where the MB86065 DAC is used in applications not requiring continuous operation, it is likely that powering down the device to minimise power consumption will be of interest. This has an obvious benefit in battery powered applications but even more so where the device is implementing noncontinuous signal generation of legacy or narrow-band air interfaces. 1.1 Power Down Configurations The active power consumption, which varies with clock rate, is well documented in the product data sheet, Section 4.8. For example, the MB86065 consumes ~750mW (typical) when running at 1GSa/s. To reduce power consumption there are a number of options primarily configured through the POWER DOWN register, [0x1C3]. These are summarised in Table 1. Through the single control bit in configuration 1, all the DAC clocks, references and bias circuits are powered down; while configuration 2 also powers down the LVDS input ports. Configurations 1 & 2 provide a significant reduction compared to the operating power consumption but can be improved further by disabling the internal LVDS terminations, as in configuration 3. The LVDS terminations consume power since these are implemented as active transistors rather than passive resistors as tends to be illustrated on a functional diagram. This approach is typical for on-chip implementation. Table 1 Alternative power down configurations Configuration 1 Configuration 2 Configuration 3 Configuration 4 POWER DOWN [0x1C3] pdn_ckandrefs = 1 POWER DOWN [0x1C3] pdn_ckandrefs = 1 pdn_indata = 1 pdn_indatb = 1 POWER DOWN [0x1C3] pdn_ckandrefs = 1 pdn_indata = 1 pdn_indatb = 1 POWER DOWN [0x1C3] pdn_reglo = 1 pdn_reg18 = 1 pdn_reg25 = 1 SYSTEM MISC [0x1C4] en_int_term = 0 SYSTEM MISC [0x1C4] en_int_term = 0 1.8V 14.0 ma 8.1 ma 0.2 ma 22.5 ma 3.3V 0.4 ma 0.4 ma 0.4 ma 35.3 ma Total Power 26.5 mw 15.9 mw 1.7 mw 157 mw In configurations 1-3 the Clock Outputs 1 & 2 and Loop Clock are powered down. This will have implications on the FPGA if it is using these clocks for anything more than driving data onto the LVDS bus. If the Clock Outputs must be maintained then configuration 4 may be considered, but the resulting power-down consumption is clearly not as attractive. Page 2 of 2 Production 2008 Fujitsu Microelectronics Europe GmbH

3 2 Powering Up After the DAC is instructed to power-up the internal references and regulators require some time to reach their stable operating point. This is illustrated in Figure 1 where VREF takes ~400µs to settle following the falling edge of SERIAL_EN. These results are based on the standard customer development kit (DK) configuration where the internal bandgap reference, BGAP, drives VREF via a 1kΩ resistor and is then decoupled by a 100nF capacitor. SERIAL_EN VREF Output Clock AVD25 Figure 1. Delayed VREF, driven by BGAP, after power-up The DK also supports provision of an external voltage reference, which can be used in place of BGAP. This is powered by a regulated output, AVD25, and the improved time to establish VREF is illustrated in Figure 2. Even though there is still a delay in the regulated output starting up, the time to establish VREF reduces to ~50µs. The external reference is also connected via a 1kΩ resistor and decoupled by a 100nF capacitor, and these component values could be optimised to further improve this time. To avoid problems caused by the extended start-up time of the references and regulated outputs an external voltage reference should be used, supplied from a clean non-switched supply that is independent to the DAC power-up state Fujitsu Microelectronics Europe GmbH Production Page 3 of 3

4 SERIAL_EN VREF Output Clock AVD25 Figure 2. Improved VREF, driven by external voltage reference Another consequence of the delayed start-up of regulated supplies is evident in the clock input bias, where this is derived from the AVD18_CLK output in accordance with Section 6.2 of the MB86065 data sheet. AVD18_CLK is decoupled by a 100nF capacitor, as recommended, and takes ~5.5µs to reach regulation. The clock input bias is then derived from this by a potential divider, with a further 100nF decoupling capacitor, resulting in a ~10µs delay to the correct clock bias being established. This is illustrated in Figure 3. To minimise start-up time of the clock bias, this should also be derived from a clean nonswitched supply. Page 4 of 4 Production 2008 Fujitsu Microelectronics Europe GmbH

5 SERIAL_EN Clock Input Bias Output Clock Figure 3. Delay to Input Clock bias voltage when derived from AVD18_CLK 2008 Fujitsu Microelectronics Europe GmbH Production Page 5 of 5

6 3 DAC Output Having reviewed the various considerations surrounding powering up the DAC, attention should also be given to what happens at the DAC output. When tested with both static and active input data the output is seen to exhibit glitches, as shown in Figure 4. For these tests the clock frequency is 20MHz and with static data presented to the LVDS inputs. The oscilloscope input is set to DC coupled but the transformer coupled output stage of the DK causes the DC shift. Repeating the test with active data at the LVDS inputs also shows glitches at the output. Further investigation identified the cause of the problem being the loading of unstable data into the data pipeline. This is a result of the data pipeline relying on one of the references in the DAC common circuits which has been powered down. Output Clock SERIAL_EN Analog Output Figure 4. DAC output glitches after power-up This problem can be avoided when powering down by disabling the LVDS input data ports, via POWER DOWN register [0x1C3], followed by the DAC core and reversing this sequence when powering up. Example sequences for the MB86065, assuming only Port A is being used, are presented in Table 2 and Table 3. Page 6 of 6 Production 2008 Fujitsu Microelectronics Europe GmbH

7 Table 2 Power-down sequence to prevent analog output glitches Register Data Action Notes 0x1C3 0x0F80 Disable LVDS inputs Output clocks remain active 0x1C3 0x0F90 Disable DAC Output clocks disabled Table 3 Power-up sequence to prevent analog output glitches Register Data Action Notes 0x1C3 0x0F80 Enable DAC Output clocks enabled 0x1C3 0x0B80 Enable LVDS inputs Output Clock Analog Output Figure 5. Glitch-free analog output after power-up 2008 Fujitsu Microelectronics Europe GmbH Production Page 7 of 7

8 4 Implications for FPGA Data Source In applications where the DAC data is provided by an FPGA it is assumed that the Fujitsu Loop- Clock will be implemented. This functionality relies on the Output Clock from the DAC and the Loop Clock circuit combined with a PLL or DLL in the FPGA. After powering-up, during which the DAC clocks will be enabled, the Loop Clock will take time to lock. As an example, the lock time was measured when using the Xilinx Virtex -5 and the results plotted for different DAC clock frequencies in Figure 6. These results were taken using an external, constantly enabled voltage reference and input clock bias circuit as per the earlier recommendations. 25 SERIAL_EN to PLL Locked Time (µs) Fclk (MHz) Figure 6. FPGA PLL lock time measured using Xilinx Virtex-5 ML550 platform Trademarks and registered trademarks are the property of their respective owners. Page 8 of 8 Production 2008 Fujitsu Microelectronics Europe GmbH

9 5 Overall Power Sequence Summary Powered up Power down stage 1 2.4µs min. to send serial word at max clock rate Power down stage 2 2.4µs min. to send serial word at max clock rate Allow current to settle 20µs for current to settle to minimum Powered down ~50µs (min.) for power down - power up sequence Power up stage 3 2.4µs min. to send serial word at max clock rate Power up stage 4 Wait for PLL to lock 22µs for PLL to lock at maximum clock of 650MHz Powered up 2008 Fujitsu Microelectronics Europe GmbH Production Page 9 of 9

10 6 Customer Support General enquiries and requests for support on any aspect of Fujitsu s high performance DACs should be ed to: msd.support@fme.fujitsu.com Page 10 of 10 Production 2008 Fujitsu Microelectronics Europe GmbH

11 Notes 2008 Fujitsu Microelectronics Europe GmbH Production Page 11 of 11

12 Worldwide Headquarters Japan Tel: Fax: Fujitsu Limited Kamikodanaka Nakahara-ku Kawasaki-shi Kanagawa-ken Japan Asia Tel: Fax: Fujitsu Microelectronics Asia Pte Ltd 151 Lorong Chauan New Tech Park #05-08 Singapore USA Tel: Fax: Fujitsu Microelectronics America, Inc E. Arques Avenue, M/S 333 Sunnyvale, CA USA Europe Tel: Fax: Fujitsu Microelectronics Europe GmbH Pittlerstrasse Langen Germany Tel: Fax: Customer Response Center Mon-Fri: 7am-5pm (PST) representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. No license is granted by implication or otherwise under any patent or patent rights of Fujitsu Microelectronics Europe GmbH. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan. Page 12 of 12 Production 2008 Fujitsu Microelectronics Europe GmbH