HW & SW co-verification of baseband HSPA Processor with Seamless PSP

Transcription

1 HW & SW co-verification of baseband HSPA Processor with Seamless PSP Zheng Li, Xuedong Yang, Bing Wang, Zhitao Lu, Lawrence Yang, James Gualdoni, Jagan Raghavendran Steven Swanchara, William Hinkel, Scott Wincklhofer, Marc Shelton, Raymond Tsui WOCC2007, NJIT, April 27, 2007

2 Overview The Structure of UMTS HSPA channels Co-design and co-verification advantages TTT significance with HW/SW co-verification Setup Co-verification environment with Seamless PSP HSPA Baseband Channel processing Explore HDL Link to Vstation for speeding up HW/SW emulation Summary

3 Structure of the HSPA channels Downlink HS-DSCH (Physical channel ) HS-SCCH (Physical channel, associated sygnalling ) E-AGCH (Physical Channel, feedback ) E-RGCH (Physical Channel, feedback ) E-HICH (Physical Channel, feedback ) Uplink : E-DPDCH (User Info) E-DPCCH (Physical channel, Associated Signaling ) HS-DPCCH (Physical channel, feedback ) UE Node B

4 Co-design and verification advantages TTT: In the early stage of baseband channel card development of HSPA (High Speed Packet Access) for W-CDMA system, an effective Hardware and Software co-verification platform can help the team to reduce the TTT (Time To Technology) period. Cycle-accurate Simulation: Co-simulation or co-verification environment (CVE) with Seamless PSP Simulator and VHDL HW simulator will help the developers to shorten the time for development. Benefits to both HW and SW designers

5 High level abstract v.s. low level design The configuration and execution of co-verification tool takes place in a higher abstract level, while the DSP FW and RTL partition can progress in specific lower design level and the executable code will target to the physical board when it s available. Using the Seamless CVE simulator on Unix station, with the HSPA symbol-level control logic being verified in a DSP simulator, the chip-level signal processing can be verified parallel in a VHDL simulator in the same environment that keeps the design consistency.

6 The significance of co-verification HW Design SW Design Time Gap Board level testing Board level testing Board level testing Coverification Job done TTT TTM Much shorter TTT compared to TTM Closed the Time Gap between HW/SW develop & Sys test. Reduced system integration time.

7 Modulation scheme & HSDPA peak rate QPSK: Channel Bit Rate = 480 kbps Channel Symbol Rate = 240 ksps Bits/HS-DSCH Subframe = 960 bit/subfrm Peak Rate = 960 x 15 / 2msec = 7.2 Mbps 16 QAM: Channel Bit Rate = 960 kbps Channel Symbol Rate = 240 ksps Bits/HS-DSCH Subframe = 1920 bit/subfrm Peak Rate = 1920 x 15 /2ms = 14.4 Mbps

8 Explore Peak rate HSDPA system 16 QAM SC1 (16 chips) 1920 bits / HS- DSCH subframe 1 subframe = 2 msec 480 mod Sym SC x 10^6 chip/sec Basic Coding R = 1/ bits / HS- DSCH subframe 480 mod Sym Information: bits Max Transport Block Size Turbo Coding code bits Symbol Secletion bits 1920 bits / HS- DSCH subframe 480 mod Sym SC3 Data Rate = bits / 2 msec = Mbps Effective Coding Rate = bits / = SC bits / HS- DSCH subframe 480 mod Sym

9 Modulation scheme & HSUPA Peak rate C 8,0 QPSK C 4,0 C 2,0 C 8,1 Data SF=4 is 960 kbps 1920 bits/tti C 4,1 C 1,0 C 8,3 I channel: = 5760 bits Q channel: = 5760 bits bits/tti = 5.76 Mbps C 4,2 per TTI = 2ms C 8,5 C 2,1 Data SF=2 is 1920 kbps C 4, bits/tti C 8,7

10 Processor Support Package HW/SW PSP (processor support package) Models in industry for ADI, ARM, IBM, MIPS, StartCore, TI, ZSP,, processor devices. PSP model simulates most of the pins of the industrial Processor chip device accurately. Seamless CVE model.

11 Prepare DSP design and HDL design for the Seamless PSP and Modelsim DSP FW design HDL SW design Select the proper: Compiler Assmebler Linker vlib work: Creating HDL design library Vcom: Compile the design package DSP executable image For DSP Simulator HDL executable image For HDL ModleSim

12 Format conversion to fit the DSP PSP simulator DSP Simulator in Windows CVE: Reloadable Executable file PSP Format conversion Format conversion DSP Simulator in UNIX CVE: Reloadable Executable file

13 HSPA baseband processor co-simulation External SRAM EMIF Bus EMIF Interupt Acknowledge DSP Simulator: Symbol level processing Seamless PSP of DSP processor mem EDMA Transfer P o r t HDL simulator: Chip level processing Matchpoint Matchpoint Test Vectors Generator The developed DSP software and HW RTL code will b re-used on the physical HSPA channel processor card simultaneously or later in the lab or in the field.

14 HSPA Baseband processing GUI: Seamless PSP, DSP debugger and Modelsim Seamless Configuration Define memory mapping for all processors & registers HDL simulator Modelsim invocation DSP Software simulator invocation

15 Baseband channel processing Rel 99 Channel setup HSPA channel setup HSPA Parameter configuration Reconfiguration Handover Power adjustment Measurement Error monitoring... Request Response Scheduler Data/ control Data/ control Symbol level Processor Data/ control Data/ control Chip level Processor

16 Explore Vstation emulation with HDL Link Workstation Simulator VStation Emulator HDL Testbench HDL LINK Transaction Interface Portal co-modeling Design Under Test HDL Link helps to establish: - Testbench Only in Software Simulator; - Testbench and behavioral blocks in Software Simulator; - Block-by-block migration. Migrate the HDL RTL code from the workstation Simulator to Vstation Emulator; - TIP co-modeling enhanced the performance and debug capabilities.

17 Compile the design for HW partitioning Partition a module in - Vstation region - Behave region Design Unit VHDL OM units Partioner - In-Circuit Emulation region - below a certain module Output: RTLC VMW Netlist Partition Database igen Compiled database used at runtime. Behave Shadow and Gate Netlist RTL Transactors RTLC vmwnetlist Design Database Integration Files Mixnet.info Gate Shadow Hierachy

18 Vstation with MCT testbench Vstation MCT Testbench Input Test Vectors Vstation output Comparison Mechanism - Multi-Channel Transport co-modeling enables SW testbench run HW verification at high speed. - Transactor portability for ASIC interfaces. - System level modeling and verification in C/C++, SystemC

19 Debugging Vstation with HDL Link - All signals are visible to user at any time. - User can set break-point on Behavioral signal, change signal without re-compile. - User can set trigger on Vstation signal to stop the emulation.

20 Vstation Emulation Speed v.s. Workstation Simulation Speed depends on: - ASIC/FPGA Design size - Vstation Driven Clock - Simulator on what kind of Workstation - The number of behavioral blocks still remained in HDL Link testbench. - The method used to hook Simulator onto Emulator

21 Design and co-verification Target - 3G Rel. 99 baseband processor. - 3G Rel. 5 for HSDPA baseband processor - 3G Rel. 6 for HSUPA baseband processor - LTE baseband processor - future wireless & comm. SoC processor

22 Summary Seamless CVE with application specific PSP provides a flexible DSP simulator solution to the HSPA baseband processor development that can cycle-accurately simulate the symbol level processing together with the Modelsim chip-level processing. HDL link can be considered to use in partitioning the HDL design modules onto Vstation for high speed emulation. System level verification methodologies can close the gap between the SW design and HW design, and between the sequential processing and parallel processing. HSPA verification methodologies introduced here applies to any large scale DSP, FPGA and ASIC integration system.

23 Reference [1] 3GPP TS , TS25.212, TS Technical Specification. 3rd Generation Partnership Project, Technical Specification Group Radio Access Network, FDD Release 5, Release 6. [2] HDL Link User s Guide. Mentor Graphics HDL Link Software, [3] WCDMA for UMTS, Radio Access for Third Generation Mobile Communications. By Harri Holma and Antti Toshala. Contact zhengli@alcatel-lucent.com zhengli@ieee.org