August, 2010 Enabling Software Defined Radio with the Modem Vector Signal Processor ENT-F0766

Transcription

1 August, 2010 Enabling Software Defined Radio with the Modem Vector Signal Processor ENT-F0766 Kevin Traylor Freescale Fellow Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc.

2 SDR = Software Defined Radio Introduction Common transceiver and modem baseband for all bands and bandwidths Able to adapt radio to new or changing requirements without making HW changes Analog Tx/Rx ADC/DAC Digital Modem Applications Processor Multi-band Multi-mode transceiver available today Not an optimal solution available for multi-mode digital modem State of the art: General Purpose DSP w/ hardware acceleration Freescale Modem Vector Signal Processor Flexibility of General Purpose DSP Large number of arithmetic Operations-per-Second (OPS) with low cost & power of hardware acceleration Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 2

3 Session Objectives Motivation for new Vector Signal Processor Identify advantages versus traditional solutions Technical review of architecture and development model Review example applications Trigger customer interest in SOC applications with new Vector Signal Processor Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 3

4 Session Agenda Positioning Modem Vector Signal Processor Architecture End Applications Software Development SOC architecture Programmable Channel Codecs Accelerator Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 4

5 Solution Optimality Combines flexibility of general purpose DSP with benefits of fixed hardware acceleration Enables standards upgrades and field bug fixes Lower cost solution than fixed accelerators Each L1 algorithm requires unique accelerator MIPS mw A D f D f A f A A f D D $ Flexibility Target cost critical, low power, applications f - Modem Vector Signal Processor A - Fixed Accelerator D - DSP Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 5

6 Architecture Enablers & Differentiators Target application space is communications signal processing Focus on sample rate processing FFT/DFT, Convolution/Corellation, Equalization, MIMO, LLR, Detection Rely on Host MCU for bulk of control functionality but limit IRQ rate Single thread no interrupts Complex Vector Arithmetic Unit Single Instruction Multiple Data (SIMD) Enables lower clock frequency for given OPS requirement Eliminates need for cache controller Lower current drain per OP Synthesizable design for rapid migration to new technology nodes Scalable number of complex elements (samples) per vector Includes non-linear operations; reciprocal, logarithm, exponential, etc. Floating point data type Rapid implementation of algorithms in software Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 6

7 Data Rate (Mbps) Modem Processor Scalability 1000 Base Station LTE 100 Cellular Subscriber LTE Home Plug 10 WiFi Cellular Subscriber HSDPA 1 Metering Two-Way Radio Building Automation Remote Control Modem Vector Processor AU s (data path width & clock frequency also scale) Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 7

8 Architecture Block Diagram Program ROM/RAM I/O Events & Flow Control Gen. Purpose Unit Instruction Decoder Twiddle Tables Dual Port DATA Memory Multi-port Register File Scalar Re-arrangement Vector Arithmetic Unit Sequence Generators Fix / Flt DMA AXI Bus Fixed Control Plane Scalable data path width Vector of N samples Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 8

9 General flow control Instruction Set Highlights Switch & case statements and conditional jmp & jsr instructions Multiple levels of jsr s & nested loops in hardware Addressing Multiple memory address generator & modifier units Includes special bit & digit reversed modes Sample based addressing w/ modulo wrap Register file address generator & modifier units General Purpose Unit Used for integer math and interfacing with control registers 32-bit single cycle fixed-point ALU with a 4-deep register file Support add, sub, compare, fix/float conversion, shift, and bitwise logical operations Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 9

10 Vector Arithmetic Unit All operations in floating point Vector composed of synthesis variable set of scalar Arithmetic Units (AUs) Arithmetic Unit functionality Single complex MAC/MADD operation per cycle; Y=X0*X1+X2 Four real MAC/MADD operations per cycle Complex DIT Butterfly operation per cycle; Y0=X0+W*X1, Y1=X0-W*X1 Complex DIF Butterfly operation per cycle; Y0=X0+X1, Y1=W*(X0-X1) Embedded twiddle factor generation Mixed radix DFT support Despreading/Spreading support for WCDMA Single cycle 1/X, 1/sqrt(X), log(x), exp(jx), etc. Single cycle vector sequence generation General complex exponentials and Chirps (LTE) WCDMA OVSF and Gold codes Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 10

11 Computation Efficiency Benchmarks Algorithm Benchmarks # cycles Number of AUs used in benchmark AU efficiency (%) 2048pt FFT % 1200pt DFT (Mixed Radix) LTE PSCH TD Correlation % % 1200 subcarriers 64QAM 2x2 MIMO MMSE Detector & LLRs % Descramble & Despread 256 chips, 256 SF, 8 PhyChan/User, 90 Users % Notes: AU = Arithmetic Unit; Single complex MAC FLOP or 4 real MAC FLOPs AU efficiency = fraction of the total cycles executing a vector AU operation Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 11

12 Applications & Enabled Horsepower Vector Clock Application Process Size Freq GFLOPs Node (Complex Samples) (MHz) Two Way Radio & 1Mbps FSK/OFDM EGPRS2 Modem (32QAM w/ Diversity) 2G/3G/LTE Terminal (150/50 Mbps Rx/Tx) Femto Base (16 users) 3G/LTE Multi-mode C90LP C65LP C65LP C45SOI Pico Base (64 users) 3G/LTE Multi-mode Optimized for high MIPS & Low Cost C45SOI X more horsepowerper-mgate than traditional DSP Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 12

13 Current drain (ma) Design minimizes mw/gflop < 10mW/GFLOP in 65nm 25X lower power than traditional DSP Proportional to computational load Dynamic Voltage & Frequency Scaling provide further improvements Optimized for low power Mean = ma Low power Idle state Microcode profile Clocks are gated off when processing interval is complete and waiting for more data Internal counter wakes up the machine when new data is ready Idle leakage power << 1mW in LP technology node Low power techniques in Active state Instruction driven clock gating used to turn off unused logic per clock Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 13

14 Algorithm Development Flow Algorithm Design ( Infinite Precision ) Finite Precision Modeling Software Module Creation Algorithm Function/ Subroutine Library Freescale provides library of physical layer algorithm functions FFT, Mixed Radix DFTs, MMSE, LLR, FM Demod/Mod, Rake, etc. Algorithm development flow leverages Matlab environment Radio Link Simulators typically written in Matlab/C code Bit-exact Matlab models of arithmetic operations available Matlab test bench used in each stage of development Debugger interface to Matlab Rapid finite precision modeling with floating point operations Typically the long pole in schedule Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 14

15 Control Software Development Flow Algorithm Intrinsics Library main.c Software Design Integration & Debug C-Compiler IDE Freescale provides library of algorithm bit exact intrinsics library ANSI C-compiler for general purpose control & ALU operations Vector algorithm function calls Vector math operations supported in future releases Debugger compatible with ARM IDE Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 15

16 Real Time Debug Features Leverages ARM RealView Development Suite (RVDS) Debugger Does not require additional IDE for system Multiple hardware breakpoints Read and Write internal registers and memory during break session Single step, Go for N cycles, Resume GPIO ports are available Example debug printout 128-bit DMEM Line 16-bit Real 16-bit Imag. 32-bit Complex Element Data Memory contents Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 16

17 LTE Base Station Application; Uplink Demodulation Modem Vector Signal Processor Software User # 1 PUSCH MMSE Detector IDFT LLR from Receiver 2 FFT User/RE Demap Channel Estimation memory to Turbo Decoder MMSE Detector memory IDFT LLR Channel Estimation User # N PUSCH Host Processor Scheduler Info Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 17

18 Bus Masters Bus Slaves Typical System-on-Chip Application Host RISC Microcontroller External Memory Interface DDR Memory Modem Vector Signal Processor Data Memory Bus Fabric Memory Radio Interface Transceiver Programmable Channel Codec Accelerator Data Memory Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 18

19 Programmable Channel Codec Accelerator HARQ LLRs MAP Engine Data Memory i/o Memory Deinterleaving Rate Matching HARQ Combining DMA Controller Turbo Decoder MAP Engine SIC Encoder LLRs Transport CH 3G R99 Deinterleaving Rate Matching Physical CH LLRs AXI Bus Dual Turbo Paths w/ SIC for MIMO Synthesis parameter sets number of MAP engines & turbo throughput Cat 5 LTE (300 Mbps Rx, 75 Mbps Tx) Low power - 133MHz clock frequency 3G R99 DCH Data Memory HSDPA HS-SCCH LTE PDCCH General Purpose Viterbi Decoder 3G/LTE Tx Encoder I/O Memory slave AXI Bus Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 19

20 Programmable Channel Codec Accelerator Features HSPA+, R99, and LTE-PDSCH complete coding chains including interleaving, rate matching, HARQ combining, Viterbi and Turbo coding Successive Interference Cancellation Re-encoder chain for improved MIMO performance Complete control channel decoding chain for HSPA and LTE including blind search Supports EGPRS and EGPRS2 viterbi and turbo decoding Optional support for CDMA2000 Minimizes Host interrupt rate and MCPS load TTI handshake Internal DMA AXI bus master Link list support on I/O to MAC software Enables transparent (from Host software) HARQ combining inside the module Turbo Decoder Synthesizable number of MAP engines enables scalable platform optimized per category Scalable up to LTE Category 5 (300Mbps Rx and 75 Mbps Tx) and beyond Optimized for Low Power Low clock frequency (133MHz) in LP process technology node with clock gating 4 th Generation of Module HSPA and R99 functionality in production part LTE functionality proven in FPGA with software and connected to standard test equipment Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 20

21 Freescale s Modem Vector Signal Processor enables SDR Lowest cost per gate solution Lowest power/mip solution Scalable platform; optimized for application MIPs Floating point operations Library of modem algorithm functions enables rapid software development Matlab based algorithm development environment C-compiler & debug tools integrated with ARM RVDS Programmable channel codec accelerator completes cellular modem physical layer solution Summary Reg. U.S. Pat. & Tm. Off. BeeKit, BeeStack, CoreNet, the Energy Efficient Solutions logo, Flexis, MXC, Platform in a Package, Processor Expert, QorIQ, QUICC Engine, SMAROS, TurboLink and VortiQa are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners Freescale Semiconductor, Inc. 21

22