The Veloce Emulator and its Use for Verification and System Integration of Complex Multi-node SOC Computing System

Transcription

1 The Veloce Emulator and its Use for Verification and System Integration of Complex Multi-node SOC Computing System Laurent VUILLEMIN Platform Compile Software Manager Emulation Division

2 Agenda What is Emulation Use models Veloce Architecture Overview Veloce Software Practical : Use Veloce to verify Veloce 2

3 Agenda What is Emulation Use models Veloce Architecture Overview Veloce Software Practical : Use Veloce to verify Veloce 3

4 Verification Challenges Systems Software Debug 4

5 Typical Development Cycle Hardware Hardware Development Development Fab System Integration Software Development Block-level Verification Chip-level Verification System Verification Time to Market Design Cycle 5

6 Typical System Development Hardware Development Fab System Integration Software Development Block-level Verification Chip-level Verification System Verification Time to Market Design Cycle 6

7 Software Simulation module counter (ck, en, step, dout); input ck, en; input [3:0] step output [3:0] dout reg [3 : 0] dout; (posedge ck) begin if ( en ==1 ) dout = dout+step; end endmodule RTL Model Model is represented in Data Structures Compute and propagate signal values module counter (ck, en, step, dout); input ck, en; input [3:0] step output [3:0] dout reg [3 : 0] dout; (posedge ck) begin if ( en ==1 ) dout = dout+step; end endmodule Test bench 7

8 Clock Speed Scaling Stalls Emulation Required to Extend Performance Source: Recording Microprocessor History 4/6/2012 Andrew Danowitz, Kyle Kelley, James Mao, John P. Stevenson, Mark Horowitz

9 Emulation module counter (ck, en, step, dout); input ck, en; input [3:0] step output [3:0] dout reg [3 : 0] dout; (posedge ck) begin if ( en ==1 ) dout = dout+step; end endmodule RTL Model Map RTL model in Programmable Logic Programmable Control execution and get results Logic Multiples FPGA reproduce Model behavior from high level description 9

10 Start Early Continue for Entire SoC Life Architecture Phase Block-level Verification Fullchip/SoC Verification Software, Firmware & Device Drivers Systems Validation Post Silicon Bringup and Validation

11 Agenda What is Emulation Use models Veloce Architecture Overview Veloce Software Practical : Use Veloce to verify Veloce 11

12 RSP Modern SOC environment Embedded SW Debugger SoC PHY PHY PHY PHY CPU USB Ethernet SATA Display Processor Master IF SlaveIF Slave IF Slave IF Slave IF Arbiter JTAG Master IF CPU Master IF Software Memory Fabric Slave IF UART Slave IF GPIO Fabric PCI Express PHY 12

13 ICE use Model The emulator is connected to actual Hardware DUT Cables External Hardware 13 Veloce

14 Ethernet Verification With ICE Ethernet Network Stimulus Generation / Analysis Tools Live Traffic isolve Ethernet 14

15 Co Emulation Testbench Xpress (TBX) Testbench Transactions PCI E 1/2 X-actor AGP 1/2 X-actor USB 1/2 X-actor 1/2 X- actor DUT Testbench divided in 2 parts one in emulator the other in Station Communication via transactor Software sends commands that are interpreted by transactor to generate DUT stimulus High-speed Interface Software Hardware 15

16 Veloce Use Models Simulation Acceleration OVM/UVM SystemVerilog C/SystemC Accelerated Transactors SW Debug Codelink VProbe Fast ISS QEMU Software Debug Virtual Protocol Solutions USB SATA Video Ethernet VirtuaLAB Solutions PCIe Testbench Xpress Co-Model Channels Physical Protocol Solutions PCIe SATA Video USB Ethernet... Physical I/O isolve Solutions 16

17 Agenda What is Emulation Use models Veloce Architecture Overview Veloce Software Practical : Use Veloce to verify Veloce 17

18 Veloce 2 Architecture 2 Chip AVB2 Maximus2 X 16 X SXB (Switch boards) + 4 CXB (clock board) Quattro2 16 AVB2 + 6 SXB (Switch boards) + 1 CXB (clock board) 18

19 2 IC Programmable Logic Array Memories Control Debug Resources Virtual Wire Logic Programmable Logic Array Set of LUT an Sequential elements Interconnect Network Memories : User Memories model Virtual Wire Logic Transport signals between chips Debug Resources Trace every Sequential element and memories Triggers Control Load configuration Control emulation 19

20 Agenda What is Emulation Use models Veloce Architecture Overview Veloce Software Compile Software Runtime Software Practical : Use Veloce to verify Veloce 20

21 Software Overview PC Farm Compile Servers N e t w o r k Emulator host User design Compile SW Configuration bitstream Runtime SW Low Level SW Transform design in bistream User Interface Control Emulator Collect debug data 21

22 Compile software Design +Testbench TBX Partition Testbench between SW and Emulator RTL RTLC Perform RTL Synthesis Gate netlist Platform Compile Partitioning in Sytem Routing Place and Route Ressource Allocation Bitstream 22

23 Runtime Software Mainten ance Server Ressour ce Server Emulator Message Bus User Message Bus Runtime Server Emulator Host Server LLSW Visibility Server UI 23 Veloce DAC 2014

24 Agenda What is Emulation Use models Veloce Architecture Overview Veloce Software Practical : Use Veloce to verify Veloce Challenges The verification infrastructure Verifying ASIC Verifying the Compilation software Low level software integration Firmware validation debug Runtime software integration 24

25 Challenges Complex system ASIC FPGAs Firmware Mutliple software components Verifying all component of the system and their interactions Time to get a bug Size : Detailed model of a full Emulator of next generatio will not fit in current generation 25

26 Addressing the challenges Use a comodel approach for more abstraction level and connection with the software Divide verification in steps based on functionality Simplify the model by using different abstraction level depending on what functionality is tested 26 Veloce DAC 2014

27 Verification Infrastructure More details on Veloce LLSW on host Control Chip Control Control Veloce Control Bus Control Commands 27 Veloce

28 Verification Infrastructure Emulation model Software Control Chip Transactor Control Control Veloce Control Bus Emulator Nature of the Software, Transactor and Model in emulator depend on abstraction level 28 Veloce

29 ASIC verification : example of Trace Data Comodel SW Transac tor Control DDR Controler DDR SW translator Macro Block Trace Capture Trace control Veloce Comands Design Emulation Model Trace Capture, Trace Control and DDR Controler are Accurate models Design is a gate level netlist generating random data Data are either manually generated or come from actual compile Run million cycles on multiple designs 29 Veloce

30 Verification of compile SW Bitstream Comodel SW Transac tor Control Configuration Block LLSW Bitstream reader Macro Block Veloce Comands Emulation Model Macro and Configuration blocks are Accurate models Bitstream is the output of actual compile flow Verify behavior of design 30 Veloce

31 Verification of Low Level Software 1/2 Example : Virtual Wire Synchronisation Control Virtual Wire Logic Data multiplexed on serial link Virtual Wire Logic Control Virtual Wire need a training/calibration sequence This sequence is controled by Low Level Software 31 Veloce

32 Verification of Low Level Software 2/2 Actual LLSW Comodel SW Trans actor Control Chip Control Control VW Block VW Block Emulation Model Control block in and VW block are accurate model Actual LLSW communicate with the model through comodel SW and transactor 32 Veloce

33 Verification of Firmware 1/2 Example : Trigger Reduction AVB Level reduction Trigger Logic FPGA AVB Level reduction FPGA Trigger Logic System Level reduction CXB FPGA Trigger Logic Macro Block Trigger Logic Macro Block Macro Block Macro Block AVB AVB 33 Veloce A trigger express a condition on values coming from the design At AVB and System level it is implemented in FPGA A binary is genrerated by runtime SW to express condition

34 Verification of Firmware Trigger binary Comodel SW Transac tor Control AVB Level reduction FPGA System Level reduction SW translator AVB Level reduction FPGA Trig ger Logi c Macro Block Trig ger Logi c Macro Block FPGA CXB Trig ger Logi c Trig ger Logi c AVB Veloce Comands Macro Block Macro Block AVB Emulation Model Design is modeled as gate level netlist Trigger binary is generated by actual runtime SW Verify behavior of trigger in multiple design sequences 34 Veloce

35 Runtime SW Verification Ressource Server Emulator Message Bus Emulator Host Server LLSW Runtime Server Comodel SW User Message Bus UI Actual Runtime Server is used High level model for the HW Transac tor Control Macro Block Design Memories Emulation Model 35 Veloce

36 QUESTIONS Veloce 36