MAX14581/MAX14582 Industry s Smallest and Lowest (V L ) Full-Speed USB Transceivers, with Low VIO 3/5-Wire Interface

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1 19-639; Rev ; 6/12 MAX14581/MAX14582 General Description The MAX14581/MAX14582 USB-compliant transceivers are designed to minimize the area and external components required to interface low-voltage ASICs to USB. These devices comply with USB 2. specification for fullspeed-only (12Mbps) operation. The transceivers include an internal 3.3V regulator, an internal 1.5kI pullup resistor, and built-in ±15kV ESD HBM protection circuitry to protect the USB I/O ports (, ). The MAX14581/ MAX14582 also have internal series resistors, allowing the devices to be wired directly to a USB connector. These devices operate with logic-supply voltages as low as +1.2V, ensuring compatibility with low-voltage ASICs. A low-power disable mode reduces current consumption to typically less than 13FA (typ) from V BUS. An enumerate function controls the pullup resistor, allowing devices to logically disconnect while remaining plugged in. The devices have 36I (typ) internal series resistors on / for direct connection to the USB connector. These devices can be used as either peripheral or host (FS) USB transceivers. As a host USB transceiver, the MAX14581/MAX14582 require external 15kI pulldown resistors and driving logic-low. The MAX14581 (3-wire) is equipped with DAT and SE interface signals. The transceiver provides a USB detection function that monitors the presence of USB V BUS and signals the event by means of a BD pin. The MAX14582 (5-wire) is equipped with VP, VM, and RCV interface signals. The detection of V BUS in the MAX14582 is encoded as VP = VM = logic-high. These devices operate over the extended -4NC to +85NC temperature range and are available in 12-bump WLP packages. Applications Benefits and Features S Provide Flexible USB Transceiver Design Supports 3-Wire Interface (MAX14581) Supports 5-Wire Interface (MAX14582) USB 2. (Full-Speed, 12Mbps)-Compliant Transceiver +1.2V to +3.6V Interface Voltage (VL) Enumeration Input Controls Pullup Resistor 13µA (typ) Current in Disable Mode S Minimize PCB Area Internal Pullup Resistor on Internal Series Resistors S Additional Protection Features Increase System Reliability Low Output Capacitance for Easy Connection to an External USB HS Transceiver in Parallel No Power-Supply Sequencing Required Ability to Accept / Voltages Up to 3.6V with V BUS = V 28V-Tolerant V BUS Pin Bus Detect (BD) Pin for the V BUS Detection (MAX14581 Only) High-ESD Protection on / and V BUS ±15kV HBM VOLTAGE SUPPLY INTERFACE Typical Application Circuits. V L BD DAT SE MAX14581 GND V BUS USB CONNECTOR Smart Phones Tablets Portable Media Players ebook Readers Ordering Information and USB Inter-Chip Typical Application Circuits appear at end of data sheet. VOLTAGE SUPPLY INTERFACE. V L RCV VP VM MAX14582 GND V BUS USB CONNECTOR For pricing, delivery, and ordering information, please contact Maxim Direct at , or visit Maxim s website at 1

2 ABSOLUTE MAXIMUM RATINGS (All Voltages Referenced to GND, unless otherwise noted.) Supply Voltage (V BUS )...-.3V to +3V Supply Voltage (V L )...-.3V to +6V V to min(+6v, V BUS +.3V), V to 6V VP, VM,, BD,, RCV,, DAT, SE V to (V L +.3V) Short-Circuit Current ( and ) to V BUS or GND...Continuous Maximum Continuous Current (all other pins)... Q15mA Continuous Power Dissipation (T A = +7NC) WLP (derate 13.7mW/NC above +7NC)...5mW Operating Temperature Range... -4NC to +85NC Junction Temperature...+15NC Storage Temperature Range NC to +15NC Soldering Temperature (reflow)...+26nc Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) WLP Junction-to-Ambient Thermal Resistance (B JA )...73NC/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to ELECTRICAL CHARACTERISTICS (V BUS = +3.V to +5.5V, V L = +1.2V to +3.6V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at V BUS = +3.6V, V L = +2.5V, and T A = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage Range Regulated Supply Voltage Output V BUS V L V BUS > 3.6V V < V BUS < 3.6V Operating V BUS Supply Current I VBUS Full-speed transmitting/receiving at 12Mbps, C L = 5pF on and Operating V L Supply Current I L 12Mbps, C L = 15pF on receiver outputs, Full-speed transmitting/receiving at V L = 2.5V Full-Speed Idle and SE Supply Current I VBUS ( IDLE ) Full-speed idle: V > 2.7V, V <.3V, = high or low SE: V <.3V,V <.3V, = high or low Static V L Supply Current I VL(STATIC) Full-speed idle, SE, or suspend mode; = high or low Suspend V BUS Supply Current Disable-Mode V BUS Supply Current I VBUS(P) DAT = SE = open, = = high (MAX14581) VM = VP = open, = = high (MAX14582) V V 8 ma 1 2 ma FA 1 4 FA I VBUS (DIS) V L = GND or open, V BUS up to 5V FA FA 2

3 ELECTRICAL CHARACTERISTICS (continued) (V BUS = +3.V to +5.5V, V L = +1.2V to +3.6V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at V BUS = +3.6V, V L = +2.5V, and T A = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Sharing-Mode V L Supply Current / Sharing-Mode Load Current V BUS Power-Supply Detection Threshold V BUS Power-Supply Detection Hysteresis V L Power-Supply Detection Threshold I VL(SHARING) I D(SHARING) V BUS = GND or open, = low, DAT = SE = high or high-z, = high, MAX14581 V BUS = GND or open, = low, VP = VM = high or high-z, = high, MAX14582 V BUS = GND or open, V D_ = V or +5.5V, = high or low FA.1 1 FA V TH_VBUS V L = 1.2V V V HYST_VBUS 1 mv V TH_VL (Note 3).85 V DIGITAL INPUTS AND OUTPUTS (VP, VM, DAT, SE, RCV,,,, BD) Input-Voltage Low V IL.3 x V L V Input-Voltage High V IH.7 x V L V Output-Voltage Low V OL I OL = 2mA Output-Voltage High V OH I OH = -2mA V L > 1.65V.4 1.2V < V L < 1.65V.55 V L > 1.65V V L V < V L < 1.65V V L -.55 Input Leakage Current I LKG FA ANALOG INPUTS AND OUTPUTS (, ) Differential Input Sensitivity V ID V - V.2 V Differential Common-Mode Voltage Single-Ended Input Low Voltage Single-Ended Input High Voltage V CM Includes V ID range V V ILSE.8 V V IHSE 2. V USB Output-Voltage Low V USB_OLD R L = 1.5kI resistor connected to +3.6V.3 V USB Output-Voltage High V USB_OHD R L = 15kI resistor connected to GND V Internal Pullup Resistance R PULLUP I Driver Output Impedance Z DRV Steady-state drive I Input Impedance Z IN Driver off 1 MI / Off Capacitance C USB Driver off (Note 3) 8 pf V V 3

4 ELECTRICAL CHARACTERISTICS (continued) (V BUS = +3.V to +5.5V, V L = +1.2V to +3.6V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at V BUS = +3.6V, V L = +2.5V, and T A = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DRIVER CHARACTERISTICS (C L = 5pF) Rise Time t FR 1% to 9% of VOHD - V OLD ; Figures 1, ns Fall Time t FF 9% to 1% of VOHD - V OLD ; Figures 1, ns Rise/Fall Time Matching t FR /t FF Figures 1, 6 (Note 3, inferred from drive Excluding the first transition from idle state; output impedance) Output Signal Crossover Voltage V CRS_F Excluding the first transition from idle state, Figure 2 (Note 3) Driver-Propagation Delay Driver-Disable Delay Driver-Enable Delay RECEIVER (C L = 15pF) Differential Receiver Propagation Delay Single-Ended Receiver Propagation Delay Single-Ended Receiver Disable Delay t PLH_DRV t PHL_DRV t PHZ_DRV t PLZ_DRV t PZH_DRV t PZL_DRV t PLH_RCV t PHL_RCV t PLH_SE t PHL_SE t PHZ_SE t PLZ_SE Low-to-high transition; Figures 2, 6 High-to-low transition; Figures 2, 6 High-to-off transition; Figures 3, 6 Low-to-off transition; Figures 3, 6 Off-to-high transition; Figures 3, 6 Off-to-low transition; Figures 3, 6 Low-to-high transition; Figures 4, 7 High-to-low transition; Figures 4, 7 Low-to-high transition; Figures 4, 7 High-to-low transition; Figures 4, 7 High-to-off transition, Figure 5 Low-to-off transition, Figure % V ns ns ns ns ns ns 4

5 ELECTRICAL CHARACTERISTICS (continued) (V BUS = +3.V to +5.5V, V L = +1.2V to +3.6V, T A = T MIN to T MAX, unless otherwise noted. Typical values are at V BUS = +3.6V, V L = +2.5V, and T A = +25NC.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Single-Ended Receiver Enable Delay ESD PROTECTION t PZH_SE t PZL_SE Off-to-high transition, Figure 5 Off-to-low transition, Figure 5 V BUS external ceramic capacitor, HBM Q15 kv, Q15 kv Note 2: All specifications are 1% production tested at T A = +25NC, unless otherwise noted. Specifications are over -4NC to +85NC and are guaranteed by design. Note 3: Guaranteed by design, not production tested. ns 5

6 Timing Diagrams V OHD t FR, t LR 9% 9% t FF, t LF VM RISE/FALL TIMES < 4ns VP V OLD 1% 1% t PLH_DRV t PHL_DRV Figure 1. Rise and Fall Times V CRS_F DAT t PLH_DRV t PHL_DRV V CRS_F SEO t PLH_DRV t PHL_DRV OR OR Figure 2. Timing of (DAT and SE) and (VP and VM) to and 6

7 Timing Diagrams (continued) +3V INPUT RISE/FALL TIME < 4ns / VP/VM CONNECTED TO GND, / CONNECTED TO PULLUP / V t PLZ_DRV t PZL_DRV V L t PLH_RCV, t PLH_SE VP/VM CONNECTED TO V L, / CONNECTED TO PULLDOWN DAT, SE, RCV, VM, AND VP Figure 4. / Timing to VP, VM, and RCV t PHL_RCV, t PHL_SE / MAX14581 MAX14582 t PHZ_DRV / TEST POINT 22I t PZH_DRV Figure 3. Driver Enable and Disable Timing 1. DISABLE TIME (/) MEASUREMENT V = FOR t PHZ V = FOR t PLZ DAT/VP DAT/VP t PLZ_SE t PHZ_SE CONNECTED TO GND, CONNECTED TO +3.V. DAT/VP PULLED TO V L WITH 33I. t PZL_SE CONNECTED TO +3.V, CONNECTED TO GND. DAT/VP PULLED TO GND WITH 33I. t PZH_SE SE/VM CONNECTED TO +3.V, CONNECTED TO GND. SE/VM PULLED TO V L WITH 33I. t PLZ_SE t PZL_SE SE/VM CONNECTED TO GND, CONNECTED TO GND. SE/VM PULLED TO GND WITH 33I. t PHZ_SE t PZH_SE Figure 5. Receiver Enable and Disable Timing 7

8 Timing Diagrams (continued) MAX14581 MAX14582 / 15kI TEST POINT C L 5pF MAX14581 MAX14582 RCV/VP/VM TEST POINT C L 15pF 1. / TO RCV/VM/VP PROPAGATION DELAYS 1. ENABLE TIME (/) MEASUREMENT 2. DAT/SE TO / PROPAGATION DELAY 3. VP/VM TO / PROPAGATION DELAY 4. / RISE/FALL TIMES Figure 7. Test Circuit for Receiver Propagation Delay DAT CONNECTED TO GND, SE CONNECTED TO GND. PULLED TO 3.V WITH 22I. t PLZ_DRV t PZL_DRV DAT CONNECTED TO VL, SE CONNECTED TO GND. PULLED TO GND WITH 22I. t PHZ_DRV t PZH_DRV DAT CONNECTED TO VL, SE CONNECTED TO GND. PULLED TO 3.V WITH 22I. t PLZ_DRV t PZL_DRV DAT CONNECTED TO GND, SE CONNECTED TO GND. PULLED TO GND WITH 22I. t PHZ_DRV t PZH_DRV Figure 6. Test Circuit for Enable Time, Disable Time, Transmitter Propagation Delay, and Transmitter Rise/Fall Time 8

9 (V BUS = +3.6V, V L = +2.5V, T A = +25NC, unless otherwise noted.) Typical Operating Characteristics PROPAGATION DELAY (ns) DIFFERENTIAL RECEIVER PROPAGATION DELAY vs. V L T A = +85 C T A = -4 C T A = +25 C MAX14581 toc1 PROPAGATION DELAY (ns) DIFFERENTIAL RECEIVER PROPAGATION DELAY vs. V BUS T A = -4 C T A = +25 C T A = +85 C MAX14581 toc2 PROPAGATION DELAY (ns) SINGLE-ENDED RECEIVER PROPAGATION DELAY vs. V L T A = -4 C T A = +85 C T A = +25 C MAX14581 toc V L (V) V BUS (V) V L (V) PROPAGATION DELAY (ns) SINGLE-ENDED RECEIVER PROPAGATION DELAY vs. V BUS T A = -4 C T A = +85 C T A = +25 C MAX14581 toc4 TRANSMITTER SKEW (ns) TRANSMITTER SKEW vs. TEMPERATURE MAX14581 toc5 RECEIVER SKEW (ns) RECEIVER SKEW vs. TEMPERATURE MAX14581 toc V BUS (V) TEMPERATURE ( C) TEMPERATURE ( C) SUPPLY CURRENT (µa) V L SUPPLY CURRENT vs. / CAPACITANCE 12Mbps DATA RATE TRANSMITTING MAX14581 toc7 SUPPLY CURRENT (ma) V BUS SUPPLY CURRENT vs. / CAPACITANCE 12Mbps DATA RATE TRANSMITTING MAX14581 toc8 VBUS SUPPLY CURRENT (µa) V BUS PEND CURRENT vs. V BUS SUPPLY VOLTAGE VM = VP = OPEN, = = HIGH T A = +85 C T A = +25 C T A = -4 C MAX14581 toc CAPACITANCE (pf) CAPACITANCE (pf) V BUS (V) 9

10 (V BUS = +3.6V, V L = +2.5V, T A = +25NC, unless otherwise noted.) Typical Operating Characteristics (continued) MAX14582 TRANSMITTTING MAX14581 toc1 MAX14582 RECEIVING MAX14581 toc11 EYE DIAGRAM VP 2V/div VM 2V/div 2V/div VP 2V/div VM 2V/div 2V/div, SIGNALS, V MAX14581 toc12 2V/div 2V/div -.5 4ns/div 4ns/div TIME (ns) 7 8 VL SUPPLY CURRENT (µa) LOGIC CURRENT CONSUMPTION IN UPEND MODE VM = VP = OPEN, = = HIGH MAX14581 toc13 VBUS SUPPLY CURRENT (µa) V BUS CURRENT CONSUMPTION IN UPEND MODE VM = VP = OPEN, = = HIGH MAX14581 toc V L (V) V BUS (V) 1

11 Bump Configurations TOP VIEW (BUMP SIDE DOWN) + V L MAX SE DAT BD + MAX V L VM VP RCV A A B B V BUS GND V BUS GND C C WLP WLP Bump Description BUMP MAX14581 NAME MAX14582 FUNCTION A1 V L V L A +1.2V to +3.6V supply is connected to V L. Bypass V L to GND with a. Digital I/O Connections Logic Supply. V L sets the logic level for the interface signal. ceramic capacitor. A2 SE A3 DAT Logic Side Data Input/Output. This pin is an input when is low and an output when is high. As an input, SE is used to output a single-ended zero (SE) on / (when active-high). and are both driven low. As an output, SE goes active-high when both and are low regardless of the status of. (See Tables 3, 4a, and 4b.) Logic Side Data Input/Output. This pin is an input when is low and an output when is high. As an input, DAT acts as the data for the and outputs. As an output DAT is the output of the differential receiver on / ( = ) or the output of the single-ended comparator if = = V L. (See Tables 3, 4a, and 4b.) A4 BD V BUS Detect. This output goes active-high when V BUS is present. B1 B2 Internal Regulator Output. provides a regulated +3.3V output. Bypass to GND with a (min) ceramic capacitor as close as possible to the device. normally derives power from V BUS. Alternatively, both V BUS and can be driven directly with the same +3.3V ±1% voltage supply. Note: In this case V BUS and must be connected to the same supply. provides power to internal circuitry only. It can also be used to power an external pullup resistor, if the application calls for the internal pullup to be disabled. It should not be used to power external circuitry. Enumerate. controls the connection of the pullup resistor. When is low, the pullup is disconnected. When is high, the pullup is connected to. 11

12 Bump Description (continued) BUMP NAME MAX14581 MAX14582 B3 B4 FUNCTION Suspend. When is low, the transceiver operates normally. When is activehigh, the transceiver enters a low-power state. The differential receiver on / is powered down, and RCV outputs low. Output Enable. controls the USB transmitter outputs (, ) and the interface signals VP/VM or DAT/SE. When is high, the interface signals are outputs and / are inputs. When is low, the interface signals are inputs and / are outputs. C1 V BUS V BUS the battery for USB inter-chip applications. V BUS should be a supply in the +3.V to +5.5V range. V BUS provides power to the internal linear regulator. Bypass V BUS to USB Power-Supply Input. V BUS is typically sourced from the USB connector or to GND with a ceramic capacitor as close as possible to the device. C2 C3 USB Input/Output. When is low, functions as a USB output. When is high, functions as a USB input. A 1.5kI resistor is connected between and to indicate full-speed (12Mbps) operation when is high. USB Input/Output. When is low, functions as a USB output. When is high, functions as a USB input. C4 GND GND Ground A2 VM A3 VP A4 RCV Logic Side Data Input/Output. This pin is an input when is low and an output when is high. As an input, VM controls the output. As an output, VM is the output of the single-ended receiver on. VM is output high when V BUS is not present. (See Tables 5 and 6.) Logic Side Data Input/Output. This pin is an input when is low and an output when is high. As an input, VP controls the output. As an output, VP is the output of the single-ended receiver on. VP is output high when V BUS is not present. (See Tables 5 and 6.) Differential Receiver Output. RCV responds to the differential input on and. (See Table 6.) RCV asserts low if = V L. 12

13 Functional Diagrams V L V L BD MAX14581 V BUS MAX14582 V BUS LDO LDO SE DAT LEVEL TRANSLATOR AND LOGIC LEVEL TRANSLATOR AND LOGIC VP VM RCV GND GND Detailed Description The MAX14581/MAX14582 USB-compliant transceivers are designed to minimize the area and external components required to interface low-voltage ASICs to USB. These devices comply with USB 2. specifications for full-speed-only (12Mbps) operation. The transceivers include an internal 3.3V regulator, an internal 1.5kI pullup resistor, and built-in ±15kV ESD protection circuitry to protect the USB I/O ports (, ). The MAX14581/ MAX14582 also have internal series resistors, allowing these devices to be wired directly to a USB connector. These devices operate with logic-supply voltages as low as +1.2V, ensuring compatibility with low-voltage ASICs. A low-power disable mode reduces current consumption to less than 13FA (typ). An enumerate function controls the pullup resistor, allowing devices to logically disconnect while remaining plugged in. The ICs have 36I (typ) internal resistors on / for direct connection to the USB connector. The MAX14581 is equipped with DAT and SE interface signals and supports 3-wire USB transceiver interface. Although the 3-wire interface is commonly associated with USB on-the-go transceivers, the MAX14581 supports USB peripherals only. These transceivers provide a USB V BUS detection function that monitors the presence of USB V BUS and signals the event. 13

14 Interface The MAX14581/MAX14582 control signals are used to control the USB / lines. V L powers the logic-side interface and sets the input and output thresholds of these signals. The control signals for the MAX14581 are DAT, SE, and. The control signals for the MAX14582 are VP, VM, RCV, and. Power-Supply Configuration Normal Operating Mode See Table 1 for various power-supply configurations. V BUS supplies power to the USB transceivers. Connect V BUS to a +3.V to +5.5V supply. Connect V L to a +1.2V to +3.6V supply. V BUS is typically connected directly to the USB connector. An internal regulator provides 3.3V to internal circuitry, and a regulated 3.3V output at, in addition to powering the internal pullup resistor. The ICs can be powered by connecting both V BUS and to the same 3.3V external regulator. V BUS can also be connected directly to a Li+ battery for inter-chip communications, when the transceiver is used for example as the USB analog front-end (AFE) of the 3G modem, used to communicate with the system-on-chip (SOC). Suspend Mode Operate the transceivers in low-power mode by asserting high. In suspend mode, the USB differential receiver is turned off and V BUS consumes less than 18FA of supply current. The single-ended and receivers are still active when driving high. Sharing Mode Connect V L to a system power supply and leave V BUS (or V BUS and ) unconnected or connected to GND. and are three-stated, allowing other circuitry to share the USB and line. V L consumes less than 1FA of supply current. When operating the transceivers in sharing mode, the and inputs are ignored, and the interface signals (SE, DAT, or RCV) are high impedance. Disable Mode Connect V BUS to a system power supply and leave V L unconnected or connect to ground. In disable mode, and are three-stated, and V BUS and/or (or V BUS and ) consume less than 13FA (typ). When operating the transceivers in disable mode,,, and inputs to the interface control signals are according to Table 2a and Table 2b. Table 1. Power-Supply Configuration V BUS (V) (V) V L (V) CONFIGURATION NOTES +3.V to to +3.6 output +1.2 to +3.6V Normal mode +3.V to to +3.6 output GND or unconnected Disable mode Tables 2a, 2b GND or unconnected High impedance +1.2 to +3.6V Sharing mode Tables 2a, 2b Table 2a. Disable Mode and Sharing Mode Connection, 3-Wire Interface INPUTS/OUTPUTS DISABLE MODE SHARING MODE V BUS 3.V to 5.5V Unconnected or connected to GND V L Unconnected or connected to GND 1.2V to 3.6V input and High impedance High impedance DAT, SE High impedance 5kI pullup resistor to V L Unconnected or connected to GND High or low Unconnected or connected to GND High or low BD Low Low 14

15 Table 2b. Disable Mode and Sharing Mode Connection, 5-Wire Interface INPUTS/OUTPUTS DISABLE MODE SHARING MODE V BUS 3.V to 5.5V Unconnected or connected to GND V L Unconnected or connected to GND 1.2V to 3.6V input and High impedance High impedance Unconnected or connected to GND High or low Unconnected or connected to GND High or low VM, VP High impedance 5kI pullup resistor to V L RCV Low Low 3-Wire Interface The MAX14581 uses DAT and SE to drive data or a single-ended zero onto the / lines. When is low, SE is an input and functions as a single-ended zero driver. When SE is high, both and are driven low. When SE is driven low, the / outputs are controlled by DAT. DAT is used to send data on / when both and SE are low. When DAT is high, is driven high and is driven low. When DAT is low, is driven low and is driven high. In receive mode ( = high), DAT is the output of the differential receiver connected to and if = or the putput of the single-ended comparator if = = V L. SE only goes active-high when both and are low. 5-Wire Interface In USB mode, the MAX14582 implements a full-speed (12Mbps) USB interface on and, with enumerate and suspend functions. A differential USB receiver presents the USB state as a logic-level output RCV (Table 6). VP/VM are outputs of single-ended USB receivers when is high, allowing detection of single-ended zero (SE) events. When is low, VP and VM serve as inputs to the USB transmitter. Drive suspend input logic-high to force the MAX14581/MAX14582 into a suspend mode and disable the differential USB receiver (Table 6). Control Signals USB Detection (MAX14581) The MAX14581 USB detection function indicates that V BUS is present. The MAX14581 push-pull bus detection output (BD) monitors V BUS, and asserts high when V BUS and V L are present. BD asserts low if V BUS is less than V TH_VBUS and enters sharing mode. controls the direction of communication when V L and V BUS are both present. For the MAX14581 when is low, DAT and SE operate as logic inputs and /D - are outputs. When is high, DAT and SE operate as logic outputs and / are inputs. For the MAX14582 when is logic-low, VP and VM operate as logic inputs, and / are outputs. When is logic-high, VP and VM operate as logic outputs, and /D are inputs. RCV is the output of the differential USB receiver connected to /, and is not affected by the logic level. determines whether the MAX14581/MAX14582 operate in normal mode or in suspend mode. Drive low for normal operation. Drive high to enable suspend mode. In suspend mode, the single-ended receivers (/) are active to detect a wake-up event. Supply current decreases to less than 18FA (typ) from V BUS in suspend mode. The devices can transmit data on and while in suspend mode. This function is used to signal a remote wake-up event. A 1.5kI pullup resistor on is used to indicate fullspeed (12Mbps) operation. Drive high to connect the internal pullup resistor from to. Drive low to disconnect the internal pullup resistor from to. and and are bidirectional signals and are ESD protected to ±15kV (HBM). controls the direction of and when in USB normal mode. 15

16 An internal linear regulator generates the voltage (+3.3V typ). derives power from V BUS (see the Power-Supply Configuration section). powers the internal USB circuitry and provides the pullup voltage for the internal 1.5kI resistor. Bypass to GND with a ceramic capacitor as close as possible to the device. Do not use to provide power to external circuitry. RCV (MAX14582) RCV is the output of the differential USB receiver. RCV is a logic-high for high and low. RCV is a logic-low for low and high. RCV retains the last valid logic state when and are both low (SE). RCV is driven logic-low when is high. See Table 3, Table 4a, and Table 4b. BD (MAX14581) The V BUS detect (BD) output is asserted high when a voltage greater than V TH-BUS is presented on V BUS. This is typically the case when the MAX14581 is connected to a powered USB. BD is low when V BUS is unconnected. The MAX14582 doesn t have the BD pin. Nevertheless, the status of V BUS is provided by encoding VP and VM as follows: VP = VM = high. Applications Information External Capacitors Use three external capacitors for proper operation. Bypass V L to GND with a. ceramic capacitor. Bypass V BUS to GND with a ceramic capacitor. Bypass to GND with a (min) ceramic or plastic capacitor. Place all capacitors as close as possible to the device. USB Data Transfer Transmitting Data, 3 Wires (MAX14581) The MAX14581 transmit USB data to the USB differentially on and when is low. The and outputs are determined by SE and DAT (see Table 3). Receiving Data, 3 Wires (MAX14581) Drive high and low to receive data on /. Differential data received on and appears at DAT. SE goes high only when both and are low (Table 4a and Table 4b). Table 3. Transmit Truth Table, 3 Wires INPUTS ( = ) Table 4a. Receive Truth Table, 3 Wires, = *Last state. **/ differential receiver output. X = Undefined Table 4b. Receive Truth Table, 3 Wires, = 1 * single-ended receiver output. OUTPUTS DAT SE INPUTS ( = 1, = ) OUTPUTS DAT SE *DAT 1 1 ** 1 **1 1 1 X INPUTS ( = 1, = 1) OUTPUTS DAT SE *1 1 1 *1 16

17 Transmitting Data, 5 Wires To transmit data to the USB, operate the MAX14582 in USB mode (see the Power-Supply Configuration section) and drive low. The MAX14582 transmits data to the USB differentially on and. VP and VM serve as differential input signals to the driver. When VP and VM are both driven low, a single-ended zero (SE) is output on /. Receiving Data, 5 Wires To receive data from the USB, operate the MAX14582 in USB mode (see the Power-Supply Configuration section). Drive high and low. Differential data received at / appears as a logic signal at RCV. VP and VM are the outputs of single-ended receivers on and. Host Usage As a host USB transceiver, the MAX14581/MAX14582 require external 15kI pulldown resistors and connecting = low. ESD Protection The MAX14581/MAX14582 feature ±15kV (HBM) ESD protection on and. The ESD structures withstand high ESD in all states: normal operation, suspend, sharing mode, disable mode, and powered down. V BUS (with a ceramic capacitor) and / are characterized for protection to the following limits: U ±15kV using the Human Body Model Table 5. Transmit Truth Table, 5 Wires ( = ) INPUTS OUTPUTS VP VM Table 6. Receive Truth Table, 5 Wires INPUTS VP VM ( = 1) OUTPUTS RCV ( = ) RCV ( = 1) *RCV X Note: The SE1 condition ( = = 1) is a forbidden condition in the USB protocol. *Last state. X = Undefined. 17

18 R C 5I to 1I CHARGE-CURRENT- LIMIT RESISTOR R D 33I DISCHARGE RESISTANCE ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. HIGH- VOLTAGE DC SOURCE Cs 15pF STORAGE CAPACITOR Figure 8. Human Body ESD Test Model DEVICE UNDER TEST HBM ESD Protection Figure 8 shows the Human Body Model, and Figure 9 shows the current waveform it generates when discharged into a low impedance. This model consists of a 1pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kI resistor. I P 1% 9% I R PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) AMPERES 36.8% 1% t RL TIME t DL CURRENT WAVEFORM Figure 9. Human Body Model Current Waveform 18

19 USB Inter-Chip Typical Application Circuits VOLTAGE SUPPLY BATTERY VOLTAGE SUPPLY VOLTAGE SUPPLY. V L V BUS V BUS V L. MAX14581 MAX14581 BD BD INTERFACE DAT SE DAT SEO INTERFACE 15kI GND GND 15kI VOLTAGE SUPPLY BATTERY VOLTAGE SUPPLY VOLTAGE SUPPLY. V L V BUS V BUS V L. MAX14582 MAX14582 RCV RCV INTERFACE VP VM VP VM INTERFACE 15kI GND GND 15kI 19

20 Ordering Information PART TEMP RANGE PIN-PACKAGE TOP MARK MAX14581EWC+T -4 C to +85 C 12 WLP ACF MAX14582EWC+T -4 C to +85 C 12 WLP ACD +Denotes a lead(pb)-free/rohs-compliant package. T = Tape and reel. Chip Information Package Information PROCESS: BiCMOS For the latest package outline information and land patterns (footprints), go to Note that a +, #, or - in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. 12 WLP W121A LAND PATTERN NO. Refer to Application Note

21 REVISION NUMBER REVISION DATE DESCRIPTION MAX14581/MAX14582 Revision History PAGES CHANGED 6/12 Initial release Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. Maxim Integrated Products, 16 Rio Robles, San Jose, CA Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.