Data Sheet, V1.0, Apr TC Bit Single-Chip Microcontroller TriCore. Microcontrollers

Transcription

1 Data Sheet, V1.0, Apr TC Bit Single-Chip Microcontroller TriCore Microcontrollers

2 Edition Published by Infineon Technologies AG München, Germany Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics ( Beschaffenheitsgarantie ). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of noninfringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office ( Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

3 Data Sheet, V1.0, Apr TC Bit Single-Chip Microcontroller TriCore Microcontrollers

4 TC1762 Data Sheet Revision History: V1.0, Previous Version: V Page Subjects (major changes since last revision) 7 VSSOSC3 is deleted from the TC1762 Logic Symbol. 8, 10 TDATA0 of Pin 17, TCLK0 of Pin 20, TCLK0 of Pin 74 and TDATA0 of Pin 77 are updated in the Pinning Diagram and Pin Definition and Functions Table. 33 Transmit DMA request in Block Diagram of ASC Interfaces is updated. 35 Alternate output functions in block diagram of SSC interfaces are updated. 41 Programmable baud rate of the MLI is updated. 42 TDATA0 and TCLK0 of the block diagram of MLI interfaces are updated. 54 The description for WDT double reset detection is updated. 91 The power sequencing details is updated. 102 MLI timing, maximum operating frequency limit is extended, t31 is added. 106 Thermal resistance junction leads is updated. Trademarks TriCore is a trademark of Infineon Technologies AG. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: mcdocu.comments@infineon.com Data Sheet V1.0,

5 Table of Contents Table of Contents 1 Summary of Features General Device Information Block Diagram Logic Symbol Pin Configuration Pad Driver and Input Classes Overview Pin Definitions and Functions Functional Description System Architecture and On-Chip Bus Systems On-Chip Memories Architectural Address Map Memory Protection System DMA Controller and Memory Checker Interrupt System Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1) High-Speed Synchronous Serial Interface (SSC0) Micro Second Bus Interface (MSC0) MultiCAN Controller (CAN) Micro Link Serial Bus Interface (MLI0) General Purpose Timer Array Functionality of GPTA Analog-to-Digital Converter (ADC0) Fast Analog-to-Digital Converter Unit (FADC) System Timer Watchdog Timer System Control Unit Boot Options Power Management System On-Chip Debug Support Clock Generation and PLL Power Supply Identification Register Values Electrical Parameters General Parameters Parameter Interpretation Pad Driver and Pad Classes Summary Absolute Maximum Ratings Operating Conditions DC Parameters Data Sheet 1 V1.0,

6 Table of Contents Input/Output Pins Analog to Digital Converter (ADC0) Fast Analog to Digital Converter (FADC) Oscillator Pins Temperature Sensor Power Supply Current AC Parameters Testing Waveforms Output Rise/Fall Times Power Sequencing Power, Pad and Reset Timing Phase Locked Loop (PLL) Debug Trace Timing Timing for JTAG Signals Peripheral Timings Micro Link Interface (MLI) Timing Micro Second Channel (MSC) Interface Timing Synchronous Serial Channel (SSC) Master Mode Timing Packaging Package Parameters Package Outline Flash Memory Parameters Quality Declaration Data Sheet 2 V1.0,

7 Summary of Features 1 Summary of Features The TC1762 has the following features: High-performance 32-bit super-scaler TriCore v1.3 CPU with 4-stage pipeline Superior real-time performance Strong bit handling Fully integrated DSP capabilities Single precision Floating Point Unit (FPU) 66 or 80 MHz operation at full temperature range Multiple on-chip memories 32 Kbyte Local Data Memory (SRAM) 4 Kbyte Overlay Memory 8 Kbyte Scratch-Pad RAM (SPRAM) 8 Kbyte Instruction Cache (ICACHE) 1024 Kbyte Flash Memory 16 Kbyte Data Flash (2 Kbyte EEPROM emulation) 16 Kbyte Boot ROM 8-channel DMA Controller Fast-response interrupt system with 255 hardware priority arbitration levels serviced by CPU High-performance on-chip bus structure 64-bit Local Memory Bus (LMB) to Flash memory System Peripheral Bus (SPB) for interconnections of functional units Versatile on-chip Peripheral Units Two Asynchronous/Synchronous Serial Channels (ASCs) with baudrate generator, parity, framing and overrun error detection One High Speed Synchronous Serial Channel (SSC) with programmable data length and shift direction One Micro Second Bus (MSC) interface for serial port expansion to external power devices One high-speed Micro Link Interface (MLI) for serial inter-processor communication One MultiCAN Module with two CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer One General Purpose Timer Array Module (GPTA) with a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management One 16-channel Analog-to-Digital Converter unit (ADC) with selectable 8-bit, 10- bit, or 12-bit, supporting 32 input channels One 2-channel Fast Analog-to-Digital Converter unit (FADC) with concatenated comb filters for hardware data reduction: supporting 10-bit resolution, with minimum conversion time of 262.5ns (@ 80 MHz) or 318.2ns (@ 66 MHz) Data Sheet 3 V1.0,

8 Summary of Features 32 analog input lines for ADC and FADC 81 digital general purpose I/O lines Digital I/O ports with 3.3 V capability On-chip debug support for OCDS Level 1 and 2 (CPU, DMA) Dedicated Emulation Device chip for multi-core debugging, tracing, and calibration via USB V1.1 interface available (TC1766ED) Power Management System Clock Generation Unit with PLL Core supply voltage of 1.5 V I/O voltage of 3.3 V Full automotive temperature range: -40 to +125 C PG-LQFP package Data Sheet 4 V1.0,

9 Summary of Features Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: The derivative itself, i.e. its function set, the temperature range, and the supply voltage The package and the type of delivery For the available ordering codes for the TC1762, please refer to the Product Catalog Microcontrollers that summarizes all available microcontroller variants. This document describes the derivatives of the device.the Table 1-1 enumerates these derivatives and summarizes the differences. Table 1-1 TC1762 Derivative Synopsis Derivative Ambient Temperature Range SAK-TC F66HL T A = -40 o C to +125 o C; 66 MHz operation frequency SAK-TC F80HL T A = -40 o C to +125 o C; 80 MHz operation frequency Data Sheet 5 V1.0,

10 General Device Information 2 General Device Information Chapter 2 provides the general information for the TC Block Diagram Figure 2-1 shows the TC1762 block diagram. PMI 8 KB SPRAM 8 KB ICACHE FPU TriCore (TC1.3M) DMI 32 KB LDRAM PMU 16 KB BROM 1024 KB Pflash 16 KB DFlash 4 KB OVRAM Overlay Me chan ism CPS LFI Bridge Local Memory Bus (LMB) LBCU Abbreviations: ICACHE: Instruction Cache SPRAM: Scratch-Pad RAM LDRAM: Local Data RAM OVRAM: Overlay RAM BROM: Boot ROM PFlash: Program Flash DFlash: Data Flash LMB: Local Memory Bus SPB: System Peripheral Bus OCDS Debug Interface/JTAG STM ASC0 ASC1 GPTA System Peripheral Bus (SPB) Ext. Request Unit SCU PLL Multi CAN (2 Nodes, 64 Buffer) f FP I f CPU MSC0 BI0 SBCU Ports DMA 8 ch. SMIF BI1 DMA Bus SSC0 ADC0 32 ch. FADC 2 ch. Analog Input Assignment MLI0 Mem Check MCB06056 Figure 2-1 TC1762 Block Diagram Data Sheet 6 V1.0,

11 General Device Information 2.2 Logic Symbol Figure 2-2 shows the TC1762 logic symbol. Alternate Functions General Control PORST HDRST NMI BYPASS TESTMODE Port 0 16-bit Port 1 15-bit Port 2 14-bit GPTA, SCU GPTA, ADC SSC0, MLI0, GPTA, MSC0 MSC0 Control FCLP 0A FCLN0 SOP0A SON0 Port 3 16-bit Port 4 4-bit ASC0/1, SSC0, SCU, CAN GPTA, SCU ADC Analog Inputs AN[35:0] Port 5 16-bit GPTA, OCDS L 2, MLI0 ADC/FADC Analog Power Supply V DDM V SSM V DDMF V SSMF V DDAF V SSAF V AREF0 V AGND0 V FAREF V FAGND TC1762 TRST TCK TDI TDO TMS BRKIN BRKOUT TRCLK XTAL1 XTAL2 OCDS / JTAG Control Digital Circuitry Power Supply V DDFL3 V DD V DDP V SS V DDOSC3 V DDOSC V SSOSC Oscillator MCB06066 Figure 2-2 TC1762 Logic Symbol Data Sheet 7 V1.0,

12 General Device Information Data Sheet 8 V1.0, Pin Configuration Figure 2-3 shows the TC1762 pin configuration. Figure 2-3 TC1762 Pinning for PG-LQFP Package P0.0/IN0/SWCFG0/OUT0/OUT56 P0.1/IN1/SWCFG1/OUT1/OUT57 P0.2/IN2/SWCFG2/OUT2/OUT58 P0.3/IN3/SWCFG3/OUT3/OUT59 P0.4/IN4/SWCFG4/OUT4/OUT60 P0.5/IN5/SWCFG5/OUT5/OUT61 P0.6/IN6/SWCFG6/REQ2/OUT6/OUT62 P0.7/IN7/SWCFG7/REQ3/OUT7/OUT63 P0.8/IN8/SWCFG8/OUT8/OUT64 P0.9/IN9/SWCFG9/OUT9/OUT65 P0.10/IN10/SWCFG10/OUT10/OUT66 P0.11/IN11/SWCFG11/OUT11/OUT67 P0.12/IN12/SWCFG12/OUT12/OUT68 P0.13/IN13/SWCFG13/OUT13/OUT69 P0.14/IN14/SWCFG14/REQ4/OUT14/OUT70 P0.15/IN15/SWCFG15/REQ5/OUT15/OUT71 P1.0/IN16/OUT16/OUT72 P1.1/IN17/OUT17/OUT73 P1.2/IN18/OUT18/OUT74 P1.3/IN19/OUT19/OUT75 P1.4/IN20/EMG_IN/OUT20/OUT76 P1.5/IN21/OUT21/OUT77 P1.6/IN22/OUT22/OUT78 P1.7/IN23/OUT23/OUT79 P1.8/IN24/IN48/OUT24/OUT48 P1.9/IN25/IN49/OUT25/OUT49 P1.10/IN26/IN50/OUT26/OUT50 P1.11/IN27/IN51/OUT27/OUT51 AD0EMUX0/P1.12 AD0EMUX1/P1.13 AD0EMUX2/P1.14 TCLK0/OUT32/IN32/P2.0 SLSO03/OUT33/TREADY0A/IN33/P2.1 TVALID0A/OUT34/IN34/P2.2 TDATA0/OUT35/IN35/P2.3 OUT36/RCLK0A/IN36/P2.4 RREADY0A/OUT37/IN37/P2.5 OUT38/RVALID0A/IN38/P2.6 OUT39/RDATA0A/IN39/P2.7 P2.8/SLSO04/EN00 P2.9/SLSO05/EN01 P2.10/GPIO P2.11/FCLP0B P2.12/SOP0B P2.13/SDI0 P3.0/RXD0A P3.1/TXD0A P3.2/SCLK0 P3.3/MRST0 P3.4/MTSR0 P3.5/SLSO00/SLSO00 P3.6/SLSO01/SLSO01 P3.7/SLSI0/SLSO02 P3.8/SLSO06/TXD1A P3.9/RXD1A P3.10/REQ0 P3.11/REQ1 P3.12/RXDCAN0/RXD0B P3.13/TXDCAN0/TXD0B P3.14/RXDCAN1/RXD1B P3.15/TXDCAN1/TXD1B OUT52/OUT28/HWCFG0/IN52/IN28/P4.0 OUT53/OUT29/HWCFG1/IN53/IN29/P4.1 OUT54/OUT30/HWCFG2/IN54/IN30/P4.2 P4.3/IN31/IN55/OUT31/OUT55/SYSCLK OCDSDBG0/OUT40/IN40/P5.0 OCDSDBG1/OUT41/IN41/P5.1 OCDSDBG2/OUT42/IN42/P5.2 OCDSDBG4/OUT44/IN44/P5.4 OCDSDBG3/OUT43/IN43/P5.3 OCDSDBG5/OUT45/IN45/P5.5 OCDSDBG6/OUT46/IN46/P5.6 OCDSDBG7/OUT47/IN47/P5.7 OCDSDBG8/RDATA0B/P5.8 OCDSDBG9/RVALID0B/P5.9 OCDSDBG10/RREADY0B/P5.10 OCDSDBG11/RCLK0B/P5.11 OCDSDBG12/TDATA0/P5.12 OCDSDBG13/TVALID0B/P5.13 OCDSDBG14/TREADY0B/P5.14 OCDSDBG15/TCLK0/P5.15 FCLP0A FCLN0 SOP0A SON0 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN8 AN7 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 TRST TCK TDI TDO TMS BRKIN BRKOUT NMI HDRST PORST BYPASS TESTMODE XTAL1 XTAL2 VDD VDDP VSS N.C. N.C. TRCLK TC1762 VDD VDDP VSS VDDMF VSSMF VDDAF VSSAF VFAREF VFAGND VDDM VSSM VAREF0 VAGND0 VDD VDDP VSS VDD VDDP VSS VSS VDD VDDP VSS VDDOSC VDDOSC3 VSSOSC VDDFL3 VDDP VSS VDD VDDP VSS VDD VDDP VSS MCP06067

13 General Device Information 2.4 Pad Driver and Input Classes Overview The TC1762 provides different types and classes of input and output lines. For understanding of the abbreviations in Table 2-1 starting at the next page, Table 4-1 gives an overview on the pad type and class types. Data Sheet 9 V1.0,

14 General Device Information 2.5 Pin Definitions and Functions Table 2-1 shows the TC1762 pin definitions and functions. Table 2-1 Pin Definitions and Functions Symbol Pins I/O Pad Driver Class Power Supply Functions Parallel Ports P0 I/O A1 V DDP Port 0 Port 0 is a 16-bit bi-directional generalpurpose I/O port which can be alternatively used for GPTA I/O lines or external trigger inputs. P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P0.8 P0.9 P0.10 P0.11 P0.12 P0.13 P0.14 P IN0 / OUT0 / IN1 / OUT1 / IN2 / OUT2 / IN3 / OUT3 / IN4 / OUT4 / IN5 / OUT5 / IN6 / OUT6 / REQ2 IN7 / OUT7 / REQ3 IN8 / OUT8 / IN9 / OUT9 / IN10 / OUT10 / IN11 / OUT11 / IN12 / OUT12 / IN13 / OUT13 / IN14 / OUT14 / REQ4 IN15 / OUT15 / REQ5 OUT56 line of GPTA OUT57 line of GPTA OUT58 line of GPTA OUT59 line of GPTA OUT60 line of GPTA OUT61 line of GPTA OUT62 line of GPTA External trigger input 2 OUT63 line of GPTA External trigger input 3 OUT64 line of GPTA OUT65 line of GPTA OUT66 line of GPTA OUT67 line of GPTA OUT68 line of GPTA OUT69 line of GPTA OUT70 line of GPTA External trigger input 4 OUT71 line of GPTA External trigger input 5 In addition, the state of the port pins are latched into the software configuration input register SCU_SCLIR at the rising edge of HDRST. Therefore, Port 0 pins can be used for operating mode selections by software. Data Sheet 10 V1.0,

15 General Device Information Table 2-1 Pin Definitions and Functions (cont d) Symbol Pins I/O Pad Driver Class Power Supply Functions P1 I/O V DDP Port 1 Port 1 is a 15-bit bi-directional general purpose I/O port which can be alternatively used for GPTA I/O lines and ADC0 interface. P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P1.8 P1.9 P1.10 P1.11 P1.12 P1.13 P A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 IN16 / OUT16 / IN17 / OUT17 / IN18 / OUT18 / IN19 / OUT19 / IN20 / OUT20 / IN21 / OUT21 / IN22 / OUT22 / IN23 / OUT23 / IN24 / OUT24 / IN25 / OUT25 / IN26 / OUT26 / IN27 / OUT27 / AD0EMUX0 AD0EMUX1 AD0EMUX2 OUT72 line of GPTA OUT73 line of GPTA OUT74 line of GPTA OUT75 line of GPTA OUT76 line of GPTA OUT77 line of GPTA OUT78 line of GPTA OUT79 line of GPTA IN48 / OUT48 line of GPTA IN49 / OUT49 line of GPTA IN50 / OUT50 line of GPTA IN51 / OUT51 line of GPTA ADC0 external multiplexer control output 0 ADC0 external multiplexer control output 1 ADC0 external multiplexer control output 2 In addition, P1.4 also serves as emergency shut-off input for certain I/O lines (e.g. GPTA related outputs). Data Sheet 11 V1.0,

16 General Device Information Table 2-1 Pin Definitions and Functions (cont d) Symbol Pins I/O Pad Driver Class Power Supply Functions P2 I/O V DDP Port 2 Port 2 is a 14-bit bi-directional generalpurpose I/O port which can be alternatively used for GPTA I/O, and interface for MLI0, MSC0 or SSC0. P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P A1 A1 A1 TCLK0 IN32 / OUT32 TREADY0A IN33 / OUT33 SLSO03 TVALID0A IN34 / OUT34 TDATA0 IN35 / OUT35 RCLK0A IN36 / OUT36 RREADY0A IN37 / OUT37 RVALID0A IN38 / OUT38 RDATA0A IN39 / OUT39 MLI0 transmit channel clock output A line of GPTA MLI0 transmit channel ready input A line of GPTA SSC0 slave select output 3 MLI0 transmit channel valid output A line of GPTA MLI0 transmit channel data output A line of GPTA MLI0 receive channel clock input A line of GPTA MLI0 receive channel ready output A line of GPTA MLI0 receive channel valid input A line of GPTA MLI0 receive channel data input A line of GPTA Data Sheet 12 V1.0,

17 Table 2-1 Pin Definitions and Functions (cont d) Symbol Pins I/O Pad Driver Class Power Supply Functions P2.8 P2.9 P2.10 P2.11 P2.12 P A1 SLSO04 EN00 SLSO05 EN01 FCLP0B SOP0B SDI0 General Device Information SSC0 Slave Select output 4 MSC0 enable output 0 SSC0 Slave Select output 5 MSC0 enable output 1 MSC0 clock output B MSC0 serial data output B MSC0 serial data input Data Sheet 13 V1.0,

18 General Device Information Table 2-1 Pin Definitions and Functions (cont d) Symbol Pins I/O Pad Driver Class Power Supply Functions P3 I/O V DDP Port 3 Port 3 is a 16-bit bi-directional generalpurpose I/O port which can be alternatively used for ASC0/1, SSC0 and CAN lines. P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12 P3.13 P3.14 P A1 A1 RXD0A TXD0A ASC0 receiver inp./outp. A ASC0 transmitter output A This pin is sampled at the rising edge of PORST. If this pin and the BYPASS input pin are both active, then oscillator bypass mode is entered. SCLK0 MRST0 MTSR0 SLSO00 SLSO01 SLSI0 SLSO02 SLSO06 TXD1A RXD1A REQ0 REQ1 RXDCAN0 RXD0B TXDCAN0 TXD0B RXDCAN1 RXD1B TXDCAN1 TXD1B SSC0 clock input/output SSC0 master receive input/ slave transmit output SSC0 master transmit output/slave receive input SSC0 slave select output 0 SSC0 slave select output 1 SSC0 slave select input SSC0 slave select output 2 SSC0 slave select output 6 ASC1 transmitter output A ASC1 receiver inp./outp. A External trigger input 0 External trigger input 1 CAN node 0 receiver input ASC0 receiver inp./outp. B CAN node 0 transm. output ASC0 transmitter output B CAN node 1 receiver input ASC1 receiver inp./outp. B CAN node 1 transm. output ASC1 transmitter output B Data Sheet 14 V1.0,

19 General Device Information Table 2-1 Pin Definitions and Functions (cont d) Symbol Pins I/O Pad Driver Class Power Supply Functions P4 I/O V DDP Port 4 / Hardware Configuration Inputs P4.[3:0] HWCFG[3:0] Boot mode and boot location inputs; inputs are latched with the rising edge of HDRST. During normal operation, Port 4 pins may be used as alternate functions for GPTA or system clock output. P4.0 P4.1 P4.2 P A1 A1 IN28 / OUT28 / IN29 / OUT29 / IN30 / OUT30 / IN31 / OUT31 / SYSCLK IN52 / OUT52 line of GPTA IN53 / OUT53 line of GPTA IN54 / OUT54 line of GPTA IN55 / OUT55 line of GPTA System Clock Output Data Sheet 15 V1.0,

20 General Device Information Table 2-1 Pin Definitions and Functions (cont d) Symbol Pins I/O Pad Driver Class Power Supply Functions P5 I/O V DDP Port 5 Port 5 is a 16-bit bi-directional generalpurpose I/O port. In emulation, it is used as a trace port for OCDS Level 2 debug lines. In normal operation, it is used for GPTA I/O or the MLI0 interface. P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P OCDSDBG0 IN40 / OUT40 OCDSDBG1 IN41 / OUT41 OCDSDBG2 IN42 / OUT42 OCDSDBG3 IN43 / OUT43 OCDSDBG4 IN44 / OUT44 OCDSDBG5 IN45 / OUT45 OCDSDBG6 IN46 / OUT46 OCDSDBG7 IN47 / OUT47 OCDS L2 Debug Line 0 (Pipeline Status Sig. PS0) line of GPTA OCDS L2 Debug Line 1 (Pipeline Status Sig. PS1) line of GPTA OCDS L2 Debug Line 2 (Pipeline Status Sig. PS2) line of GPTA OCDS L2 Debug Line 3 (Pipeline Status Sig. PS3) line of GPTA OCDS L2 Debug Line 4 (Pipeline Status Sig. PS4) line of GPTA OCDS L2 Debug Line 5 (Break Qualification Line BRK0) line of GPTA OCDS L2 Debug Line 6 (Break Qualification Line BRK1) line of GPTA OCDS L2 Debug Line 7 (Break Qualification Line BRK2) line of GPTA Data Sheet 16 V1.0,

21 Table 2-1 Pin Definitions and Functions (cont d) Symbol Pins I/O Pad Driver Class Power Supply Functions P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P OCDSDBG8 RDATA0B OCDSDBG9 RVALID0B OCDSDBG10 RREADY0B OCDSDBG11 RCLK0B OCDSDBG12 TDATA0 OCDSDBG13 TVALID0B OCDSDBG14 TREADY0B OCDSDBG15 TCLK0 General Device Information OCDS L2 Debug Line 8 (Indirect PC Addr. PC0) MLI0 receive channel data input B OCDS L2 Debug Line 9 (Indirect PC Addr. PC1) MLI0 receive channel valid input B OCDS L2 Debug Line 10 (Indirect PC Addr. PC2) MLI0 receive channel ready output B OCDS L2 Debug Line 11 (Indirect PC Addr. PC3) MLI0 receive channel clock input B OCDS L2 Debug Line 12 (Indirect PC Addr. PC04) MLI0 transmit channel data output B OCDS L2 Debug Line 13 (Indirect PC Addr. PC05) MLI0 transmit channel valid output B OCDS L2 Debug Line 14 (Indirect PC Address PC6) MLI0 transmit channel ready input B OCDS L2 Debug Line 15 (Indirect PC Address PC7) MLI0 transmit channel clock output B Data Sheet 17 V1.0,

22 General Device Information Table 2-1 Pin Definitions and Functions (cont d) Symbol Pins I/O Pad Driver Class Power Supply Functions MSC0 Outputs FCLP0A FCLN0 SOP0A SON O O O O C V DDP LVDS MSC Clock and Data Outputs 2) MSC0 Differential Driver Clock Output Positive A MSC0 Differential Driver Clock Output Negative MSC0 Differential Driver Serial Data Output Positive A MSC0 Differential Driver Serial Data Output Negative Data Sheet 18 V1.0,

23 General Device Information Table 2-1 Pin Definitions and Functions (cont d) Symbol Pins I/O Pad Driver Class Power Supply Functions Analog Inputs AN[35:0] AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN I D Analog Input Port The Analog Input Port provides altogether 36 analog input lines to ADC0 and FADC. AN[31:0]: ADC0 analog inputs [31:0] AN[35:32]: FADC analog differential inputs Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5 Analog input 6 Analog input 7 Analog input 8 Analog input 9 Analog input 10 Analog input 11 Analog input 12 Analog input 13 Analog input 14 Analog input 15 Analog input 16 Analog input 17 Analog input 18 Analog input 19 Analog input 20 Analog input 21 Analog input 22 Analog input 23 Analog input 24 Analog input 25 Analog input 26 Analog input 27 Analog input 28 Analog input 29 Analog input 30 Data Sheet 19 V1.0,

24 General Device Information Table 2-1 Pin Definitions and Functions (cont d) Symbol Pins I/O Pad Driver Class Power Supply Functions AN31 AN32 AN33 AN34 AN I D Analog input 31 Analog input 32 Analog input 33 Analog input 34 Analog input 35 System I/O TRST 114 I 1) V DDP JTAG Module Reset/Enable Input TCK 115 I 1) V DDP JTAG Module Clock Input TDI 111 I A1 1) V DDP JTAG Module Serial Data Input TDO 113 O V DDP JTAG Module Serial Data Output TMS 112 I 1) V DDP JTAG Module State Machine Control Input BRKIN 117 I/O A3 V DDP OCDS Break Input (Alternate Output) 2)3) BRK OUT 116 I/O A3 V DDP OCDS Break Output (Alternate Input) 2)3) TRCLK 9 O A4 V DDP Trace Clock for OCDS_L2 Lines 2) NMI 120 I 4)5) V DDP Non-Maskable Interrupt Input HDRST 122 I/O 6) V DDP Hardware Reset Input / Reset Indication Output PORST 7) 121 I 4) V DDP Power-on Reset Input BYPASS 119 I A1 1) V DDP PLL Clock Bypass Select Input This input has to be held stable during poweron resets. With BYPASS = 1, the spike filters in the HDRST, PORST and NMI inputs are switched off. TEST MODE XTAL1 XTAL2 118 I 4)8) V DDP Test Mode Select Input For normal operation of the TC1762, this pin should be connected to high level N.C. 21, 89 I O n.a. V DDOSC Oscillator/PLL/Clock Generator Input/Output Pins Not Connected These pins are reserved for future extension and must not be connected externally. Data Sheet 20 V1.0,

25 General Device Information Table 2-1 Pin Definitions and Functions (cont d) Symbol Pins I/O Pad Driver Class Power Supply Functions Power Supplies V DDM 54 ADC Analog Part Power Supply (3.3 V) V SSM 53 ADC Analog Part Ground for V DDM V DDMF 24 FADC Analog Part Power Supply (3.3 V) V SSMF 25 FADC Analog Part Ground for V DDMF V DDAF 23 FADC Analog Part Logic Power Supply (1.5 V) V SSAF 22 FADC Analog Part Logic Ground for V DDAF V AREF0 52 ADC Reference Voltage V AGND0 51 ADC Reference Ground V FAREF 26 FADC Reference Voltage V FAGND 27 FADC Reference Ground V DDOSC 105 Main Oscillator and PLL Power Supply (1.5 V) V DDOSC3 106 Main Oscillator Power Supply (3.3 V) V SSOSC 104 Main Oscillator and PLL Ground V DDFL3 141 Power Supply for Flash (3.3 V) V DD 10, 68, 84, 99, 123, 153, 170 Core Power Supply (1.5 V) Data Sheet 21 V1.0,

26 General Device Information Table 2-1 Symbol Pins I/O Pad Driver Class V DDP 11, 69, 83, 100, 124, 154, 171, 139 V SS 12, 70, 85, 101, 125, 155, 172, 140, 82 Pin Definitions and Functions (cont d) Power Supply Functions Port Power Supply (3.3 V) Ground 1) These pads are I/O pads with input only function. Its input characteristics are identical with the input characteristics as defined for class A pads. 2) In case of a power-fail condition (one or more power supply voltages drop below the specified voltage range), an undefined output driving level may occur at these pins. 3) Programmed by software as either break input or break output. 4) These pads are input only pads with input characteristics. 5) Input only pads with input spike filter. 6) Open drain pad with input spike filter. 7) The dual input reset system of TC1762/TC1766ED, assumes that the PORST reset pin is used for power-on reset only. It has to be taken into account that if a system uses the PORST reset input for other system resets, the emulation part of the TC1766ED Emulation Device is reset as well. Thus, it will always force a complete re-initialization of the emulator and will prevent the user debugging across these types of resets. 8) Input only pads without input spike filter. Data Sheet 22 V1.0,

27 General Device Information Table 2-2 List of Pull-up/Pull-down Reset Behavior of the Pins Pins PORST = 0 PORST = 1 All GPIOs, TDI, TMS, TDO Pull-up HDRST Drive-low Pull-up BYPASS Pull-up High-impedance TRST, TCK High-impedance Pull-down TRCLK High-impedance BRKIN, BRKOUT, TESTMODE Pull-up NMI, PORST Pull-down Data Sheet 23 V1.0,

28 Functional Description 3 Functional Description Chapter 3 provides an overview of the TC1762 functional description. 3.1 System Architecture and On-Chip Bus Systems The TC1762 has two independent on-chip buses (see also TC1762 block diagram on Page 2-6): Local Memory Bus (LMB) System Peripheral Bus (SPB) The LMB Bus connects the CPU local resources for data and instruction fetch. The Local Memory Bus interconnects the memory units and functional units, such as CPU and PMU. The main target of the LMB bus is to support devices with fast response times, optimized for speed. This allows the DMI and PMI fast access to local memory and reduces load on the FPI bus. The Tricore system itself is located on LMB bus. The Local Memory Bus is a synchronous, pipelined, split bus with variable block size transfer support. It supports 8-, 16-, 32- and 64-bit single transactions and variable length 64-bit block transfers. The SPB Bus is accessible to the CPU via the LMB Bus bridge. The System Peripheral Bus (SPB Bus) in TC1762 is an on-chip FPI Bus. The FPI Bus interconnects the functional units of the TC1762, such as the DMA and on-chip peripheral components. The FPI Bus is designed to be quick to be acquired by on-chip functional units, and quick to transfer data. The low setup overhead of the FPI Bus access protocol guarantees fast FPI Bus acquisition, which is required for time-critical applications.the FPI Bus is designed to sustain high transfer rates. For example, a peak transfer rate of up to 320 Mbyte/s can be achieved with a 80 MHz bus clock and 32-bit data bus. With a 66 MHz bus clock, the peak transfer rate is up to 264 Mbytes/s. Multiple data transfers per bus arbitration cycle allow the FPI Bus to operate at close to its peak bandwidth. Both the LMB Bus and the SPB Bus runs at full CPU speed. The maximum CPU speed is 66 or 80 MHz depending on the derivative. Additionally, two simplified bus interfaces are connected to and controlled by the DMA Controller: DMA Bus SMIF Interface Data Sheet 24 V1.0,

29 Functional Description 3.2 On-Chip Memories As shown in the TC1762 block diagram on Page 2-6, some of the TC1762 units provide on-chip memories that are used as program or data memory. Program memory in PMU 16 Kbyte Boot ROM (BROM) 1024 Kbyte Program Flash (PFlash) Program memory in PMI 8 Kbyte Scratch-Pad RAM (SPRAM) 8 Kbyte Instruction Cache (ICACHE) Data memory in PMU 16 Kbyte Data Flash (DFlash) 4 Kbyte Overlay RAM (OVRAM) Data memory in DMI 32 Kbyte Local Data RAM (LDRAM) On-chip SRAM with parity error protection Features of Program Flash 1024 Kbyte on-chip program Flash memory Usable for instruction code or constant data storage 256-byte program interface 256 bytes are programmed into PFLASH page in one step/command 256-bit read interface Transfer from PFLASH to CPU/PMI by four 64-bit single cycle burst transfers Dynamic correction of single-bit errors during read access Detection of double-bit errors Fixed sector architecture Eight 16 Kbyte, one 128 Kbyte, one 256 Kbyte and one 512 Kbyte sectors Each sector separately erasable Each sector separately write-protectable Configurable read protection for complete PFLASH with sophisticated read access supervision, combined with write protection for complete PFLASH (protection against Trojan horse software) Configurable write protection for each sector Each sector separately write-protectable With capability to be re-programmed With capability to be locked forever (OTP) Password mechanism for temporary disabling of write and read protection On-chip generation of programming voltage JEDEC-standard based command sequences for PFLASH control Write state machine controls programming and erase operations Status and error reporting by status flags and interrupt Margin check for detection of problematic PFLASH bits Data Sheet 25 V1.0,

30 Functional Description Features of Data Flash 16 Kbyte on-chip data Flash memory, organized in two 8 Kbyte banks Usable for data storage with EEPROM functionality 128 Byte of program interface 128 bytes are programmed into one DFLASH page by one step/command 64-bit read interface (no burst transfers) Dynamic correction of single-bit errors during read access Detection of double-bit errors Fixed sector architecture Two 8 Kbyte banks/sectors Each sector separately erasable Configurable read protection (combined with write protection) for complete DFLASH together with PFLASH read protection Password mechanism for temporary disabling of write and read protection Erasing/programming of one bank possible while reading data from the other bank Programming of one bank while erasing the other bank possible On-chip generation of programming voltage JEDEC-standard based command sequences for DFLASH control Write state machine controls programming and erase operations Status and error reporting by status flags and interrupt Margin check for detection of problematic DFLASH bits Data Sheet 26 V1.0,

31 Functional Description 3.3 Architectural Address Map Table 3-1 shows the overall architectural address map as defined for the TriCore and as implemented in TC1762. Table 3-1 TC1762 Architectural Address Map Segment Contents Size Description 0-7 Global 8 x 256 Mbyte Reserved (MMU space); cached 8 Global Memory 9 Global Memory 10 Global Memory 11 Global Memory 12 Local LMB Memory 256 Mbyte Reserved (246 Mbyte); PMU, Boot ROM; cached 256 Mbyte FPI space; cached 256 Mbyte Reserved (246 Mbyte), PMU, Boot ROM; noncached 256 Mbyte FPI space; non-cached 256 Mbyte Reserved; bottom 4 Mbyte visible from FPI bus in segment 14; cached 13 DMI 64 Mbyte Local Data Memory RAM; non-cached PMI 64 Mbyte Local Code Memory RAM; non-cached EXT_PER 96 Mbyte Reserved; non-cached EXT_EMU 16 Mbyte Reserved; non-cached BOOTROM 16 Mbyte Boot ROM space, Boot ROM mirror; non-cached 14 EXTPER 128 Mbyte Reserved; non-speculative; non-cached; no execution CPU[0..15] image region 15 LMB_PER CSFRs INT_PER 16 x 8 Mbyte 256 Mbyte Non-speculative; non-cached; no execution CSFRs of CPUs[0..15]; LMB & FPI Peripheral Space; non-speculative; non-cached; no execution Data Sheet 27 V1.0,

32 Functional Description 3.4 Memory Protection System The TC1762 memory protection system specifies the addressable range and read/write permissions of memory segments available to the current executing task. The memory protection system controls the position and range of addressable segments in memory. It also controls the types of read and write operations allowed within addressable memory segments. Any illegal memory access is detected by the memory protection hardware, which then invokes the appropriate Trap Service Routine (TSR) to handle the error. Thus, the memory protection system protects critical system functions against both software and hardware errors. The memory protection hardware can also generate signals to the Debug Unit to facilitate tracing illegal memory accesses. There are two Memory Protection Register Sets in the TC1762, numbered 0 and 1, which specify memory protection ranges and permissions for code and data. The PSW.PRS bit field determines which of these is the set currently in use by the CPU. As the TC1762 uses a Harvard-style memory architecture, each Memory Protection Register Set is broken down into a Data Protection Register Set and a Code Protection Register Set. Each Data Protection Register Set can specify up to four address ranges to receive a particular protection modes. Each Code Protection Register Set can specify up to two address ranges to receive a particular protection modes. Each Data Protection Register Sets and Code Protection Register Sets determines the range and protection modes for a separate memory area. Each set contains a pair of registers which determine the address range (the Data Segment Protection Registers and Code Segment Protection Registers) and one register (Data Protection Mode Register) which determines the memory access modes that applies to the specified range. Data Sheet 28 V1.0,

33 Functional Description 3.5 DMA Controller and Memory Checker The DMA Controller of the TC1762 transfers data from data source locations to data destination locations without intervention of the CPU or other on-chip devices. One data move operation is controlled by one DMA channel. Eight DMA channels are provided in one DMA Sub-Block. The Bus Switch provides the connection of the DMA Sub-Block to the two FPI Bus interfaces and an MLI bus interface. In the TC1762, the FPI Bus interfaces are connected to the System Peripheral Bus and the DMA Bus. The third specific bus interface provides a connection to the Micro Link Interface module (MLI0 in the TC1762) and other DMA-related devices (Memory Checker module in the TC1762). Clock control, address decoding, DMA request wiring, and DMA interrupt service request control are implementation-specific and managed outside the DMA controller kernel. Figure 3-1 shows the implementation details and interconnections of the DMA module. Clock Control f DMA DMA Controller DMA Requests of On-chip Periph. Units DMA Sub-Block 0 Request CH0n_OUT Selection/ Arbitration DMA Channels Transaction Control Unit Bus Switch FPI Bus Interface 0 FPI Bus Interface 1 System Periphera Bus DMA Bus Address Decoder MLI Interfac e MLI0 Memory Checker Interrupt Request Nodes SR[15:0] DMA Interrupt Control Arbiter/ Switch Control MCB06149 Figure 3-1 DMA Controller Block Diagram Features 8 independent DMA channels Data Sheet 29 V1.0,

34 Functional Description 8 DMA channels in the DMA Sub-Block Up to 8 selectable request inputs per DMA channel 2-level programmable priority of DMA channels within the DMA Sub-Block Software and hardware DMA request Hardware requests by selected on-chip peripherals and external inputs Programmable priority of the DMA Sub-Blocks on the bus interfaces Buffer capability for move actions on the buses (at least 1 move per bus is buffered). Individually programmable operation modes for each DMA channel Single Mode: stops and disables DMA channel after a predefined number of DMA transfers Continuous Mode: DMA channel remains enabled after a predefined number of DMA transfers; DMA transaction can be repeated. Programmable address modification Full 32-bit addressing capability of each DMA channel 4 Gbyte address range Support of circular buffer addressing mode Programmable data width of DMA transfer/transaction: 8-bit, 16-bit, or 32-bit Micro Link bus interface support Register set for each DMA channel Source and destination address register Channel control and status register Transfer count register Flexible interrupt generation (the service request node logic for the MLI channels is also implemented in the DMA module) All buses connected to the DMA module must work at the same frequency. Read/write requests of the System Bus side to the peripherals on DMA Bus are bridged to the DMA Bus (only the DMA is the master on the DMA bus), allowing easy access to these peripherals by CPU Memory Checker The Memory Checker Module (MCHK) makes it possible to check the data consistency of memories. Any SPB bus master may access the memory checker. It is preferable the DMA does it as described hereafter. It uses DMA 8-bit, 16-bit, or 32-bit moves to read from the selected address area and to write the value read in a memory checker input register. With each write operation to the memory checker input register, a polynomial checksum calculation is triggered and the result of the calculation is stored in the memory checker result register. The memory checker uses the standard Ethernet polynomial, which is given by: G 32 = x 32 + x 26 + x 23 + x 22 + x 16 + x 12 + x 11 + x 10 + x 8 + x 7 + x 5 + x 4 + x 2 + x +1 Note: Although the polynomial above is used for generation, the generation algorithm differs from the one that is used by the Ethernet protocol. Data Sheet 30 V1.0,

35 Functional Description 3.6 Interrupt System The TC1762 interrupt system provides a flexible and time-efficient means of processing interrupts. An interrupt request is serviced by the CPU, which is called the Service Provider. Interrupt requests are called Service Requests rather than Interrupt Requests in this document. Each peripheral in the TC1762 can generate service requests. Additionally, the Bus Control Units, the Debug Unit, and even the CPU itself can generate service requests to the Service Provider. As shown in Figure 3-2, each TC1762 unit that can generate service requests is connected to one or multiple Service Request Nodes (SRN). Each SRN contains a Service Request Control Register mod_srcx, where mod is the identifier of the service requesting unit and x an optional index. The CPU Interrupt Arbitration Bus connects the SRNs with the Interrupt Control Unit (ICU), which arbitrates service requests for the CPU and administers the CPU Interrupt Arbitration Bus. The Debug Unit can generate service requests to the CPU. The CPU makes service requests directly to itself (via the ICU). The CPU Service Request Nodes are activated through software. Depending on the selected system clock frequency f SYS, the number of f SYS clock cycles per arbitration cycle must be selected as follows: f SYS < 60 MHz: ICR.CONECYC = 1 f SYS > 60 MHz: ICR.CONECYC = 0 Data Sheet 31 V1.0,

36 Functional Description Service Requestors Service Req. Nodes CPU Interrupt Arbitration Bus MSC0 2 2 SRNs 2 MLI0 SSC0 ASC0 ASC SRNs 3 SRNs 4 SRNs 4 SRNs CPU Interrupt Control Unit SRNs Interrupt Service Provider Software and Breakpoint Interrupts MultiCAN 6 6 SRNs 6 CPU Interrupt Control Unit CPU ADC0 4 4 SRNs 4 ICU Int. Req. Int. Ack. FADC 2 2 SRNs 2 PIPN CCPN GPTA0 STM SRNs 2 SRNs 38 2 Service Req. Nodes 1 1 SRN 1 Service Requestors LBCU FPU 1 1 SRN SRN 1 SBCU Flash 1 1 SRN SRNs 4 DMA Ext. Int 2 2 SRNs SRN 1 Cerberus 1 1 SRN 1 DMA Bus MCA06181 Figure 3-2 Block Diagram of the TC1762 Interrupt System Data Sheet 32 V1.0,

37 Functional Description 3.7 Asynchronous/Synchronous Serial Interfaces (ASC0, ASC1) Figure 3-3 shows a global view of the functional blocks and interfaces of the two Asynchronous/Synchronous Serial Interfaces, ASC0 and ASC1. Clock Control Address Decoder Interrupt Control f ASC EIR TBIR TIR RIR ASC0 Module (Kernel) RXD_I0 RXD_I1 RXD_O TXD_O P3.0 / RXD0A P3.1 / TXD0A P3.12 / RXD0B P3.13 / TXD0B To DMA ASC0_RDR ASC0_TDR Port 3 Control Interrupt Control EIR TBIR TIR RIR ASC1 Module (Kernel) RXD_I0 RXD_I1 RXD_O TXD_O P3.9 / RXD1A P3.8 / TXD1A P3.14 / RXD1B P3.15 / TXD1B To DMA ASC1_RDR ASC1_TDR MCB06211c Figure 3-3 Block Diagram of the ASC Interfaces The ASC provides serial communication between the TC1762 and other microcontrollers, microprocessors, or external peripherals. The ASC supports full-duplex asynchronous communication and half-duplex synchronous communication. In Synchronous Mode, data is transmitted or received synchronous to a shift clock that is generated by the ASC internally. In Asynchronous Mode, 8-bit or 9-bit data transfer, parity generation, and the number of stop bits can be Data Sheet 33 V1.0,

38 Functional Description selected. Parity, framing, and overrun error detection are provided to increase the reliability of data transfers. Transmission and reception of data is double-buffered. For multiprocessor communication, a mechanism is included to distinguish address bytes from data bytes. Testing is supported by a loop-back option. A 13-bit baud rate generator provides the ASC with a separate serial clock signal, which can be accurately adjusted by a prescaler implemented as fractional divider. Features Full-duplex asynchronous operating modes 8-bit or 9-bit data frames, LSB first Parity-bit generation/checking One or two stop bits Baud rate from 5.0 Mbit/s to 1.19 bit/s (@ 80 MHz module clock) and 4.1Mbit/s to 0.98 bit/s (@ 66 MHz module clock) Multiprocessor mode for automatic address/data byte detection Loop-back capability Half-duplex 8-bit synchronous operating mode Baud rate from 10.0 Mbit/s to bit/s (@ 80 MHz module clock) and 8.25 Mbit/s to bit/s (@ 66 MHz module clock) Double-buffered transmitter/receiver Interrupt generation On a transmit buffer empty condition On a transmit last bit of a frame condition On a receive buffer full condition On an error condition (frame, parity, overrun error) Data Sheet 34 V1.0,

39 Functional Description 3.8 High-Speed Synchronous Serial Interface (SSC0) Figure 3-4 shows a global view of the functional blocks and interfaces of the high-speed Synchronous Serial Interface, SSC0. Clock Control Address Decoder Interrupt Control f SSC0 f CLC0 EIR TIR RIR SSC0 Module (Kernel) Master Slave Slave Master Slave MRSTA MRSTB MTSR MTSRA MTSRB MRST SCLKA SCLKB SCLK SLSI1 SLSI[7:2] 1) SLSO[2:0] Port 3 Control P3.4 /MTSR0 P3.3 /MRST0 P3.2 /SCLK0 P3.7 /SLSI0 P3.5 /SLSO00 To DMA SSC0_RDR SSC0_TDR M/S Select 1) Enable 1) Master SLSO[5:3] SLSO6 SLSO7 1) P3.6 /SLSO01 P3.7 /SLSO02 P3.8 /SLSO06 Port 2 Control P2.1 /SLSO03 P2.8 /SLSO04 P2.9 /SLSO05 1) These lines are not connected MCB06225 Figure 3-4 Block Diagram of the SSC Interfaces The SSC supports full-duplex and half-duplex serial synchronous communication up to 40.0 MBaud at 80 MHz module clock and up to 33 MBaud at 66 MHz module clock. The serial clock signal can be generated by the SSC itself (Master Mode) or can be received from an external master (Slave Mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data is double-buffered. A shift clock generator provides the SSC with a separate serial clock signal. Seven slave select inputs are available for Data Sheet 35 V1.0,

40 Functional Description Slave Mode operation. Eight programmable slave select outputs (chip selects) are supported in Master Mode. Features Master and Slave Mode operation Full-duplex or half-duplex operation Automatic pad control possible Flexible data format Programmable number of data bits: 2 to 16 bits Programmable shift direction: LSB or MSB shift first Programmable clock polarity: Idle low or idle high state for the shift clock Programmable clock/data phase: Data shift with leading or trailing edge of the shift clock Baud rate generation from 40.0 Mbit/s to bit/s (@ 80 MHz module clock) and bit/s to 33 Mbit/s (@ 66 MHz module clock) Interrupt generation On a transmitter empty condition On a receiver full condition On an error condition (receive, phase, baud rate, transmit error) Flexible SSC pin configuration Seven slave select inputs SLSI[7:1] in Slave Mode Eight programmable slave select outputs SLSO[7:0] in Master Mode Automatic SLSO generation with programmable timing Programmable active level and enable control Data Sheet 36 V1.0,

41 Functional Description 3.9 Micro Second Bus Interface (MSC0) The MSC interface provides a serial communication link typically used to connect power switches or other peripheral devices. The serial communication link includes a fast synchronous downstream channel and a slow asynchronous upstream channel. Figure 3-5 shows a global view of the MSC interface signals. SR15 (from CAN) Clock Control Address Decoder Interrupt Control To DMA ALTINL[15:0] (from GPTA) ALTINH[15:0] f MSC0 f CLC0 EMGSTOPMSC (from SCU) SR[1:0] SR[3:2] MSC0 Module (Kernel) Downstream Channel Upstream Channel FCLP FCLN SOP SON EN0 EN1 SDI[0] 1) Port 2 Control C C C C A1 FCLP0A FCLN0 SOP0A SON0 P2.11 / FCLP0B P2.12 / SOP0B P2.8 / EN00 P2.9 / EN01 P2.13 / SDI0 1) SDI[7:1] are connected to high level MCA06255 Figure 3-5 Block Diagram of the MSC Interfaces The downstream and upstream channels of the MSC module communicate with the external world via nine I/O lines. Eight output lines are required for the serial communication of the downstream channel (clock, data, and enable signals). One out of eight input lines SDI[7:0] is used as serial data input signal for the upstream channel. The source of the serial data to be transmitted by the downstream channel can be MSC register contents or data that is provided at the ALTINL/ALTINH input lines. These input lines are typically connected to other on-chip peripheral units (for example with a timer unit like the GPTA). An emergency stop input signal makes it possible to set bits of the serial data stream to dedicated values in emergency cases. Data Sheet 37 V1.0,

42 Functional Description Clock control, address decoding, and interrupt service request control are managed outside the MSC module kernel. Service request outputs are able to trigger an interrupt or a DMA request. Features Fast synchronous serial interface to connect power switches in particular, or other peripheral devices via serial buses High-speed synchronous serial transmission on downstream channel Serial output clock frequency: f FCL = f MSC /2 Fractional clock divider for precise frequency control of serial clock f MSC Command, data, and passive frame types Start of serial frame: Software-controlled, timer-controlled, or free-running Programmable upstream data frame length (16 or 12 bits) Transmission with or without SEL bit Flexible chip select generation indicates status during serial frame transmission Emergency stop without CPU intervention Low-speed asynchronous serial reception on upstream channel Baud rate: f MSC divided by 4, 8, 16, 32, 64, 128, or 256 Standard asynchronous serial frames Parity error checker 8-to-1 input multiplexer for SDI lines Built-in spike filter on SDI lines Data Sheet 38 V1.0,