Atmel Exploits FPGA Flexibility in Application Development for Customizable Microcontroller-based Systems Peter Bishop, Atmel Corporation 22-Dec-2008

Transcription

1 Atmel Exploits Flexibility in Application Development for Customizable Microcontrollerbased Peter Bishop, Atmel Corporation 22Dec2008 Introduction Designing an embedded microcontrollerbased system poses a number of challenges. These include minimizing the design cycle time and design cost, optimizing the balance between hardware and software, developing hardware and software in parallel, and validating the system in order to achieve rightfirsttime silicon and software. Using an based emulation board for application development and validation, and implementing the design on a customizable microcontroller, such as the CAP ARM based MCU from Atmel, addresses all of these challenges. The emulation board hosts the applicationspecific functions of the design in an that interfaces with the fixed microcontroller, memories, peripherals and standard interfaces. The emulation board connects to a PC running industrystandard tools for hardware and software development and debug. This configuration enables custom hardware to be developed, simulated and synthesized on the PC, and then programmed into the. Application software is also developed on the PC, and then loaded, together with a qualified operating system such as Windows CE or Linux, onto the memories on the emulation board. The board, thus configured, runs the application software on the MCUplus configuration that closely emulates the performance of the customizable microcontroller that will incorporate the applicationspecific functions into its metal programmable (MP) block. The emulation board can be singlestepped, run between breakpoints or run at close to the operational speed of the customized device. Registers can be traced for debug. Errors can be corrected rapidly, either by modifying the applicationspecific logic or updating the application software. In this way the total functionality of the system is developed and validated in a unified environment. The design cycle time and cost are reduced, and the chances are increased of rightfirsttime silicon and software. Page 1 of 8

2 Atmel Exploits Flexibility in Application Development for Customizable Microcontrollerbased The CAP Design Flow The CAP design flow is oriented towards concurrent hardware and software development, as shown in Figure 1. Customer Flow MCU Core Hardware Design Flow Platform Peripherals/ Interfaces Specify Application Software Development Flow Platform Device Drivers MCU/MP Block Platform Define Hardware/ Software Architecture Applicationspecific Code Modules Applicationspecific Hardware Blocks Integrate Applicationspecific Blocks into MCU/MP Block Platform Integrate Device Drivers, Operating System and Application Code Applicationspecific Device Drivers Synthesis/ Functional Simulation Hardware/Software Cosimulation Software Simulation Operating System Customer Atmel Hardware and Lowlevel Software Emulation on based Emulation Platform Third Party Design House/ Customer Thied Party Supplier Place & Route Application Software Development Prototype Fabrication Hardware/Software Verification on Application Prototype or Development Board Software Test Volume Fabrication Final Software Debug/Test Integrate Device and Software into Application Figure 1: CAP Design Flow Diagram Page 2 of 8

3 Atmel Exploits Flexibility in Application Development for Customizable Microcontrollerbased The starting point of the CAP design flow is the specification of the required system, and the partitioning of its functionality between hardware and software. The general guideline is hardware for performance, software for flexibility, but in practice there is considerable scope for variation of this partitioning. One of the major benefits of the CAP emulation phase is that the hardware/software partitioning can be validated and, if necessary, corrected, before committing the hardware to silicon. The first phase of customizing the MP Block is to develop applicationspecific hardware. In most cases these hardware blocks are coded in Verilog RTL. The RTL code is synthesized using processspecific target libraries supplied by Atmel and functional simulations are performed on the entire device. Atmel supplies the lowlevel software device drivers for the fixed part of the microcontroller; the software driving the functions in the MP Block is developed by the application developer or by a thirdparty design house. This software is generally written in C, C++ or ARM assembly language. These drivers are integrated with the higherlevel application modules that program the MCU and peripherals/interfaces. If an operating system is required, a preported version is obtained from a qualified third party and integrated into the software suite. The software suite is tested using industrystandard development tools. Optionally, hardware/software cosimulation may be carried out at this stage if the required tools are available. Page 3 of 8

4 Atmel Exploits Flexibility in Application Development for Customizable Microcontrollerbased Validation on based Emulation Board Serial Debug I/O Serial Debug CAP Development Board Power Supply Image Sensor I/f Image Sensor Inputs CAN Bus 2XUSB Host USB Device Ethernet CAN Drivers Ethernet Phy Stereo Analog In Stereo Audio Stereo Codec Analog Out Headphone/ Line Out Line In Microphone Stereo Audio Codec Analog Inputs 2XSD/ MMC/ DataFlash CAN USB Host/Dev Ethernet I2S AC97 ADC MCI Memory CAP Config Memory SDRAM BCRAM Mobile DDRAM NOR Flash NAND Flash External Bus Interface LCD Ctrl Touch Screen Ctrl PIO LED Keyboard USB Ext Touch Screen I/f LCD Display Parallel I/O User LEDs Power LED 4X4 Keyboard I/O Touch Screen Input 3X USB Device InCircuit Emulator Interface CAP ICE JTAG JTAG Interface Figure 2: CAP Emulation Board Schematic The key step in the design flow is the emulation of the hardware and at least the lowlevel software on an based CAP emulation board. As illustrated in Figure 2, the CAP emulation board includes a full complement of memories, standard interfaces and network connections together with additional connections that can be configured for the requirements of the application. Specifically: The fixed portion of the CAP device is implemented as single MCU chip with a bondedout interface in the MP Block. A highdensity emulates MP Block including embedded memories and external I/Os. An configuration memory contains the compiled HDL code for the MP Block. The External Bus Interface (EBI) and the external input/outputs from the are connected to a wide selection of memories on an extension board: SDRAM, Mobile DDRAM, Burst Cellular RAM, NOR Flash, NAND Flash, etc. These are loaded with the software suite and reference data for the application. Page 4 of 8

5 Atmel Exploits Flexibility in Application Development for Customizable Microcontrollerbased All standard interfaces (CAN, USB, Ethernet, I2S, AC97, ADC, MCI, etc.) are routed through transceivers/phys/codecs to external connections. This enables full test/debug of the external interfaces and networking/communication links of the device. All elements of the Graphical User Interface (GUI) are connected to onboard devices or interfaces: LCD, keyboard, touch screen interface, etc. This enables the basic elements of the GUI to be tested onboard. External Parallel I/O (PIO) and input/outputs are provided for connection to applicationspecific external devices, and the implementation of nonstandard interfaces. Spare I/Os can also be used for validation, as described below. A JTAG incircuit emulator (ICE) port enables the ARM core and its peripherals to be validated using industrystandard development tools in conjunction with a JTAGtoUSB interface, as described below. An JTAG port enables internal signals in the to be traced and analyzed using tools from the supplier, also as described below. The MCU/ combination runs at close to the operating frequency of the final CAP device. This enables atspeed validation of the device, including the MCU, standard interfaces and the functions implemented in the MP Block, together with all the software that has been developed up to this point. Corrections can be made to the applicationspecific hardware or software of the device at no cost penalty. Experience indicates that this emulation step almost always highlights errors in the hardware and/or software, or the hardware/software interface of the device. The ability correct and retest the complete design of the device at this stage is a major factor in reducing the design time and cost, and increases the probability of rightfirsttime silicon and software. An additional benefit is that the emulated version of the final design can be used as the starting point for future design iterations, at a substantial saving of design effort. Figure 3: CAP Emulation Board Page 5 of 8

6 Atmel Exploits Flexibility in Application Development for Customizable Microcontrollerbased Validation of Software Running on the ARM Processor A JTAG emulator from Atmel or an accredited thirdparty supplier provides a JTAGtoUSB interface that connects the CAPICE JTAG port from the ARM processor on the CAP emulation board to the PC being used to develop and debug the software. A USB driver for this device enables it to be seamlessly integrated into industrystandard application development tools. These enable the software under development to be compiled and run, either at full speed between breakpoints or watchpoints, or under single stepping, while internal registers, signals and memories in the ARM processor and address space (including control registers for peripherals and interfaces) are nonintrusively monitored. This data can be viewed in a variety of formats to aid comprehension. Validation of ApplicationSpecific Hardware in the It is essential to provide the same level of traceability for signals and registers implemented in the MP Block as for those in the ARM processor. This is achieved while the MP Block is mirrored in the during the emulation phase, using either or both of the techniques described below. Tracing Internal Signals by Additional BondOuts The simplest approach to debug is to designate internal signals to be monitored as external I/Os. The generous provision of I/O signals in the CAP emulation board should provide spare capacity for these signals in most cases. However, if sufficient unallocated I/Os are not available, multiplexing with nonessential operational signals in a test mode is a possibility. This should be treated with caution as it modifies the logical structure of the relative to the operational version that will be transformed into the MP block, and can affect the timing of signals on critical paths. Test signals designated in this way can be examined with logic analyzer or fed, via a suitable interface, into software development tools running on the PC. Page 6 of 8

7 Atmel Exploits Flexibility in Application Development for Customizable Microcontrollerbased Instancing Trace Logic in the Traced Signals/ Clocks/ Triggers Embedded Logic Analyzsers Filtering Logic JTAG Hub To JTAG Port Figure 4: Embedded Logic Analyzers and JTAG Hub in An approach to debug that comes close to the level provided for the processor core is to use tools provided by the supplier to instance a number of embedded logic analyzers () and a JTAG hub into the. Each is associated with a signal to be traced, together with clocks and triggers. For each, conditions can be specified for the capture of a signal trace depending on the states or transitions of the clock and trigger. The data gathered by each is buffered in one of the internal SRAM blocks that are an integral part of the fabric. The traced data is gathered in a JTAG hub that is also instanced in the, and linked to its JTAG port that is carried to an external connection on the CAP emulation board. The s and JTAG hub consume gates, but are independent of the operational hardware modules that are implemented in the. They have minimal effect on the timing of operational signals. In many cases extremely large quantities of traced data are generated by this approach. Some development tools allow for the insertion of filtering logic between the s and the JTAG hub in order to preprocess the traced data, and reduce its volume to manageable proportions. The JTAG signal is connected, via an interface provided by the supplier, to the PC that runs the development tools. These tools enable the traced signals to be displayed in various formats and stored for detailed analysis. Page 7 of 8

8 Atmel Exploits Flexibility in Application Development for Customizable Microcontrollerbased The combination of processor and trace facilities provides the application developer with a finegrained picture of the behavior of the systemonchip under development under realistic conditions of operation. In particular interrupt handling and the coordination of the MCU and applicationspecific logic can be examined in a way that is impossible to simulate. The emulation usually runs at a lower clock frequency than the fabricated device, and the probe circuitry can have some impact on the detailed timing of operational signals, but nevertheless the insight provided by these tools is extremely valuable for hardware and software covalidation. CAP Physical Design Flow and Fabrication Once the functionality of the device under development has been fully validated during the emulation phase, the final RTL code that has been used to program the is mapped onto the metal layers that personalize the CAP metal programmable block. Rigorous postlayout simulation ensures that the functionality of the metalprogrammed CAP is identical to that of the emulated version. Prototypes are rapidly fabricated from blanks that have been staged in the fab prior to metal layers. These enable the application developer to do a final verification of the device s hardware/software functionality. In the worst case, if the prototypes are not satisfactory, the additional cost and time of a respin starting from the emulation phase are reasonable, much lower than those for a full mask replacement for a standardcell ASIC. When the prototypes have been approved, volume fabrication of the personalized CAP devices commences, using the same flow as for the prototypes. Conclusion The architecture and design flow of Atmel s CAP customizable microcontroller enables applicationspecific functions to be instanced in the MP block of the device. Their architecture, together with the entire software suite, concurrently developed for the ARM core and MP block, is validated at close to operational speed during the emulation phase. The flexibility of architecture enables corrections to be made and revalidated with no cost overhead. This gives confidence in rightfirsttime operation of the hardware and software of the system, while keeping development time and costs to a minimum. About Atmel Atmel is a worldwide leader in the design and manufacture of microcontrollers, advanced logic, mixedsignal, nonvolatile memory and radio frequency (RF) components. Leveraging one of the industry's broadest intellectual property (IP) technology portfolios, Atmel is able to provide the electronics industry with complete system solutions focused on consumer, industrial, security, communications, computing and automotive markets Atmel Corporation. All Rights Reserved. Atmel, logo and combinations thereof, CAP and others, are registered trademarks, or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Page 8 of 8