USB3.0-IP Core intruduction
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1 USB3.0 Host & Device IP Ver1.7XE Supports Virtex6/Spartan6 Enchant your product with SuperSpeed! 2012/7/11 Design Gateway Page 1 USB3.0-IP Core intruduction IP Core to support USB3.0 SuperSpeed for Host (USB3H-IP) or Device (USB3D-IP) Includes Protocol&Link Layer as well as DMAC,Host I/F, and PIPE I/F Practical implementation is provided by reference design. 2012/7/11 Design Gateway Page 2
2 USB3.0-IP Core merit1 Supports SuperSpeed(5.0Gbps) of USB3.0 Standard. Provides controller function of either Host or Device side. Connects with external PHY device. (TUSB1310A of T.I) Includes USB3.0 PIPE interface. Saves FPGA resource usage by limiting SuperSpeed only. USB3.0-IP resourc report (1 Control, 2 IN/OUT each) 2012/7/11 Design Gateway Page 3 USB3.0-IP Core merit2 Supports 15 IN/OUT Endpoints at maximum. 1 Control Endpoint 7 IN/OUT Endpoints each at maximum. Supports all transport type. (Control/Bulk/Isochronous/Interrupt) Real board evaluation with Xilinx FPGA board (Both Host-IP and Device-IP) Simple and easy connection user I/F. 2012/7/11 Design Gateway Page 4
3 Device-IP Core performance Best performance in existing USB3.0 system. High performance at both sequential and random access. Provides design that minimizes overhead. USB3D-IP benchmark result (Reference: competitor result) 2012/7/11 Design Gateway Page 5 Host-IP Core performance Extracts SuperSpeed upper limit! Raw sequential aceess (non-fat) result: Read=412MB/s, Write=399MB/s (use USB3.0 RamDisk) Environment: * Use SP-605 Host reference design. * Connect 4 port USB3.0-Hub (from VIA) * Assign drv1 as RamDisk emulation drive * Assign drv4 as Intel-SSD via ASMedia bridge Raw data (non-fat) performance SSD Read=270MB/s,Write=85MB/s RamDisk drive Read=412MB/s, Write=399MB/s USB3H-IP performance result (Note) drv1 RamDisk is SP-605 with Device-IP reference design. 2012/7/11 Design Gateway Page 6
4 Core product line up Supported FPGA and Core product Product Info. Spartan-6 Virtex-6 Device-IP Core USB3D-IP002 USB3D-IP003 Host-IP Core USB3H-IP002 USB3H-IP003 Released Next product plan Support Virtex-7/Kintex 7/Kintex-7/Artix 7/Artix-7 Comming soon 2012/7/11 Design Gateway Page 7 Evaluation bit-file for Spartan-6 Free bit-file for evaluation using SP-605 Demo board (AB07-USB3FMC) is required USB3.0 port of Host PC Config uration Bit-file for evaluation SP-605 USB3.0-IP evaluation environment USB3.0-IP demo board (AB07-USB3FMC) 2012/7/11 Design Gateway Page 8
5 Demo board(ab07-usb3fmc) Connects with FMC on SP-605/ML-605 Mounts TUSB1310A (T.I) and peripheral circuit Mounts additional SATA Host connector PHY device (TUSB1310A) USB3.0 connector SATA Host connector (FMC connector on solder side) AB07-USB3FMC 2012/7/11 Design Gateway Page 9 Reference Design (Summary) Real operation on SP-605/ML-605 and demo board. ISE/EDK/SDK project of evaluation bit-file Provides all HDL source code except IP-Core. Also provides MicroBlaze firmware by C source 2012/7/11 Design Gateway Page 10
6 Reference Design (Device function) HostPC can recognize storage class device Emulate RamDisk by DDR3 on SP-605 HostPC can recognize storage class device 2012/7/11 Design Gateway Page 11 Reference Design (Host function) Access to USB3.0 storage device by FAT16 Issue command from serial console Execute FAT operation command via serial console Can execute R/W raw (non FAT) data by Supervisor mode FAT operation menu of Host reference design 2012/7/11 Design Gateway Page 12
7 Application example1 Connect multiple high-resolution USB3.0 camera/video 3D process in FPGA and send data to PC via USB3.0 High resolution 3D image processing system 2012/7/11 Design Gateway Page 13 Application Example2 Dual Role system that can operate both PC-connection and stand-alone environment Prepare individual configuration data for Host/Device function Dual Role measurement system 2012/7/11 Design Gateway Page 14
8 Inquiry Detailed technical information on Web site or Inquiry Design Gateway Co.,Ltd. sales@design-gateway.com FAX : /7/11 Design Gateway Page 15 Revision History Rev. Date Description 1.7XE 2012/07/11 Release English presentation 2012/7/11 Design Gateway Page 16
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