HSMC SATA RAID board [AB12-HSMCRAID] Manual [Ver1.0E]
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1 HSMC SATA RAID board [AB-HSMCRAID] Manual [Ver.0E] Introduction Thank you for choosing HSMC SATA RAID board [Part Number: AB-HSMCRAID] ( RAID board in this manual.) The RAID board is compliant with HSMC standard of Altera and provides SATA channels at maximum by high speed serial interface in HSMC so that user can build SATA RAID prototype system. The RAID board can directly connect with pcs of. -SATA drive. User can supply power to the connected SATA drive via -pin ATX Standard power connector. On-board 0MHz low-jitter differential oscillator will supply high-quality reference SATA clock to the refclk input of FPGA via HSMC I/F (CLKINp/n). Board Appearance The RAID board size is mm width and 90mm length. Following figure- and figure- shows component side and solder side appearance respectively. Figure-: AB-HSMCRAID component side Copyright 0 Design Gateway Co,.Ltd. All rights reserved.
2 Figure-: AB-HSMCRAID solder side Connection to the FPGA board Connect the RAID board with HSMC connector on the FPGA board. For. -SATA drive connection, user can directly connect SATA drive with CN0 CN SATA connector on the RAID board. Use -pin ATX Standard power connector for SATA drive power supply. User must check that all SATA drives, RAID board and FPGA board are powered off when remove or connect. To connect. -SATA drive, use SATA general extention cable. Following general extention cable is suitable for. usage. Vendor: AREA (Setagaya Denki) Product Number: AR-S00S URL : Vendor: AINEX Product Number: SAT-EXPA URL : When user want to assign SATA channel of the RAID board as a SATA Device to connect with SATA Host-PC, use above extention cable along with the following crossover adapter provided from DesignGateway. Vendor: DesignGateway Product Number: AB0-CROSSOVER URL : Copyright 0 Design Gateway Co,.Ltd. All rights reserved.
3 Pin Assignment Pin assignment of HSMC on the RAID board is listed following table-. HSMC Pin# (*) Samtec Pin# (*) HSMC definition Signal Name RAID Bd destination connection TX_ HTP CN-S (TX Pos) RX_ HRP CN- (RX Pos) TX_N HTN CN- (TX Neg) RX_N HRN CN- (RX Neg) TX_ HTP CN-S (TX Pos) RX_ HRP CN- (RX Pos) 9 TX_N HTN CN- (TX Neg) 0 RX_N HRN CN- (RX Neg) 9 TX_ HTP CN-S (TX Pos) 0 RX_ HRP CN- (RX Pos) TX_N HTN CN- (TX Neg) RX_N HRN CN- (RX Neg) 9 TX_ HTP CN-S (TX Pos) 0 RX_ HRP CN- (RX Pos) TX_N HTN CN- (TX Neg) RX_N HRN CN- (RX Neg) TX_ HTP CN-S (TX Pos) RX_ HRP CN- (RX Pos) 9 TX_N HTN CN- (TX Neg) 0 RX_N HRN CN- (RX Neg) TX_P HTP CN-S (TX Pos) RX_P HRP CN- (RX Pos) TX_N HTN CN- (TX Neg) RX_N HRN CN- (RX Neg) TX_P HTP CN-S (TX Pos) RX_P HRP CN- (RX Pos) 9 TX_N HTN CN- (TX Neg) 0 RX_N HRN CN- (RX Neg) 9 TX_P0 HT0P CN0-S (TX Pos) 0 RX_P0 HR0P CN0- (RX Pos) TX_N0 HT0N CN0- (TX Neg) RX_N0 HR0N CN0- (RX Neg) CLKINP SCKN (via R) X- (*) CLKINN SCKP (via R) X- (*) Table: HSMC pin assignment of AB-HSMCRAID board Note: (*) HSMC Pin# is pin number defined in HSMC standard, while Samtec Pin# is pin number of connector specification. (*) 0MHz SATA reference clock of CLKINP/N is reversed in its polarity due to the board trace, however, this polarity invertion is no problem because differential clock waveform is symmetrical. Copyright 0 Design Gateway Co,.Ltd. All rights reserved.
4 Disclaimer DesignGateway is exempted from any damage to the connected SATA device or FPGA board. DesignGateway does not guarantee transfer speed performance. [Inquiry] URL : mailto:sales@design-gateway.com Revision History Revision Date Description.0E -Jul-0 Release English manual Copyright 0 Design Gateway Co,.Ltd. All rights reserved.
5 D D C C B B A A [Vot=.V] Component side test pin Solder side test pin [POWER] (No mount) (LVDS-level differential clock) -:Short -:Open AB-HSMCRAID.0 RAID A Friday, January, 0 Title Size Document Number Rev Date: Sheet of HR0N JTAG JTAG HT0N HT0P HR0P HTN TP TP RP HRN RN HTP HTN T0P HTP HR0N RN RP TN HTP HRN RN TP TP HT0N HRN PWRV RP TP TN HTN PWRV PWRV PWRV PWRV HT0P HTN HRP HTP HTN HTN HRP HRP LA HR0P HRP RP RP HTN TN PWRV HRP HRP TP HRP RN T0N HRN HRN RN HRN HRN PWRV PWRV RN RN TN R0N RP HTP TN HTP TN RP HTP TN TP R0P HTN HTP HRP HRN HTN HTP HTN HTP HTN HTN HTP HTP HTP HTN HTP HTN HRN HRP HRP HRN HRP HRP HRN HRN HRP HRP HRN HRN VCC VCK DC0 CKP SCKN CKN SCKP AJ VCC DD0 PWRV T HK--S JD QTH L-D-A C C LED PGC C CN --ML P P P0 P P S S V_ V_ V_ C0 R 00K U MCT-ADJE/DC VIN SHDN VOUT ADJ TAB C C C C C C R 0K JP SOLJ C CN --ML P P P0 P P S S V_ V_ V_ R 0 C R 0 C C C R9 0 C C C 0.u CN --ML P P P0 P P S S V_ V_ V_ CN --ML P P P0 P P S S V_ V_ V_ C0 C 0.u C CN --ML P P P0 P P S S V_ V_ V_ CN --ML P P P0 P P S S V_ V_ V_ C C C C9 U IPLockDevice VDD NC NC NC NC DC0 DD0 TP HK--S C C9 X DiffOsc(0MHz) OE NC OUT OUT_B VCC TP HK--S C C.u R C9 R C C R K T HK--S R K C0 T HK--S CN0 --ML P P P0 P P S S V_ V_ V_ C T HK--S CN 0- T HK--S JA QTH L-D-A T HK--S JB QTH L-D-A C C.u JC QTH L-D-A CN --ML P P P0 P P S S V_ V_ V_
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