RAID prototype system introduction. SATA-IP RAID prototype system for Xilinx FPGA. 3 September 2018 Design Gateway Page 1.
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1 RAID prototype system introduction Ver1.3E - RAID prototype system for Xilinx FPGA 3 September 2018 Design Gateway Page 1 System Outline RAID prototype for the latest Xilinx FPGA Use RAID adapter board (AB09-FMCRAID) Operate 4-channel RAID0 (parallel access) Standard and High Performance version Show read/write result to PC via RS232C Execute test pattern read/write Display measured transfer performance 3 September 2018 Design Gateway Page 2
2 Prototype System Xilinx FPGA board (KCU105 in this picture) Mount AB09-FMCRAID adapter board on FMC connector Connect SSDs RAID prototype system using Xilinx FPGA board 3 September 2018 Design Gateway Page 3 RAID Adapter Board Can support up to 10 channels (each 5 ports on both component and solder side) Connect with FMC-HPC connector on Xilinx FPGA board 2.5 -SSD/HDD drive direct insertion Drive power supply via standard ATX power connector Part Number: AB09-FMCRAID Available on Mouser website 10 combiconnectors Connect with FMC-HPC ATX power connector 2.5 drive direct insertion 3 September 2018 Design Gateway Page 4
3 Two types RAID design Standard Version (MicroBlaze control) Use MicroBlaze for - controller All channel control by time division in CPU F/W Requires - only (no need HCTL-) High Performance Version (HCTL- control) Use HCTL- core for - controller Minimum latency, Maximum performance Requires Both - and HCTL- core 3 September 2018 Design Gateway Page 5 Standard Version Block Diagram MicroBlaze (CPU) A single MicroLBaze controls all channels in time division AXI2 AXI- 3 SSD LMB Bus AXI4_Lite Bus AXI- AXI2 3 SSD DDR3 (1 GB) AXI_DDR3 AXI2 AXI- 3 SSD R/W data transfer via individual AXI interconnect LMB BRAM AXI- AXI2 3 SSD Serial Port RAID Reference Design Timer UART Interrupt Controller Standard version RAID prototype system block diagram 3 September 2018 Design Gateway Page 6
4 High Performance Version Block Diagram MicroBlaze does not require and RAID control Independent HCTL- in each channel directly controls - HCTL- - High Performance version RAID prototype system block diagram 3 September 2018 Design Gateway Page 7 Write Result (High Performance Version) Set transfer size 0x sector = 32GB Set data pattern 4 = LFSR pseudo random pattern Write = 2068MB/s 4ch RAID Write Performance result 32GByte Write Result [Measurement Condition] FPGA: KCU105 board SSD: Samsung 850PRO x 4 High Performance Version 3 September 2018 Design Gateway Page 8
5 Read Result (High Performance Version) Set transfer size 0x sector = 32GB Set data pattern 4 = LFSR pseudo random pattern Read = 2225MB/s 4ch RAID Read Performance result 32GByte Read Result [Measurement Condition] FPGA: KCU105 board SSD: Samsung 850PRO x 4 High Performance Version 3 September 2018 Design Gateway Page 9 RAID Performance Write speed efficiency=99% Single=520MB/s, 4ch-RAID=2068MB/s Speed efficiency = 2068/(4 x 520) = 99% Read speed efficiency=97.29% Single=560MB/s, 4ch-RAID=2225MB/s Speed efficiency = 2225/(4 x 560) = 99% 3 September 2018 Design Gateway Page 10
6 RAID Design in deliverables Vivado project is attached with - and/or HCTL- product Full source code except core VHDL for hardware and C for MicroBlaze firmware Can save user system development duration Confirm real board operation by original reference design Then modify a little to approach final user product Check real operation in each modification step Short-term develpment is possible without big turn back 3 September 2018 Design Gateway Page 11 Conclusion Can build RAID prototype with FPGA & RAID adapter Quick check of RAID system without new board building RAID performance is almost 100% of single drive total Multiply performance by drive count Prototype design is available for - users Reduce RAID system development period based on this design RAID Reference Adapter bd. FPGA bd. - Quick!! 3 September 2018 Design Gateway Page 12
7 For more detail Detailed technical information available on the web site. Contact Design Gateway Co,. Ltd. FAX: September 2018 Design Gateway Page 13 Revision History Rev. Date Description Jun-09 RAID prototype system introduction 1st release 1.1E 21-Feb-13 Updated tokc705 based RAID system 1.3E 03-Sep-18 Added latest family support, added high performance version description 3 September 2018 Design Gateway Page 14
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