All Frames Recept. VC Pkt Extraction VC Reception VC Demux. MC Demux. Data Link Protocol Sub-Layer VC0 VC1. VC2 AHB DMA 2k FIFO

Transcription

1 Features CCSDS/ECSS compatible Telemetry Encoder and Telecommand Decoder Telemetry encoder implements in hardware part of protocol sub-layer, synchronization & channel coding sub-layer, and part of physical layer Telemetry input via multiple SpaceWire links Reed-Solomon and Convolutional encoding Telecommand decoder implements in hardware synchronization & channel coding sub-layer, and part of physical layer Software telecommands via SpaceWire link Hardware telecommands via parallel port At least 2 Mbit/s downlink & 100 kbit/s uplink CCSDS Telemetry and Telecommand CCSDS TM / TC and SpaceWire FPGA Data Sheet and User s Manual Description The telemetry encoder and telecommand decoder are implemented in an Actel RTAX FPGA. The lower layers of the encoder and decoder are implemented in hardware with the higher layers externally in software. Support is provided for additional hardware encoded telemetry and hardware decoded command outputs and pulses. Specification RTAX2000S-CQ352 Total Ionizing Dose Up to 300 krad (Si) Single-Event Latch-Up Immunity (SEL) to LET TH > 104 MeV-cm2/mg Immune to Single-Event Upsets (SEU) to LET TH > 37 MeV-cm2/mg SRAM MRAM SpaceWire (LEON3) HW Cmd Interrupt Memory Controller AHB Slave GRSPW RMAP AHB Master Interrupt Controller AMBA Data Link Protocol Sub-Layer AMBA AHB DMA FIFO Master Configuration AMBA AHB Slave Hardware Commands Packet Extraction Path Recovery VC Pkt Extraction VC Reception VC Demux MC Demux All Frames Recept. Coding Sub-Layer Physical Layer Pseudo-Derandomizer BCH Decoder Start sequence search NRZ-L/M Telecommand Decoder Telecommand CLTU 4k Memory AHB Slave Descriptor Memory AHB Slave 16k Buffer Memory AHB Slave Data Link Protocol Sub-Layer AMBA APB Slave Configuration VC0 VC1 AMBA VC2 AHB DMA 2k FIFO Master Virtual Channel Frame Service Telemetry Encoder Coding Sub-Layer Physical Layer CLCW SpaceWire (Science) SpaceWire (Science) GRSPW RMAP AHB Master GRSPW RMAP AHB Master AMBA AMBA AHB Slave AHB Slave AHB Slave AHB Slave VC Generate VC Generate VC Generate VC Generate AMBA AHB Master AMBA AHB Master AMBA AHB Master AMBA AHB Master VC3 VC4 VC5 VC6 Virtual Channel Multiplexer Master Channel Generation All Frames Generation Sync Marker Reed-Solomon Convolutional Pseudo Randomizer NRZ-L/M Telemetry CADU Idle Frame VC7 TMTC FPGA Applications The telemetry encoder and telecommand decoder can be used in systems where CCSDS/ECSS compatible communication services are required. The software implementation of the higher layers of the telemetry encoder and the telecommand decoder allows for implementation flexibility and accommodation of future standard enhancements. The hardware encoded telemetry and decoded command outputs do not require software and can be used for critical operations.

2 2 CCSDS TM / TC and SpaceWire FPGA Table of contents 1 Introduction Overview Hierarchy Telemetry encoder Telemetry encoder specification Virtual Channels 0, 1 and Virtual Channels 3, 4, 5 and Virtual Channel Telecommand decoder Telecommand decoder specification Software Virtual Channel Hardware Virtual Channel Memory Interface SpaceWire Link Interfaces On-chip Memory Interrupt Controller Signal overview Architecture Specification Interfaces Clock and reset Performance IP cores Interrupts Memory map Signals Abbreviations and acronyms Conventions Consultative Committee for Space Data Systems Galois Field Telemetry Transfer Frame format Reed-Solomon encoder data format Attached Synchronization Marker Telecommand Transfer Frame format Command Link Control Word Space Packet Asynchronous bit serial data format SpaceWire Remote Memory Access Protocol (RMAP) Command Link Control Word interface (CLCW) Waveform formats Telemetry Encoder Overview Layers Introduction Data Link Protocol Sub-layer... 31

3 3 CCSDS TM / TC and SpaceWire FPGA Synchronization and Channel Coding Sub-Layer Physical Layer Data Link Protocol Sub-Layer Physical Channel Virtual Channel Frame Service Virtual Channel Generation - Virtual Channels 3, 4, 5 and Virtual Channel Generation - Idle Frames - Virtual Channel Virtual Channel Multiplexing Master Channel Generation Master Channel Frame Service Master Channel Multiplexing All Frame Generation Synchronization and Channel Coding Sub-Layer Attached Synchronization Marker Reed-Solomon Encoder Pseudo-Randomiser Convolutional Encoder Physical Layer Non-Return-to-Zero Level encoder Clock Divider Connectivity Operation Introduction Descriptor setup Starting transmissions Descriptor handling after transmission Auto start Registers Signal definitions and reset values Timing Telemetry Encoder - Virtual Channel Generation function input interface Overview Interrupts Registers Status Register (R) Control Register (R/W) AHB I/O area Telemetry Encoder - Virtual Channel Generation Overview Registers Signal definitions and reset values Timing Telemetry Encoder - Descriptor Overview Operation Introduction Descriptor definition Registers Signal definitions and reset values... 54

4 4 CCSDS TM / TC and SpaceWire FPGA 7.5 Timing Telecommand Decoder - Software Commands Overview Concept Functions and options Data formats Reference documents Waveforms Coding Layer (CL) Synchronisation and selection of input channel Codeblock decoding De-Randomiser Non-Return-to-Zero Mark Design specifics Direct Memory Access (DMA) Transmission Data formatting CLTU Decoder State Diagram Nominal CASE CASE Abandoned Relationship between buffers and FIFOs Buffer full Buffer full interrupt Command Link Control Word interface (CLCW) Configuration Interface (AMBA AHB slave) Interrupts Registers Interrupt registers Signal definitions and reset values Timing Telecommand Decoder - Hardware Commands Overview Concept Operation All Frames Reception Master Channel Demultiplexing Virtual Channel Demultiplexing Virtual Channel Reception Virtual Channel Packet Extraction Path Recovery Packet Extraction Application Layer Telecommand Transfer Frame format - Hardware Commands Signal definitions and reset values Timing SpaceWire Interface with RMAP target Overview... 83

5 5 CCSDS TM / TC and SpaceWire FPGA 10.2 Operation Overview Protocol support Link interface Link interface FSM Transmitter Receiver RMAP Fundamentals of the protocol Implementation Write commands Read commands RMW commands Control Signal definitions and reset values Timing Fault Tolerant PROM/SRAM Memory Interface Overview Operation Access errors Using bus ready signalling PROM/SRAM/IO waveforms Registers Signal definitions and reset values Timing On-chip Memory with EDAC Protection Overview Operation Registers Status Registers Overview Operation Errors Correctable errors Interrupts Registers Serial Debug Interface Overview Operation Transmission protocol Baud rate generation Registers Signal definitions and reset values Timing Interrupt Controller Overview Operation

6 6 CCSDS TM / TC and SpaceWire FPGA Interrupt prioritization Extended interrupts Processor status monitoring Irq broadcasting Registers Interrupt level register Interrupt pending register Interrupt force register (NCPU = 0) Interrupt clear register Multiprocessor status register Processor interrupt mask register Broadcast register (NCPU > 0) Processor interrupt force register (NCPU > 0) Extended interrupt acknowledge register Signal definitions and reset values Timing Clock generation Overview Signal definitions and reset values Timing Reset generation Overview Signal definitions and reset values Timing AMBA AHB controller with plug&play support Overview Operation Arbitration Decoding Plug&play information Registers Debug print-out AMBA AHB/APB bridge with plug&play support Overview Operation Decoding Plug&play information Debug print-out Electrical description Absolute maximum ratings Operating conditions Input voltages, leakage currents and capacitances Output voltages, leakage currents and capacitances Clock Input voltages, leakage currents and capacitances Power supplies Mechanical description

7 7 CCSDS TM / TC and SpaceWire FPGA 21.1 Package Pin assignment RTAX2000S specific pins - CQ352 package RTAX2000S specific pins - CG624 package Package figure Mechanical drawing Weight Package materials Thermal characteristics Reference documents Ordering information Change record

8 8 CCSDS TM / TC and SpaceWire FPGA 1 Introduction 1.1 Overview The CCSDS/ECSS Telemetry Encoder and Telecommand Decoder can be used in systems where CCSDS/ECSS compatible communication services are required. The Telemetry and Telecommand concept is based on implementing the associated protocols partly in hardware and partly in software. The lower layers, such as physical layer and the channel coding sub-layer, are implemented in hardware, whereas high levels such as data link - protocol sub-layer are implemented in software. 1.2 Hierarchy Figure 1 shows a simple block diagram of the device. Note that all cores with AHB master interfaces also have APB slave interfaces for configuration and status monitoring, although not shown in the block diagram. The following sub-sections briefly describe the functionality of the blocks. SRAM MRAM SpaceWire (LEON3) HW Cmd Interrupt Memory Controller AHB Slave GRSPW RMAP AHB Master Interrupt Controller AMBA AMBA AHB Master AMBA AHB Slave Data Link Protocol Sub-Layer Hardware Commands DMA Packet Extraction FIFO Configuration Path Recovery VC Pkt Extraction VC Reception VC Demux MC Demux All Frames Recept. Coding Sub-Layer Physical Layer Pseudo-Derandomizer BCH Decoder Start sequence search NRZ-L/M Telecommand Decoder Telecommand CLTU 4k Memory AHB Slave Descriptor Memory AHB Slave 16k Buffer Memory AHB Slave AMBA APB Slave AMBA AHB Master DMA Data Link Protocol Sub-Layer Configuration 2k FIFO Virtual Channel Frame Service VC0 VC1 VC2 Telemetry Encoder Coding Sub-Layer Physical Layer CLCW SpaceWire (Science) SpaceWire (Science) GRSPW RMAP AHB Master GRSPW RMAP AHB Master AMBA AMBA AHB Slave AHB Slave AHB Slave AHB Slave VC Generate VC Generate VC Generate VC Generate AMBA AHB Master AMBA AHB Master AMBA AHB Master AMBA AHB Master VC3 VC4 VC5 VC6 Virtual Channel Multiplexer Master Channel Generation All Frames Generation Sync Marker Reed-Solomon Convolutional Pseudo Randomizer NRZ-L/M Telemetry CADU Idle Frame VC7 TMTC FPGA Figure 1. Block diagram

9 9 CCSDS TM / TC and SpaceWire FPGA 1.3 Telemetry encoder The CCSDS Telemetry Encoder implements part of the Data Link Layer, covering the Protocol Sublayer and the Synchronization and Coding Sub-layer and part of the Physical Layer of the packet telemetry encoder protocol. The Telemetry Encoder comprises several encoders and modulators implementing the Consultative Committee for Space Data Systems (CCSDS) recommendations, European Cooperation on Space Standardization (ECSS) and the European Space Agency (ESA) Procedures, Standards and Specifications (PSS) for telemetry and channel coding. The Telemetry Encoder implements seven Virtual Channels accessible via SpaceWire links. Three of the Virtual Channels accept partial Telemetry Frames from software implementing higher protocol layers such as Virtual Channel Generation function. The other four Virtual Channels accept CCSDS Space Packet data [CCSDS-133.0] as input via the SpaceWire RMAP protocol. An eighth Virtual Channel is implemented for Idle Frames only Telemetry encoder specification This Data Link - Protocol Sub-layer [CCSDS-132.0] functionality is not implemented in hardware: Packet Processing Virtual Channel Frame Service (DMA functionality only) (see also Virtual Channel 3, 4, 5 and 6) Master Channel Frame Service (only single Spacecraft Identifier supported) Master Channel Multiplexing (only single Spacecraft Identifier supported) This Data Link - Protocol Sub-layer [CCSDS-132.0] functionality is implemented in hardware: Virtual Channel Generation (for Virtual Channels 3, 4, 5 and 6) Virtual Channel Generation (for Idle Frame generation only, e.g. Virtual Channel 7) Virtual Channel Multiplexing (for all frames) Master Channel Generation (for all frames) All Frame Generation (for all frames) Multiplexing of four CLCW sources, of which two external via asynchronous bit serial interfaces This Synchronization and Channel Coding Sub-Layer [CCSDS-131.0] functionality is implemented in hardware: Attached Synchronization Marker Reed-Solomon coding Pseudo-Randomiser Convolutional coding This Physical Layer [ECSS-50-05A] functionality is implemented in hardware: Non-Return-to-Zero Mark/Level modulation (NRZ-M/L) The Telemetry Encoder fixed configuration is as follows: fixed transfer frame format, version 00b, Packet Telemetry fixed transfer frame length of 1115 octets common Master Channel Frame Counter for all Virtual Channels

10 10 CCSDS TM / TC and SpaceWire FPGA fixed nominal Attached Synchronization Marker usage fixed 2 kbyte telemetry transmit FIFO fixed 4 kbyte on-chip EDAC protected RAM memory per Virtual Channel 3, 4, 5 and 6 The Telemetry Encoder programmability is as follows: telemetry Spacecraft Identifier telemetry OCF/CLCW enable telemetry No RF Available and No Bit Lock bits in CLCW overwriting from input pins telemetry Frame Error Control Field (FECF/CRC) enable telemetry Reed-Solomon enable (E=16 coding, interleave depth 5, 160 check symbols) telemetry Pseudo Randomization enable telemetry Convolutional Encoder enable and rate telemetry NRZ-L/ NRZ-M modulation telemetry transfer rate The Telemetry Encoder does not implement the following: no Advanced Orbiting Systems (AOS) support (also no Insert Zone (AOS) and no Frame Header Error Control (FHEC)) no Transfer Frame Secondary Header (also no Extended Virtual Channel Frame Counter) no Turbo Encoding no Split-Phase Level modulation no Sub-carrier modulation Virtual Channels 0, 1 and 2 Virtual Channels 0, 1 and 2 are implemented by means of software support from an external processor via SpaceWire RMAP commands. The input is a partial Transfer Frame. See section 4 for details Virtual Channels 3, 4, 5 and 6 Virtual Channels 3, 4, 5 and 6 are implemented in hardware without any software support being required. Data are input via SpaceWire RMAP commands. See sections 5 and 10 for details. The following Data Link - Protocol Sub-layer [CCSDS-132.0] functionality is implemented: Virtual Channel Generation Transfer Frame Primary Header insertion Transfer Frame Data Field insertion First Header Pointer (FHP) handling and insertion Buffering of two complete Transfer Frames per Virtual Channel CCSDS Space Packet [CCSDS-133.0] data input (or user-defined data-blocks) Virtual Channel 7 Idle Frames are generated on a separate Virtual Channel, using identifier 7. See section

11 11 CCSDS TM / TC and SpaceWire FPGA 1.4 Telecommand decoder The CCSDS Telecommand Decoder implements part of the Data Link Layer, covering the Protocol Sub-layer and the Synchronization and Coding Sub-layer and part of the Physical Layer of the packet telecommand decoder protocol. The Telecommand Decoder supports decoding of higher protocol layers in software, being accessible via a SpaceWire link. It also supports decoding in hardware for bit-parallel output with pulse generation, for which CLCW is produced to on-chip Telemetry Encoder Telecommand decoder specification The following Data Link - Synchronization and Channel Coding Sub-Layer [CCSDS-231.0] functionality is implemented in hardware: Pseudo-De-randomization BCH codeblock decoding Start Sequence Search The following Physical Layer functionality [ECSS-50-05A] is implemented in hardware: Non-Return-to-Zero Mark/Level de-modulation (NRZ-M/L) The telecommand decoder fixed configuration is as follows: fixed telecommand decoder support for CCSDS/ECSS functionality, not ESA PSS The telecommand decoder provide the following pin programmability: telecommand (hardware commands) Spacecraft Identifier (10 pins) telecommand (hardware commands) Virtual Channel Identifier (6 pins) telecommand Pseudo De-randomization enable telecommand NRZ-L / NRZ-M modulation selection telecommand RF available indicator polarity selection telecommand active signal (bit lock) polarity selection telecommand bit clock active edge selection The Telecommand Decoder has multiple separate serial input streams from transponders etc., comprising serial data, clock, channel active indicator (bit lock) and RF carrier available. The input streams are possible to individually disable or enable. The input stream is auto-adaptable Software Virtual Channel The interface between the Telecommand Decoder hardware and software is a SpaceWire link with RMAP protocol. The CLCW produced by the software is input to the Telemetry Encoder via the Telecommand Decoder CLCW Registers (CLCWRn), see section 8.9 for details, using the SpaceWire link with RMAP protocol, with the same information being output on an asynchronous bit serial output suitable for cross-strapping. The higher protocol levels are implemented in software. These software telecommands are stored in external memory and can be accessed via a SpaceWire interfaces. The software implementation of the higher layers of the telecommand decoder allows for implementation flexibility and accommodation of future standard enhancements. See sections 8 and 10 for details.

12 12 CCSDS TM / TC and SpaceWire FPGA Hardware Virtual Channel A separate Virtual Channel for hardware commands is implemented in hardware, without the need of software support. The hardware commands control an external bit-parallel output port, setting or clearing bits individually, or generating pulses. The hardware commands are carried inside the Transfer Frame Data Field, and the Transfer Frame includes the Frame Error Control Field (FECF/CRC). This Application Layer functionality is implemented in hardware: Hardware command decoding and execution: Individually controlled parallel outputs Static logical 0 or 1, or pulsed output Command controlled pulse length This Space Packet Protocol layer [CCSDS-133.0] functionality is implemented in hardware: Packet Extraction Path Recovery This Data Link - Protocol Sub-Layer [CCSDS-232.0] functionality is implemented in hardware: Virtual Channel Packet Extraction Virtual Channel Reception: Support for Command Link Control Word (CLCW) Virtual Channel Demultiplexing Master Channel Demultiplexing All Frames Reception: Frame Delimiting and Fill Removal Procedure; and Frame Validation Check Procedure, in this order. The CLCW is automatically transferred to the on-chip Telemetry Encoder, with the same information being output on an asynchronous bit serial output suitable for cross-strapping. The hardware telecommands are implemented entirely in hardware and do not require any software and can therefore be used for critical operations. See section 9 for details. 1.5 Memory Interface The memory interface support external volatile and non-volatile memory (e.g. MRAM), supporting 32-bit data and 8-bit EDAC check sum, with multiple chip select signals. 1.6 SpaceWire Link Interfaces The SpaceWire links provide an interface between the on-chip bus and a SpaceWire network. They implement the SpaceWire standard [ECSS-E-ST-50-12C] with the protocol identification extension [ECSS-E-ST-50-11C]. The Memory Access Protocol (RMAP) command handler implements the ECSS standard [ECSS-E-ST-50-11C].

13 13 CCSDS TM / TC and SpaceWire FPGA 1.7 On-chip Memory 16 kbyte of on-chip volatile memory is provided for temporary storage of two telemetry transfer frames for each of the Telemetry Virtual Channels 3 through 6, together with a dedicated hard coded descriptor memory containing two descriptors for each channel. Additional general purpose 4 kbyte of on-chip volatile memory is provided and can for example be used for telemetry or telecommand descriptor. All memory is protected by EDAC. Neither automatic scrubbing nor error counter are implemented. 1.8 Interrupt Controller The Interrupt Controller is used to prioritize and propagate interrupt requests from internal devices to a single interrupt output.

14 14 CCSDS TM / TC and SpaceWire FPGA 1.9 Signal overview The signal overview of the telemetry encoder and telecommand decoder is shown in figure 2. clk resetn dsurx Clock & Reset & Interrupt Debug UART irq dsutx transclk clcwin[0:1] tcscid[0:9] tcvcid[0:5] tcrfpos tchigh tcrise tcpseudo tcmark tcrfa[0:3] tcactive[0:3] tcclk[0:3] tcdata[0:3] Telemetry Encoder Telecommand Decoder caduclk[0:3] caduout[0:3] clcwout[0:1] tcgpio[0:31] spw_clk spw_rxd[] spw_rxdn[] spw_rxs[] spw_rxsn[] SpaceWire Links spw_txd[] spw_txdn[] spw_txs[] spw_txsn[] data[31:0] cb[7:0] Memory Interface address[27:0] ramsn[7:0] ramoen[7:0] ramben[3:0] rwen[3:0] romsn[7:0] oen writen Figure 2. Signal overview

15 15 CCSDS TM / TC and SpaceWire FPGA 2 Architecture 2.1 Specification The Telemetry and Telecommand FPGA specification comprises the following elements. CCSDS compliant Telemetry encoder: Input: 7 Virtual Channels Input access via SpaceWire link CCSDS Space Packet data (or any custom data block) CLCW Input via SpaceWire link CLCW internally from hardware commands CLCW externally from two dedicated asynchronous bit serial inputs Output: CADU / encoded CADU NRZ-L / NRZ-M encoding Pseudo-Randomization Reed-Solomon and/or Convolutional encoding Bit synchronous output: clock and data CCSDS compliant Telecommand decoder (software commands): Layers in hardware: Coding layer Input: Auto adaptable bit rate Bit synchronous input: clock, qualifier and data Output: Output access via SpaceWire link CLTU (Telecommand Transfer Frame and Filler Data) CLCW internally connected to Telemetry encoder CLCW on dedicated asynchronous bit serial output CCSDS compliant Telecommand decoder (hardware commands): Layers in hardware: Coding layer Transfer layer (BD frames only) Space Packet Protocol CLCW internally connected to Telemetry encoder Input: Auto adaptable bit rate Bit synchronous input: clock, qualifier and data Telecommand Frame with Space Packet Output: Bit-parallel output with pulse generation CLCW on dedicated asynchronous bit serial output

16 16 CCSDS TM / TC and SpaceWire FPGA 2.2 Interfaces The following interfaces are provided: Telemetry Telemetry transmitter clock input CLCW externally from two dedicated asynchronous bit serial inputs Physical layer output: Two sets of bit synchronous output: clock and data One set of bit synchronous output: clock and data for EGSE One set of Manchester encoded data output for EGSE (Manchester as per IEEE when GRTM physical layer register bit SF=0) (Manchester as per G.E. Thomas when GRTM physical layer register bit SF=1) Telecommand Physical layer input: Four sets of bit synchronous input: data, qualifier (bit lock), clock and RF status Hardware commands: Bit-parallel output CLCW on dedicated asynchronous bit serial output (hardware commands) CLCW on dedicated asynchronous bit serial output (software commands) System level Memory interface (SRAM and PROM chip selects, read and write strobes, 32-bit data, 8- bit checksum, at least 21 bit address) Interrupt output System clock and reset SpaceWire link with RMAP support for software telemetry and telecommand SpaceWire link with RMAP support for hardware telemetry (VC3 - VC4) SpaceWire link with RMAP support for hardware telemetry (VC5 - VC6) SpaceWire transmitter clock input 2.3 Clock and reset The system clock is taken directly from a separate external input. The telemetry transmitter clock is derived from a separate external input. The SpaceWire transmitter clock is derived from a separate external input. The device is reset with a single external reset input that need not be synchronous with the system clock input. 2.4 Performance Telemetry downlink rate is programmable up to at least 2 Mbit/s, based on a 8 MHz input clock. Telecommand uplink rate up to at least 100 kbit/s is supported. SpaceWire links rate up to at least 10 Mbit/s is supported, based on a 10 MHz input clock. System clock frequency up to at least 20 MHz is supported, based on a 20 MHz input clock.

17 17 CCSDS TM / TC and SpaceWire FPGA 2.5 IP cores The architecture is based on cores from the GRLIB IP library. The vendor and device identifiers for each core can be extracted from the plug & play information. The used IP cores are listed in table 1. Table 1. Used IP cores Core Function Vendor Device AHBCTRL AHB Arbiter & Decoder 0x01 - APBCTRL AHB/APB Bridge 0x01 0x006 AHBUART Serial/AHB debug interface 0x01 0x007 FTSRCTRL PROM/SRAM/IO Memory Interface 0x01 0x051 FTAHBRAM On-chip SRAM with EDAC 0x01 0x050 AHBSTAT AHB failing address register 0x01 0x052 IRQMP Interrupt controller 0x01 0x00D GRSPW SpaceWire link with RMAP 0x01 0x01F GRTC CCSDS TC Decoder 0x01 0x031 GRTM CCSDS TM Encoder 0x01 0x030 GRTM_PAHB CCSDS TM Encoder Virtual Channel Generation Input 0x01 0x088 GRTM_VC CCSDS TM Encoder Virtual Channel Generation 0x01 0x085 GRTM_DESC CCSDS TM Encoder Descriptors 0x01 0x084 GRTC HW CCSDS TC Decoder - Hardware Commands Interrupts See the description of the individual cores for how and when the interrupts are raised. Table 2. Interrupt assignment Core Interrupt Comment AHBSTAT 4 AHB failing address register GRTM_PAHB 7-8, 9-10, 11-12, CCSDS TM Encoder Virtual Channel Generation Input (VC3-6) GRTC 5 CCSDS TC Decoder GRTM 6 CCSDS TM Encoder 2.7 Memory map The internal architecture is based on three sets of AMBA AHB and AMBA ABP buses. The three sets are separated from each other. See figure 1 for details. The memory map shown in tables 3, 5 and 7 is based on the AMBA AHB address space. Access to addresses outside the ranges will return an AHB error response. The detailed register layout is defined in the description of each individual core. The control registers of most on-chip peripherals are accessible via the AHB/APB bridge, which is mapped at address 0x The memory map shown in tables 4, 6 and 8 is based on the AMBA AHB address space.

18 18 CCSDS TM / TC and SpaceWire FPGA Table 3. AMBA AHB address range - primary bus Core Address range Area FTSRCTRL 0x x x x PROM area SRAM area APBCTRL 0x x APB bridge FTAHBRAM 0xA xB On-chip RAM, 4 kbyte FTAHBRAM 0xB xC On-chip RAM, 16 kbyte GRTM_DESC 0xC xD CCSDS TM Encoder Descriptors (VC3 - VC6) GRTC 0xFFF xFFF10000 CCSDS TC Decoder AHB plug&play 0xFFFFF000-0xFFFFFFFF Plug & Play Table 4. APB address range - primary bus Core Address range Comment IRQMP 0x x Interrupt controller FTSRCTRL 0x x Memory controller AHBSTAT 0x x AHB failing address register FTAHBRAM 0x x On-chip RAM, 4 kbyte FTAHBRAM 0x x On-chip RAM, 16 kbyte AHBUART 0x x Serial/AHB debug interface GRTM 0x x CCSDS TM Encoder APB plug&play 0x800FF000-0x Plug & Play Table 5. AMBA AHB address range - secondary bus Core Address range Area GRTM_PAHB 0xFFF xFFF80000 CCSDS TM Encoder VC Generation Input VC3 GRTM_PAHB 0xFFF xFFF90000 CCSDS TM Encoder VC Generation Input VC4 AHB plug&play 0xFFFFF000-0xFFFFFFFF Plug & Play Table 6. APB address range - secondary bus Core Address range Comment GRTM_PAHB 0x x CCSDS TM Encoder VC Generation Input VC3 GRTM_PAHB 0x x CCSDS TM Encoder VC Generation Input VC4 APB plug&play 0x800FF000-0x Plug & Play

19 19 CCSDS TM / TC and SpaceWire FPGA Table 7. AMBA AHB address range - third bus Core Address range Area GRTM_PAHB 0xFFF xFFFA0000 CCSDS TM Encoder VC Generation Input VC5 GRTM_PAHB 0xFFFA0000-0xFFFB0000 CCSDS TM Encoder VC Generation Input VC6 AHB plug&play 0xFFFFF000-0xFFFFFFFF Plug & Play Table 8. APB address range - third bus Core Address range Comment GRTM_PAHB 0x x800A0000 CCSDS TM Encoder VC Generation Input VC5 GRTM_PAHB 0x800A0000-0x800B0000 CCSDS TM Encoder VC Generation Input VC6 APB plug&play 0x800FF000-0x Plug & Play 2.8 Signals The functional signals are shown in table 9. Note that index 0 is MSB for TM/TC signals. Table 9. External signals Name Usage Direction Polarity Reset clk System and telemetry transmitter clock In Rising - resetn System reset In Low - irq System interrupt Out High Low dsutx Debug UART transmit data Out Low - dsurx Debug UART receive data In Low - transclk Telemetry transmitter clock In High - caduclk[0:2] Telemetry CADU serial bit clock output Out - Low caduout[0:2] Telemetry CADU serial bit data output Out - Low caduclk[3] Telemetry CADU serial bit clock output Out - Low caduout[3] Telemetry CADU serial bit data output, Manchester coded Out - Low tcscid[0:9] Telecommand Spacecraft identifier In - - tcvcid[0:5] Telecommand (hardware command) Virtual Channel identifier In - - tcrfpos Telecommand RF Available positive level selection In High - tchigh Telecommand input active (bit lock) positive level selection In High - tcrise Telecommand serial bit clock rising edge selection In High - tcpseudo Telecommand Pseudo-Derandomiser decoder enable In High - tcmark Telecommand NRZ-M de-modulation enable In High - tcrfa[0:3] Telecommand CLTU RF available indicator In - - tcactive[0:3] Telecommand CLTU input active indicator (bit lock) In - - tcclk[0:3] Telecommand CLTU serial bit clock input In - - tcdata[0:3] Telecommand CLTU serial bit data input In - - tcgpio[0:31] Telecommand (hardware command) parallel output Out High Low

20 20 CCSDS TM / TC and SpaceWire FPGA Table 9. External signals Name Usage Direction Polarity Reset clcwin[0:1] Telemetry CLCW asynchronous bit serial inputs In - - clcwout[0:1] Telecommand CLCW asynchronous bit serial outputs Out - High spw_clk Transmitter default run-state clock In Rising - spw_rxd[0:2] Data input, positive In High - spw_rxdn[0:2] Data input, negative {spare} In, LVDS Low - spw_rxs[0:2] Strobe input, positive In High - spw_rxsn[0:2] Strobe input, negative {spare} In, LVDS Low - spw_txd[0:2] Data output, positive Out High Low spw_txdn[0:2] Data output, negative {spare} Out, LVDS Low Low spw_txs[0:2] Strobe output, positive Out High Low spw_txsn[0:2] Strobe output, negative {spare} Out, LVDS Low Low address[27:0] Memory word address Out High - data[31:0] Memory data bus BiDir High Tristate cb[7:0] Memory checkbits BiDir High Tristate ramsn[7:0] SRAM chip selects Out Low High ramoen[7:0] SRAM output enable Out Low High ramben[3:0] SRAM read/write byte enable Out Low High rwen[3:0] SRAM write enable strobe Out Low High romsn[7:0] PROM chip select Out Low High oen PROM output enable Out Low High writen PROM write strobe Out Low High

21 21 CCSDS TM / TC and SpaceWire FPGA 2.9 Abbreviations and acronyms AHB AHBCTRL AMBA AOS APB APBCTRL ARM ASIC ASM BCH CADU CCSDS CLCW CLTU CMOS COP-1 CQFP CRC DMA ECSS EDAC EGSE EM ESA FARM FECF FHEC FHP FIFO FM FPGA FSH FTAHBRAM FTMCTRL FTSRCTRL AMBA Advanced High-Speed Bus AMBA AHB Controller with plug&play support (IP core) Advanced Microcontroller Bus Architecture Advanced Orbiting Systems AMBA Advanced Peripheral Bus AMBA AHB/APB Bridge with plug&play support (IP core) Advanced RISC Machine Application Specific Integrated Circuit Attached Synchronization Marker Bose Chaudhuri Hocquenghem Channel Access Data Unit Consultative Committee for Space Data Systems Command Link Control Word Command Link Transfer Unit Complementary Metal-Oxide Semiconductor Communications Operation Procedure-1 Ceramic Quad Flat Package Cyclic Redundancy Code Direct Memory Access European Cooperation on Space Standardization Error Detection And Correction Electrical Ground Support Equipment Engineering Model European Space Agency Frame Acceptance and Reporting Mechanism Frame Error Control Field Frame Header Error Control First Header Pointer First In First Out Flight Model Field Programmable Gate Array Frame Secondary Header On-chip SRAM with EDAC and AHB interface (IP core) Memory Controller with EDAC (IP core) Fault Tolerant 32-bit PROM/SRAM/IO Controller (IP core)

22 22 CCSDS TM / TC and SpaceWire FPGA GF GPIO GRLIB GRSPW GRTC GRTM HDL ID I/O IP IRQMP JTAG kbit/s kbps kbyte LET LFSR LSB LVTTL Mbit/s Mbps MByte MC MC_OCF MHz MRAM MSB NRZ-L NRZ-M OCF PROM PSR PSS RF RISC RMAP Galois Field General Purpose Input Output Aeroflex Gaisler VHDL IP Core Library SpaceWire codec with AHB host Interface and RMAP support (IP core) Telecommand Decoder Telemetry Encoder Hardware Description Language Identifier Input/Output Intellectual Property Interrupt Controller (IP core) Joint Test Action Group Thousand bits per second Thousand bits per second 1024 bytes Linear Energy Transfer Linear Feedback Shift Register Least Significant Bit/Byte Low Voltage Transistor Transistor Logic Million bits per second Million bits per second bytes Master Channel Master Channel associated Operation Control Field Million Hertz Magneto-resistive Random Access Memory Most Significant Bit/Byte Non Return to Zero - Level encoding Non Return to Zero - Mark encoding Operational Control Field Programmable Ready Only Memory Pseudo Randomiser Procedures, Standards and Specifications Radio Frequency Reduced Instruction Set Computing Remote Memory Access Protocol

23 23 CCSDS TM / TC and SpaceWire FPGA RS SCID SEL SEU SRAM TBD TC TM UART VC VHDL VHSIC XOR Reed-Solomon Spacecraft Identifier Single Event Latch-up Single Event Upsets Static Random Access Memory To Be Defined Telecommand Telemetry Universal Asynchronous Receiver Transmitter Virtual Channel VHSIC Hardware Description Language Very High Speed Integrated Circuit Exclusive-or

24 24 CCSDS TM / TC and SpaceWire FPGA 3 Conventions 3.1 Consultative Committee for Space Data Systems Convention according to the Consultative Committee for Space Data Systems (CCSDS) recommendations, applying to all relevant structures: The most significant bit of an array is located to the left, carrying index number zero, and is transmitted first. An octet comprises eight bits. General convention, applying to signals and interfaces: Signal names are in mixed case. An upper case '_N' suffix in the name indicates that the signal is active low. CCSDS n-bit field most significant least significant 0 1 to n-2 n Galois Field Table 10. CCSDS n-bit field definition Convention according to the Consultative Committee for Space Data Systems (CCSDS) recommendations, applying to all Galois Field GF(28) symbols: A Galois Field GF(28) symbol comprises eight bits. The least significant bit of a symbol is located to the left, carrying index number zero, and is transmitted first. Galois Field GF(2 8 ) symbol least significant most significant 0 1 to 6 7 Table 11. Galois Field GF(2 8 ) symbol definition

25 25 CCSDS TM / TC and SpaceWire FPGA 3.3 Telemetry Transfer Frame format The Telemetry Transfer Frame specified in [CCSDS-132.0] and [ECSS-50-03A] is composed of a Primary Header, a Secondary Header, a Data Field and a Trailer with the following structures. Transfer Frame Transfer Frame Header Transfer Frame Data Field Transfer Frame Trailer Primary Secondary (optional) ket Packet Pa OCF / FECF (optional) 6 octets variable variable 0 / 2 /4 / 6 octets up to 2048 octets Table 12. Telemetry Transfer Frame format Version 2 bits 0:1 Transfer Frame Primary Header Frame Identification Master Channel S/C Id VC Id OCF Flag Frame Count 10 bits 2:11 3 bits 12:14 1 bit 15 Virtual Channel Frame Count Frame Data Field Status 8 bits 8 bits 16 bits 2 octets 1 octet 1 octet 2 octets Table 13. Telemetry Transfer Frame Primary Header format Frame Data Field Status Secondary Header Flag Sync Flag Packet Order Flag Segment Length Id First Header Pointer 1 bit 0 1 bit 1 1 bit 2 2 bits 3:4 11 bits 5:15 2 octets Table 14. Part of Telemetry Transfer Frame Primary Header format Transfer Frame Secondary Header (optional) Secondary Header Identification Secondary Header Data Field Secondary Header Version Secondary Header Length Custom data 2 bits 0:1 6 bits 2:7 1 octet up to 63 octets Table 15. Telemetry Transfer Frame Secondary Header format Transfer Frame Trailer (optional) Operational Control Field (optional) Frame Error Control Field (optional) 0 / 4 octets 0 / 2 octets Table 16. Telemetry Transfer Frame Trailer format

26 26 CCSDS TM / TC and SpaceWire FPGA 3.4 Reed-Solomon encoder data format The applicable standards [CCSDS-131.0] and [ECSS-50-01A] specify a Reed-Solomon E=16 (255, 223) code resulting in the frame lengths and codeblock sizes listed in table 17. Interleave depth Attached Synchronization Marker Transfer Frame Reed-Solomon Check Symbols 1 4 octets 223 octets 32 octets octets 64 octets octets 96 octets octets 128 octets octets 160 octets octets 256 octets Table 17. Reed-Solomon E=16 codeblocks with Attached Synchronisation Marker The applicable standards [CCSDS-131.0] also specifies a Reed-Solomon E=8 (255, 239) code resulting in the frame lengths and codeblock sizes listed in table 18. Interleave depth Attached Synchronization Marker Transfer Frame Reed-Solomon Check Symbols 1 4 octets 239 octets 16 octets octets 32 octets octets 48 octets octets 64 octets octets 80 octets octets 128 octets Table 18. Reed-Solomon E=8 codeblocks with Attached Synchronisation Marker 3.5 Attached Synchronization Marker The Attached Synchronization Marker pattern depends on the encoding scheme in use, as specified in [CCSDS-131.0] and [ECSS-50-01A] as shown in table 19. Mode Nominal Hexadecimal stream (left to right) 1ACFFC1D h Table 19. Attached Synchronization Marker hexadecimal pattern

27 27 CCSDS TM / TC and SpaceWire FPGA 3.6 Telecommand Transfer Frame format The Telecommand Transfer Frame specified in [CCSDS-232.0] and [ECSS-50-04A] is composed of a Primary Header, a Data Field and a trailer with the following structures. Transfer Frame Transfer Frame Primary Transfer Frame Data Field Frame Error Control Field Header Segment Header (optional) ket Packet Pa FECF (optional) 5 octets variable variable 2 octets up to 1024 octets Table 20. Telecommand Transfer Frame format Transfer Frame Primary Header Version Bypass Flag Control Command Flag Reserved Spare S/C Id Virtual Channel Id Frame Length Frame Sequence Number 2 bits 1 bit 1 bit 2 bits 10 bits 6 bits 10 bits 8 bits 0: :15 16:21 22:31 32:39 2 octets 2 octets 1 octet1 Table 21. Telecommand Transfer Frame Primary Header format Sequence Flags 3.7 Command Link Control Word Segment Header (optional) Multiplexer Access Point (MAP) Id 2 bits 6 bits 40:41 42:47 Table 22. Transfer Frame Secondary Header format 1 octet The Command Link Control Word (CLCW) can be transmitted as part of the Operation Control Field (OCF) in a Transfer Frame Trailer. The CLCW is specified in [CCSDS-232.0] and [ECSS-50-04A] and is listed in table 23. Command Link Control Word Control Word Type Version Number Status Field COP in Effect Virtual Channel Identifier Reserved Spare 0 1:2 3:5 6:7 8:13 14:15 1 bit 2 bits 3 bits 2 bits 6 bits 2 bits No RF Available No Bit Lock Lock Out Wait Retransmit FARM B Counter Reserved Spare Report Value : :31 1 bit 1 bit 1 bit 1 bit 1 bit 2 bits 1 bit Table 23. Command Link Control Word

28 28 CCSDS TM / TC and SpaceWire FPGA 3.8 Space Packet The Space Packet defined in the CCSDS [CCSDS-133.0] recommendation and is listed in table 24. Primary Header 3.9 Asynchronous bit serial data format Space Packet The asynchronous bit serial interface complies to the data format defined in [EIA232]. It also complies to the data format and waveform shown in table 25 and figure 3. The interface is independent of the transmitted data contents. Positive logic is considered for the data bits. The number of stop bits can optionally be either one or two. The parity bit can be optionally included SpaceWire Remote Memory Access Protocol (RMAP) A general definition of RMAP commands is specified in [RMAP]. Packet Data Field Packet Packet Identification Packet Sequence Control Packet Secondary User Packet Version Type Secondary Application Sequence Sequence Data Header Data Error Number Header Flag Process Id Flags Count Length (optional) Field Control 0: :15 16:17 18:31 32:47 (optional) 3 bits 1 bit 1 bit 11 bits 2 bits 14 bits 16 bits variable variable variable Table 24. CCSDS Space Packet format Asynchronous bit serial format General data format i = {0, n} start D0 D1 D2 D3 D4 D5 D6 D7 parity stop stop first lsb msb last Table 25. Asynchronous bit serial data format 8*i+7 8*i+6 8*i+5 8*i+4 8*i+3 8*i+2 8*i+1 8*i last first For Telemetry Virtual Channels 3 through 6, a complete CCSDS Space Packet [CCSDS-133.0] is carried inside an RMAP write command [RMAP], which in turn is carried inside a SpaceWire packet [SPW], as shown in the table 26. SpaceWire Packet Destination Address Cargo EOP RMAP Write Command Target SpaceWire Address Target Logical Address Protocol Identifier Instruction Key Reply Address Initiator Logical Address Transaction Identifier Extended Address Address Data Length Header CRC Data Data CRC EOP CCSDS Space Packet CCSDS Space Packet optional, variable 1 byte 1 byte 1 byte 1 byte optional, variable 1 byte 2 bytes 1 byte 4 bytes 3 bytes 1 byte variable 1 byte token Table 26. CCSDS Space Packet, inside RMAP write command, inside SpaceWire packet

29 29 CCSDS TM / TC and SpaceWire FPGA 3.11 Command Link Control Word interface (CLCW) Table 27. CLCW transmission protocol Byte Number CLCW register bits CLCW contents First [31:24] Control Word Type CLCW Version Number Second [23:16] Virtual Channel ID Reserved Field Status Field Third [15:8] No RF Available No Bit Lock Lock Out Fourth [7:0] Report Value Fifth N/A [RS232 Break Command] COP In Effect Wait Retransmit Farm B Counter Report Type 3.12 Waveform formats The design receives and generates the waveform formats shown in the following figures. Start bit Data Stop bits Start LSB MSB Stop Start LSB MSB Stop Stop Start bit Data Parity Stop bits Start LSB MSB P Stop Start LSB MSB P Stop Stop Start Break Figure 3. Asynchronous bit serial protocol / waveform Stop Delimiter Clock Data n-8 n-7 n-6 n-5 n-4 n-3 n-2 n-1 MSB Figure 4. Telecommand input protocol / waveform LSB Data: Clock Manchester Figure 5. Manchester encoded waveform (IEEE 802.3) (when GRTM physical layer register bit SF=0)

30 30 CCSDS TM / TC and SpaceWire FPGA 4 Telemetry Encoder 4.1 Overview The CCSDS/ECSS/PSS Telemetry Encoder implements part of the Data Link Layer, covering the Protocol Sub-layer and the Frame Synchronization and Coding Sub-layer and part of the Physical Layer of the packet telemetry encoder protocol. The operation of the Telemetry Encoder is highly programmable by means of control registers. The Telemetry Encoder comprises several encoders and modulators implementing the Consultative Committee for Space Data Systems (CCSDS) recommendations, European Cooperation on Space Standardization (ECSS) and the European Space Agency (ESA) Procedures, Standards and Specifications (PSS) for telemetry and channel coding. The encoder comprises the following: Packet Telemetry Encoder (TM) Reed-Solomon Encoder Pseudo-Randomiser (PSR) Non-Return-to-Zero Level / Mark encoder (NRZ-L/NRZ-M) Convolutional Encoder (CE) Clock Divider (CD) Note that the SpaceWire input interface is described separately. The SpaceWire interfaces and corresponding Virtual Channel Generation function and buffer memories are not shown in the block diagram below, as is the case for the CLCW multiplexing function. AMBA AHB AMBA AHB Master DMA FIFO Virtual Channel & Master Channel Frame Services Virtual Channel Generation Virtual Channel Mux Master Channel Generation Master Channel Mux All Frame Generation Idle Frame Generation OCF Data Link Protocol Sub-Layer AMBA APB AMBA APB Slave System clock domain Attached Sync Mark Reed-Solomon Pseudo-Randomiser Coding Sub-Layer GRTM NRZ-L Convolutional - - Octet clock domain Transponder clock domain Clock Divider Physical Layer Telemetry output Figure 6. Block diagram

31 31 CCSDS TM / TC and SpaceWire FPGA 4.2 Layers Introduction The relationship between Packet Telemetry standard and the Open Systems Interconnection (OSI) reference model is such that the OSI Data Link Layer corresponds to two separate layer, namely the Data Link Protocol Sub-layer and Synchronization and Channel Coding Sub-Layer Data Link Protocol Sub-layer The following functionality is not implemented in the core: Packet Processing Virtual Channel Frame Service (DMA functionality only) (see also Virtual Channel 3, 4, 5 and 6) Master Channel Frame Service (only single Spacecraft Identifier supported) Master Channel Multiplexing (only single Spacecraft Identifier supported) The following functionality is implemented in the core: Virtual Channel Generation (for Virtual Channels 3, 4, 5 and 6) Virtual Channel Generation (for Idle Frame generation only, e.g. Virtual Channel 7) Master Channel Generation (for all frames) All Frame Generation (for all frames) Synchronization and Channel Coding Sub-Layer The following functionality is implemented in the core: Attached Synchronization Marker Reed-Solomon coding Pseudo-Randomiser Convolutional coding Physical Layer The following functionality is implemented in the core: Non-Return-to-Zero Level / Mark modulation 4.3 Data Link Protocol Sub-Layer Physical Channel The configuration of a Physical Channel covers the following parameters: Transfer Frame Length is fixed to 1115 octets Transfer Frame Version Number is fixed to 0, i.e. Packet Telemetry

32 32 CCSDS TM / TC and SpaceWire FPGA Virtual Channel Frame Service The Virtual Channel Frame Service is implemented by means of a DMA interface, providing the user with a means for inserting Transfer Frames into the Telemetry Encoder. Transfer Frames are automatically fetched from memory, for which the user configures a descriptor table with descriptors that point to each individual Transfer Frame. For each individual Transfer Frame the descriptor also provides means for bypassing functions in the Telemetry Encoder. This includes the following: Virtual Channel Counter generation can be enabled in the Virtual Channel Generation function (this function is normally only used for Idle Frame generation but can be used for the Virtual Channel Frame Service when sharing a Virtual Channel, e.g. Virtual Channel 7) Master Channel Counter generation can be bypassed in the Master Channel Generation function Operational Control Field (OCF) generation can be bypassed in the Master Channel Generation function Frame Error Control Field (FECF) generation can be bypassed in the All Frame Generation function Note that the above features can only be bypassed for each Transfer Frame, the overall enabling of the features is done for the corresponding functions in the Telemetry Encoder, as described in the subsequent sections. The detailed operation of the DMA interface is described in section Virtual Channel Generation - Virtual Channels 3, 4, 5 and 6 There is a Virtual Channel Generation function for each of Virtual Channels 3, 4, 5 and 6. The channels have each an on-chip memory buffer to store two complete Transfer Frames (see section 12). Each Virtual Channel Generation function receives data from the SpaceWire interface that are stored in the on-chip memory buffer that is EDAC protected (see section 5). The function supports: Transfer Frame Primary Header insertion Transfer Frame Data Field insertion (with support for different lengths due to OCF and FECF) First Header Pointer (FHP) handling and insertion The function keeps track of the number of octets received and the packet boundaries in order to calculated the First Header Pointer (FHP). The data are stored in pre-allocated slots in the buffer memory comprising complete Transfer Frames. The module fully supports the FHP generation and does not require any alignment of the packets with the Transfer Frame Data Field boundary. The buffer memory space allocated to each Virtual Channel is treated as a circular buffer. The function communicates with the Virtual Channel Frame Service by means of the on-chip buffer memory. The data input format can be CCSDS Space Packet [CCSDS-133.0] or any user-defined data-block (see section 5). The Virtual Channel Generation function for Virtual Channels 3, 4, 5 and 6 is enabled through the GRTM DMA External VC Control register. The transfer is done automatically via the Virtual Channel Frame Service (i.e. DMA function) Virtual Channel Generation - Idle Frames - Virtual Channel 7 The Virtual Channel Generation function is used to generate the Virtual Channel Counter for Idle Frames as described here below.