Building Blocks For System on a Chip Spacecraft Controller on a Chip

Transcription

1 PIO/TEST/WDOGN/ 19 ERRORN 2 Clock, Reset CT_PULSE CT_EVENT SWB0 : Space Wire SWB1 : Space Wire SWB2 : Space Wire HKP Housekeeping Packetizer Context RA CT CCSDS Time anager SWT SWITCH ATRIX IT from IP1553, PTCDIP, CT, HDA,SWB, IOCTRL IT AHB I/F CON FIG IT ngt IRQCTRL2 Secondary interrupt controller Encoder Decoder IP I/F Clock RX0, TX0 RX1, TX1 RTAD APB CPU AHB PTCDIP 8 LEON Peripherals TIER & IRQCTRL UARTs WATCHDOG APBST AHB/APB Bridge CONFI GURAT ION 3 APB extended extended AP CPDU I/F I/F TCDAT RSTTCN LAC TC inputs CPDU I/F CTRL TCC, TCA, TCS 4 channels IT ngt TC Report generator AP I/F to CPU Serial AP I/F IU SPARC V8 CPU IOAHBARB : IO AHB Arbiter IT DCACHE 32 Kbits Acache AHBARB CPU AHB Arbiter Decoder VCLSB RFAVN ICACHE 32 Kbits HDA : CPU AHB / IO AHB DA HK APB Config uration FPU EIKO IO AHB I/F VC0 T clock LEON IP CORE CTRL RA Controller PCI WRAPPER ASTER / SLAVE 8x32 8x32 4 Assembly ultiplexing RS Turbo Encoder 2 T output 4 83 PCI ASTER/ 50 TARGET 33 Hz PCI Arbiter RS RS APB APB APB PW PW IOCTRL IO RA Idle Frame 6 PTE PCI bus PCI bus Arbitration lines for 3 other masters TC PRO 6 ctrl data 19 ad external SRA 4 bits PW I/F PW I/F RS232 I/F T inputs RS232 I/F CPU EXTERNAL PRO CPU EXTERNAL EORY Blocks provided by ESA Blocks purchased by commercial vendors Blocks provided by ASTRIU Blocks designed for COO3 RA FIFO Building Blocks For System on a Chip Spacecraft Controller on a Chip ESTEC contract COO3 Spacecraft Controller-On-a-Chip Block Diagram S S S S S S S Controller 16 IO AHB I/F VC1 VC2 VC3 VC4 VC5 VC6 BC RT B PTD IP 18 Kgates EADS Astrium drawing reference : 5 Feb issue 08 arc LEFEBVRE arc SOUYRI marc.lefebvre@astrium.eads.net marc.souyri@astrium.eads.net Page 1 icroelectronics Presentation Days. 4 and 5 of February 2004

2 Content 1. Contract and Studies presentation 2. Architecture and main IP blocks of the System On a Chip (SOC) a. Overall architecture b. Performances 3. Detailed design and breadboarding a. Detailed design results b. Test environment and results 4. Results of the study Page 2 icroelectronics Presentation Days. 4 and 5 of February 2004

3 Contract and study presentation COO3 is phase 3 of ESA contract called Building Blocks for System on a Chip. Development of a modular architecture Based on a standard bus : ABA T AHB and APB Based on standard services : interrupt, synchronization Development of re-usable IP cores Use of existing IP cores from different sources : Company internal IP cores ESA provided IP cores Re-use of previous VHDL ASIC developments Page 3 icroelectronics Presentation Days. 4 and 5 of February 2004

4 Development Plan Classical development approach of an ASIC Architectural design with full VHDL RTL simulation IP core interconnection study Adaptation of the previous ASIC design Global simulation of the SoC Detailed design performed targeting a XILINX FPGA But with specific methodology for SoC design odular approach of the SoC : progressive integration of the IP cores Validation of the IP core at block level Validation of the interconnection scheme at upper level Page 4 icroelectronics Presentation Days. 4 and 5 of February 2004

5 Environment of the SCoC Spacecraft Controller on a Chip Heater Sensors Thermal control - Drive Electronic - onitoring PCI Actuators PCI ON BOARD CONTROLLER Payload Power control Low Rate edium rate T LEON CPU Low Rate TC SCoC edium Rate SPW Nom. + Red. SPW Router ass emory Star tracker Transponders Page 5 icroelectronics Presentation Days. 4 and 5 of February 2004

6 IP cores integrated into the SCoC Includes the main digital functions able to perform the Data Handling of a Spacecraft : The processor based on LEON with its FPU A parallel bus at board level : PCI A fast serial link : SpaceWire Link A CCSDS Time anagement function A serial bus for control of remote equipments : 1553 A Telecommand function based on PTCD design A Telemetry function based on PTE IP Automatic housekeeping generation Page 6 icroelectronics Presentation Days. 4 and 5 of February 2004

7 SCoC Simplified Architecture UARTS LEON (CPU) CPU AHB High performance IO bus PCI Bus PCI CT 1553 BC/B/RT 1553 Bus Spacewire Spacewire 1 PTE T, CLCW PW,PA HDA Spacewire Spacewire 2 PTCD TC,AP LAC, CLCW Spacewire Spacewire 3 House Keeping IO emory Controller SRA PRO SRA PRO CPU emory controller IO AHB Latency Controlled IO bus Page 7 icroelectronics Presentation Days. 4 and 5 of February 2004

8 Distributed DA control DA controller are integrated at IP core level in order to have Core specific capabilities Into the PCI interface : burst access, prefetch Into the Spacewire : double buffer management, linked list of packets Into the il-std-1553 : Spacewire The Spacewire directly transmits a linked list of packet when the address of the first descriptor is provided Packet size Data Address Next Descriptor Packet size Data Address Next Descriptor Packet size Data Address 0 Packet Data Packet Data Packet Data programmable Bus Controller The spacewire handles 2 programmable buffer areas in the memory and switch automatically between them CPU emory StartArea1 EndPacketArea1 EndArea1 Area 1 Page 8 icroelectronics Presentation Days. 4 and 5 of February 2004 StartArea2 EndPacketArea2 EndArea2 Area 2

9 IP Core synchronisation ost of IP core can receive or distribute synchronisation signals : spacewire, PTE, 1553, CT odular time distribution implemented to adapt the SCoC to specific system requirements Spacewire 2 Spacewire 1 Spacewire BC/B/ RT Switch atrix PTE External Pulses PTCD Page 9 icroelectronics Presentation Days. 4 and 5 of February 2004 CT

10 Performance of the system The SCoC presents limitation Bottleneck identified at CPU SRA level and AHB bus Reduces maximum performances COPUTATION OF PERFORANCES ON CPU AHB BUS Global Hypothesis asters Hypotheses aximum allowed bus load 80% Processor Bus Frequency 100 Hz CPU usage ratio 65,5% Instruction cache hit ratio 80% Slaves Hypotheses Data cache hit ratio 80% emory controller Load instruction ratio 10% RA Read Wait states 0 Store instruction ratio 5% RA Write Wait States 0 Instruction cache fill burst length 4 CTRL AHB WS on first read access 3 CTRL AHB WS on next read access 2 Spacewire CTRL AHB WS on first write access 3 overall Spacewire TX bit rate 100 bits/s CTRL AHB WS on next write access 2 overall Spacewire RX bit rate 100 bits/s PCI PCI write rate PCI read rate 0,5 words/s 0,5 words/s Page 10 icroelectronics Presentation Days. 4 and 5 of February 2004

11 Possible Performance Enhancement Use of ulti-layer AHB and a second external RA interface LEON (CPU) CPU emory controller Spacewire 1 Spacewire 2 Spacewire 3 PTCD PTE PCI High Speed IO emory controller Low Speed IO emory Controller DA controller 1553 BC/B/RT 3 layers AHB interconnect matrix Increases the number of external I/O (which is already high) Page 11 icroelectronics Presentation Days. 4 and 5 of February 2004

12 . odularity in simulation environment.tb.tb Each IP core is associated to an emulator handling the protocol and verification of the external I/Os.tb SpaceWire 1553 SCOC PCI T TC.tb EXTERN SIGNALS.tb SRA/PRO CPU SUPPORT PROCESSOR SRA/PRO IO CONTROLLER SOFT EORY.dat.dat.dat EORY SPY.tb Page 12 icroelectronics Presentation Days. 4 and 5 of February 2004

13 Detailed design targeting XILINX XCV2000-E Full SCoC design does not fit into the selected FPGA odular approach of SCoC allowed targeting reduced SCoC definitions Configuration 1 : PCI, 1553 and Spacewires Configuration 2 : with PCI, T/TC and housekeeping Configuration PCI, 1553, SPW PCI, TTC ax Frequency 23.7 Hz (WC path in IU of LEON1) 20.8 Hz (WC path in PTE) Resource usage 97 % of slices 96 % of slices Page 13 icroelectronics Presentation Days. 4 and 5 of February 2004

14 Prototyping of the SCoC BLADE Board Board developed for the evaluation of the SCoC Design implemented in XILINX VIRTEX-E FPGA CompacPCI 6U standard board Specific interfaces implemented on the board 1553 transceiver Spacewire interfaces T/TC interfaces (RS232, RS422) Embedded FPGA to conduct test without need of specific external hardware (EGSE) Page 14 icroelectronics Presentation Days. 4 and 5 of February 2004

15 BLADE board description Power regulation XCV2000E for SCoC integration XCV300E for Test integration SCoC emory banks Spacewire connector il-std-1553 transceivers Page 15 icroelectronics Presentation Days. 4 and 5 of February 2004

16 Test results All functionalities of the SCoC are activated Test of performances for PCI and Spacewire interfaces : Spacewire :High efficient DA controller allow high speed transfer with little CPU usage PCI : The system clock limits the performances reached on the PCI bus Page 16 icroelectronics Presentation Days. 4 and 5 of February 2004

17 COO3 Study results This study permit to : Evaluate the methodology of the design of a large ASIC based on the use of IP core Verification at SoC level versus verification at IP level anagement of the configuration of the SCoC with IP cores coming from different sources Development of modular designs Develop the library of available IP cores for use in space applications PTCD, PTE, 1553, CT, ABA bus related IP Page 17 icroelectronics Presentation Days. 4 and 5 of February 2004

18 Conclusion BLADE Board used for A3 R&T : VxWorks on LEON Use of Spacewire for data exchange Use of CT for time synchronisation This activity is a good starting point ABA can be used as standard for internal busses ethodology of IP integration for complex ASIC developments Astrium gained experience in the development of complex integrated system Page 18 icroelectronics Presentation Days. 4 and 5 of February 2004