Fifth SpaceWire WG Meeting SpaceWire based On-Board-Computer

Transcription

1 Fifth SpaceWire WG Meeting SpaceWire based On-Board-Computer

2 On Board Computer Concept Page 2

3 OBC Concept -Aims- Based on ERC32 32-bit processor cores Fully redundant Each function provided in two independent electrically and mechanically separated modules Point-to-Point SpaceWire/1355 Modular design to allow easy adaptation to customer requirements Redundancy concept allowing to switch between individual functions or switch-over of complete computer function Single-Point Failure free High reliability for e.g. 15 years GEO Missions Integrated high speed test interface (Service I/F) SIF Page 3

4 OBC Concept -System Architecture- Core Functional Overview Page 4

5 OBC Concept -System Architecture- Module Overview PM32: Processor Module TTRS: Telecommand / Telemetry / Reconfiguration / Safeguard Memory Module IOM: Actuator / Sensor Interface Modules MMU: Mass Memory Units (optional) GPS: GPS Receiver Module (optional) CVM: Power Converter Cross Coupling Network (CCN) Pr. Tr. Power tbd UART MTQ Sync SIF TC in Antenna in An/Th Wheels IMU GP in/out HDLC MIL1553 HPC TM out PPS Synch Watchdog HPC Unreg. DC CVM (M) GPS (M) CCN-I/F IOM (M) CCN-I/F PM32 (M) CCN-I/F TM/TC RM/SGM (M) CCN-I/F MMU (M) CCN-I/F Cross Coupling Network Unreg. DC CVM (R) CCN-I/F GPS (R) CCN-I/F IOM (R) CCN-I/F PM32 (R) CCN-I/F TM/TC RM/SGM (R) CCN-I/F MMU (R) PPS Synch Watchdog HPC Antenna in An/Th Wheels IMU GP in/out Pr. Tr. Power tbd UART MTQ Sync HDLC MIL1553 SIF HPC TC in TM out Page 5 OBC Module Overview

6 OBC Concept -System Architecture- Redundancy The arrangement of the box is such, that the main and redundant part of the modules are separated Hot redundant modules are not located next to each other The box separation is optimised regarding number of interfaces between modules (maximum between TTRS and PM32), thermal issues and backplane flex structure maximum of power lines at outer end of the box, maximum of signal lines in inner part of the box ICDU, Part A ICDU, Part B Power Converter Input / Output GPS Receiver Mass Memory Board Telem / Telecmd Reconfig / Safeguard Processor Module Processor Module Telem / Telecmd Reconfig / Safeguard Mass Memory Board GPS Receiver Input / Output Power Converter Page 6 Hot Redundant Module

7 OBC Concept -Mechanic- Overview Modular approach Several modules connected to each other on the front and back sides Left and right side modules carry additional plates to close the box A top plate covers the box internal cross-coupling network Each Module is screwed to the S/C structure to achieve a maximum thermal connection of each module to the structure By this design every module can be treated (almost) as a thermal and mechanical self-standing system with reduced cross-coupling effects. Page 7

8 OBC Concept -Mechanic- Module Frame Page 8 PCB Example (PM32)

9 OBC Concept TerraSAR-X OBC Page 9

10 Processor Module PM32 Page 10

11 PM32 -Functions (1)- Sparc V7 based 32-bit RISC Processor (ERC32/TSC695F) Memory non-volatile start-up PROM non-volatile EEPROM in flight program-able Dual Port RAM (DPRAM) Clocks 40 MHz crystal oscillator appr MHz, 10 MIPS required at least Timer External Watchdog trigger ( alive signal) Input/Output full-duplex HDLC interfaces multiplexed half-duplex HDLC interfaces Reset Page 11

12 PM32 -Functions (2)- Input/Output cont interfaces SpaceWire links PPS Synchronization 1MHz precision clocks MIL-STD-1553B bus Separation ERC32 -UART Power Select signals (out) Timer Test and maintenance Service-interface SIF PM-PM interface Page 12

13 PM32 -PSIE PSIE in Master Mode Timer2 Timer1 UART2 UART1 GPIO SpaceWire RAM interface UART interface JTAG (IEEE ) 2 2 Service Interface internal control & data bus internal Controller Host Interface 32 General purpose I/O Timer / Event Counter 2 2 SpaceWire Interface Service Interface Half-duplex HDLC Full-duplex HDLC Host Interface HDLC half duplex HDLC1 full duplex Dual Port RAM 6K x 8 RAM Interface OBRT generation 2 2 HDLC2 full duplex OBRT 4 Page 13

14 PM32 -Block Diagram Discrete- 128K x 8 2,5M x 40 PROM Memory Osczil. 40 MHz 4M x 8 EEPROM 8K x 32 DPRAM DPRAM Divider MIL Bus 1553B 16K x 16 RAM included SMCS DPRAM (6kBytes) ERC32 SC (TSC695F) PSIE UART WDCLK Result Sep. Reset/Power Buf. PCLK A/B PPS A/B Bus A/B BC/RT Driver LVDS. 6 x 1355 Links Watchdog I/F alive Signal WD- Int. Discrete I/O Select/Sep. Reset FD- HDLC Transformer MPX- HDLC SPW Timer Test I/F PM-PM I/F LVDS SIF Page 14

15 PM32 -Processor Functions- 128K x 8 2,5M x 40 4M x 8 8K x 32 MIL Bus 1553B 16K x 16 RAM included PROM EEPROM DPRAM DPRAM SMCS 32M x 32 DRAM DRAM DPRAM (6Kbytes) PSIE Oscil. 40 MHz Divider ERC32 SC ERC32 SC (TSC695F) (TSC695F) UART int. WDCLK Sep. Result Reset/Power Buf. PRCLK A/B PPS A/B ERC32 SC SPARC V7 RISC µprocessor 5 x User Interrupts 1 x non-mask able Interrupt 2 x UARTs Internal Watchdog EDAC and Parity Timers JTAG BC/RT Driver LVDS. Watchdog I/F Discrete I/O Transformer FD- HDLC MPX- HDLC SPW Timer Test I/F LVDS Bus A/B 4 x 1355 Links alive Signal WD Int. SEL/Sep PM-PM I/F SIF Page 15

16 PM32 -Memory- 128K x 8 2,5M x 40 4M x 8 8K x 32 MIL Bus 1553B 16K x 16 RAM included Transformer Bus A/B BC/RT PROM EEPROM DPRAM Driver 4 x 1355 Links DPRAM SMCS LVDS. Watchdog I/F alive Signal 32M x 32 WD Int. DRAM Discrete I/O 4 x SEL/Sep. DRAM DPRAM (6Kbytes) DPRAM (6Kbytes) FD- HDLC MPX- HDLC PSIE Osczil. 40 MHz Divider ERC32 SC (TSC695F) SPW UART int. WDCLK Timer Sep. Result Reset/Power Buf. Test I/F PM-PM I/F PRCLK A/B PPS A/B SIF LVDS Up to 128K x 8 Startup- PROM Up to 2M x 40 EDAC protected organized in 4 banks; 0 Waitstates 0,5M x 40 EDAC protected as redundant bank 32M x 32 protected DRAM (MCM) Up to 5M x 8 EEPROM organized in 2 separate banks. each bank is powerswitch able separately enable for in flight programming by ground command 8K x 32 DPRAM for datatransfers with the SMCS 6Kbytes PSIE internal DPRAM Page 16

17 PM32 -Clocks- 128K x 8 2,5M x 40 4M x 8 8K x 32 MIL Bus 1553B 16K x 16 RAM included BC/RT PROM EEPROM DPRAM DPRAM SMCS Driver LVDS. Watchdog I/F 32M x 32 DRAM Discrete I/O DRAM DPRAM (6Kbytes) Transformer FD- HDLC MPX- HDLC PSIE PSIE Osczil. Osczil. 40 MHz 40 MHz Divider Divider ERC32 SC (TSC695F) SPW UART int. WDCLK Timer Sep. Result Reset/Power Buf. Test I/F PRCLK A/B PPS A/B LVDS 40MHz oscillator Divider by 10 for using the internal Watchdog (not baseline) Switching logic with select-and status information for determining the clock source (Intern or PCLK-A or PCLK-B) realized in the PSIE 2 PPS Inputs () Bus A/B 4 x 1355 Links alive Signal WD Int. 4 x SEL/Sep. PM-PM I/F SIF Page 17

18 PM32 -Input / Output- 128K x 8 2,5M x 40 4M x 8 8K x 32 PROM EEPROM DPRAM MIL Bus MIL Bus 1553B 1553B 16K x 16 16K x 16 RAM included RAM included Transformer Transformer Bus A/B BC/RT Driver Driver 4 x 1355 Links DPRAM SMCS SMCS LVDS. Watchdog Watchdog I/F I/F alive Signal 32M x 32 WD Int. DRAM Discrete Discrete I/O Out I/O 4 x SEL/ Sep. DRAM DPRAM (6Kbytes) FD- FD- HDLC HDLC MPX- MPX- HDLC HDLC PSIE PSIE Osczil. 40 MHz Divider ERC32 SC (TSC695F) SPW SPW UART int. WDCLK Timer Timer Sep. Result Reset/Power Buf. Buf. Test I/F PM-PM I/F PRCLK A/B PPS A/B SIF LVDS Mil-STD-1553 Controller with isolation transformer in longstub configuration BC/RT/BM feasibility dual redundant buses Internal Communication RAM 6 x 1355 Links with LVDS 2 links hot-redundant Discrete Outputs 4 x Select outputs 3 x Separation inputs Watchdog I/F sends out the alive signal and receives a ext. WD-interrupt 1 x ERC32-UART enabled by the separation result 2 full-duplex HDLC I/F 8 half-duplex-multiplexed HDLC I/F 2 cold-redundant SpaceWire with LVDS 2 Timers (PSIE) Page 18

19 PM32 -Test Interface- 128K x 8 2,5M x 40 4M x 8 8K x 32 MIL Bus 1553B 16K x 16 RAM included Transformer Bus A/B BC/RT PROM EEPROM DPRAM Driver 4 x 1355 Links DPRAM SMCS LVDS. Watchdog I/F alive Signal 32M x 32 WD Int. DRAM Discrete I/O 4 x SEL/Sep. DRAM DPRAM (6Kbytes) FD- HDLC MPX- HDLC PSIE PSIE Osczil. 40 MHz Divider ERC32 SC (TSC695F) SPW UART UART int. WDCLK Timer Sep. Result Reset/Power Buf. Test Test I/F I/F PM-PM I/F PRCLK A/B PPS A/B SIF LVDS PM-PM I/F for interchanging data s between the two PM- Modules. (One Module is on control and the other module is in Testmode) In Testmode all I/F are disabled, except the PM-PM I/F and the MIL-Bus in RTconfiguration SIF (Service Interface) Downloading Debugging Monitoring galvanically isolated (realized in the SIFbox) hot plug-able 1 x ERC32-UART (used for test-software) disabled, when no connector is plugged-in Hardware Debug Page 19

20 PM32 -Pictures (1)- Discrete PM32: Top View LP1/LP2 Page 20

21 PM32 -Pictures (2)- MCM PM32: Top View Page 21

22 PM32 -Pictures (3)- MCM PM32: Bottom View Page 22

23 Telecommand/Telemetry/Reconfiguration/ Safeguard Memory Module TTRS Page 23

24 TTRS: Function Receive telecommands, generate packets to be sent to the PM32 Generate High Priority Commands (HPC) by telecommands or PM32 Telemetry data coming from active/inactive HK memory or PM32 Provision of surveillance and reconfiguration logic Safe Guard Memory Housekeeping Memory Space Craft Elapsed Timer (SCET) Prevention of Single Point Failures (SPF) guaranteed by HW design Page 24

25 TTRS Overview Reconfi HPC/ Reconfi- Relais HPC1/HPC2/ Alarm-I/F Oscilator SCET PSIE HPCn... HPC1 Map Decoder TC FPGA HPC enable Cmd HPC Decryption FPGA Encrypted Cmd Data HPC CMD PTD TC SpaceWire RAM-I/F 8 Data TC-Packet Buffer SGM 128Kx8 TM-Packet Buffer VCA0 FIFO-I/F 8 TM FPGA VCA1 VCM Reed- Solomon TM Latch-up Protection HK Memory 128Mx8+ 32Mx8 EDAC VCA7 Page 25

26 TTRS-EM-Module VCA VCM RS/CV HKM TM-FPGA CM-FPGA PSIE Relay-Storage PTD TC-FPGA Page 26

27 TerraSAR-X FM Module Page 27

28 Input- Output Module IOM Page 28

29 IOM -Overview- Two independent redundant IOMs Provides all interfaces between the OBC internal CCN and the AOCS Data-Handling scientific equipment. The IOM is physically divided into 2 modules Analog Digital Page 29

30 IOM -Function- Following capabilities are implemented: Serial Asynchronous UART Interfaces Synchronization Interface Serial IMU interface (reduced SDLC protocol) Input/output Interface Relay Status Interface Magnetorquer Interface Analogue Input Interface Thermistor and Coarse Earth Sun Sensor Interface Wheel Interface Page 30

31 IOM -PSIE- PSIE in SpaceWire-Remote-Mode SpaceWire FIFO interface ADC interface DAC interface RAM interface UART interface JTAG (IEEE ) General purpose I/O Timer / Event Counter SpaceWire Interface Timer2 internal Controller Timer1 packet bus internal register bus 2+2 UART2 RAM I/F DAC I/F ADC I/F 2+2 UART1 RAM-Data GPIO GPIO RAM-Control DAC-Control ADC-DAC-Data ADC/MUX-Control FIFO I/F FIFO-Control FIFO-Data 6 16 MODE: Remote SpaceWire Page 31

32 IOM-A -Picture- MUX Amplifier Differential Analog Inputs 12bit DAC Main Red MTQ Driver Track&Hold + 12bit ADC Page 32 IOM-A: LP1 and LP2

33 IOM-D -Picture- 128KBytes FPGA PSIE IOM-D: LP1 Page 33

34 Converter Module CVM (Power Converter) Page 34

35 Converter Module CVM The CVM power module consists of 3 independent power converters Each power converter is dedicated to one box module (TTRS, PM32, IOM) 2 Converters (PM32, I/O) can be switched on/off by TTRS- Commands via latch-relays. Relays status signals are generated and is be monitored by the I/O module. The TTRS module Converter is hot redundant, not switchable. Wide input voltage range 18 V to 50 V DC. Operating temperature range - 45 C to + 80 C separation I/F with 2 of 3 voter for TTRS and PM32-Converter Page 35

36 Converter Module CVM Compensation of SEE especially SET effects included in design Control loop stability verified by worst-case analysis and supported by measurement Output & input impedances of different converter stages matched to avoid oscillations (e.g. input filter main converter) Parts de-rating according to ECSS-Q A Page 36

37 FM Module Page 37

38 GPS Receiver Module GPS Rx Page 38

39 GPS Rx -Features- Low cost single board GPS L1 C/A code receiver for space applications Part of a modular spacecraft AOCS or stand-alone usage Acquiring and tracking up to 8 GPS satellites Configurable for LEO, MEO, and GEO Software based signal processing Processes weak signals Dynamic navigation solution provides PVT even with less than four GPS satellites Synchronization to GPS time by a one Hertz Time Mark Pulse Based on Mosaic020 DSP technology with radiation tolerant, hi-rel components Single or fully redundant configuration Next receiver generation will be compatible to Galileo and modernized GPS. Page 39

40 GPS -Heritage- Page 40

41 GPS Rx for TerraSAR-X Test AvNG I/O PM DSP Ext. Conn. GPS PSIE ASIC EEPROM DM RF FE Page 41