Recent Advancements in Spin-Torque Switching for High-Density MRAM

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1 Recent Advancements in Spin-Torque Switching for High-Density MRAM Jon Slaughter Everspin Technologies 7th International Symposium on Advanced Gate Stack Technology, September 30, 2010 Everspin Technologies, Inc September 2010

2 Outline Current status of MRAM products Toggle MRAM and Spin-Torque MRAM in the memory landscape Recent advancements in Spin-Torque MRAM technology Summary and Future Prospects for MRAM Everspin Technologies, Inc September 2010

3 Everspin Introduction Formed as Everspin in June 2008 Previously part of Freescale Semiconductor The leading developer and manufacturer of integrated magnetic products Industry-first MRAM supplier since June 2006 Embedded MRAM systems Integrated magnetic sensors Current MRAM products Parallel interface products ranging from 256k-16Mb Infinite endurance, >20 year data retention, 35 ns read & write speed Serial interface products ranging from 256kb-1Mb 40 MHz SPI interface, No write delay, infinite endurance Everspin Technologies, Inc September 2010

4 Everspin MRAM Advantages Parameter Non-volatile capability Performance Endurance CMOS integration Temperature range, reliability Soft error immunity Environmentally friendly Capability Data retention >20 years Symmetric read/write 35ns Unlimited cycling endurance Easily integrates in manufacturing back-end Compatible with embedded designs No impact on CMOS device performance -40ºC < T < 150ºC operation demonstrated Intrinsic reliability > 20 years lifetime at 125ºC MRAM cell radiation tolerant Soft error rate from alpha radiation too low to measure (<0.1 FIT/Mb) No battery, RoHS compliant, low power Everspin Technologies, Inc September 2010

5 Everspin MRAM Technology MTJ Transistor Simple 1-transistor + 1-MTJ memory cell MTJ inserted between metal layers State of bit detected as change in resistance Unlimited endurance Leverage CMOS semiconductor ecosystem Cross-sectional view Everspin Technologies, Inc September 2010

6 MRAM Storage Concept R LOW Free Layer Tunnel Barrier Fixed Layer R HIGH Parallel = Low Resistance Anti-Parallel = High Resistance 4Mb Measured Resistance Distribution 2500 Low State High State 2000 #bits σ~0.8% MR w/ xstr Bit Resistance [kω] 10 nm NiFe/AlOx/NiFe Everspin Technologies, Inc September 2010

7 Outline Current status of MRAM products Toggle MRAM and Spin-Torque MRAM in the memory landscape Recent advancements in Spin-Torque MRAM technology Summary and Future Prospects for MRAM Everspin Technologies, Inc September 2010

8 Memory Endurance Comparison Enduranc ce (Cycles) 1E15 1E12 1E9 1E6 1E3 1E0 SRAM MRAM DRAM Working Memory Ox vacancy & Joule heating Interface degradation. Unsuitable for Working RAM FeRAM PRAM RRAM Volume Expansion/Interface Degradation Unsuitable for working RAM NOR Code Storage HDD Data Storage 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 1E-2 Write/ Program Cycle Time (s) NAND Non-volatile Volatile Everspin MRAM is the only Working Memory in the market that is Nonvolatile Everspin Technologies, Inc September 2010

9 Memory Capacity Comparison Capa acity (bits) 1T 100G 10G 1G 100M 10M Working Memory DRAM SRAM MRAM Non-volatile Volatile PRAM NOR Code Storage NAND HDD Data Storage 1M RRAM FeRAM 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 1E-2 Write/ Program Cycle Time (s) Current Everspin MRAM products are utilized as a Nonvolatile Working Memory in the market with performance/density similar to volatile SRAM Everspin Technologies, Inc September 2010

10 Memory Capacity Comparison Capa acity (bits) 1T 100G 10G 1G 100M 10M Working Memory DRAM ST-MRA AM SRAM MRAM Non-volatile Volatile PRAM NOR Code Storage NAND HDD Data Storage 1M RRAM FeRAM 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 1E-2 Write/ Program Cycle Time (s) Current Everspin MRAM products are utilized as a Nonvolatile Working Memory in the market with performance/density similar to volatile SRAM Everspin Technologies, Inc September 2010

11 MRAM bit switching Toggle-MRAM in production ST-MRAM in development H-field Free layer Tunnel barrier Fixed layer Bit line write current I DC Digit line write current H-field Isolation transistor Write architecture: cross-point Magnetic field pulses switch free layer Read architecture: 1T-1MTJ 1T-1MTJ architecture read and write Spin torque from polarized tunneling current switches free layer Everspin Technologies, Inc September 2010

12 Toggle Write Operation Low-R State H 1 H 1 + H 2 H 2 High-R State pinned I 2 I 2 pinned I 1 I 1 MTJ I 1 I 2 Advantages: Eliminates disturb - Large operating window Everspin Technologies, Inc September 2010

13 Toggle-Bit Selection No ½-select bit disturb All bits along ½-selected current lines have increased energy barrier during programming Single write line can not switch bits 4Mb, March6N Toggle Map Operating region i bit 0% switching region (no disturbs) i digit Everspin Technologies, Inc September 2010

14 Spin Torque MRAM Use spin momentum from current to change direction of S, m. Free layer Tunnel Barrier Fixed Layer S m S = t Torque Resistanc ce (Ω) Rmax MR Rmin Current (ma) Everspin Technologies, Inc September 2010

15 Outline Current status of MRAM products Toggle MRAM and Spin-Torque MRAM in the memory landscape Recent advancements in Spin-Torque MRAM technology Summary and Future Prospects for MRAM Everspin Technologies, Inc September 2010

16 Distribution Considerations Separation of V switch and V breakdown Tunnel barrier reliability V read V switch V breakdown Separation of V read and V switch Avoid read-disturb errors Log(N) σ s σ r 6*(σ s +σ b ) σ b Separation of distributions important for working memory MB memory 12σ separation 6*(σ s +σ r ) V bd V Separation = sw σ avg Applied Voltage Everspin Technologies, Inc September

17 Separation of switching and breakdown Prob bability Bits switching Breakdown Separation 20σ Large separation provides operating window From 16 kb arrays integrated with CMOS Distributions: σ 4% Nonvolatile: E b /k B T 60 Continue increasing separation for reliability and manufacturing margin Goal is unlimited endurance V (mv) Everspin Technologies, Inc September 2010

18 Scaling ST-MRAM Today: Reduce J c for reliability and smaller transistors Continued scaling: maintain energy barrier and manage distributions Current (ua) Main Challenge: I sw (array) I C (MTJ) I d-sat (transistor) Reduce I sw (J c ) ST-MRAM bits scale favorably to available current from transistor Scaling requires continued improvement in magnetic devices and materials Maintain Energy Barrier Maintain Distributions Technology Node (nm) I c calculated for J c =2MA/cm 2 Everspin Technologies, Inc September 2010

19 Summary MRAM is a highly reliable, high-performance, nonvolatile memory ICs, with unlimited endurance Has the unique characteristics of a working memory while providing non-volatility Current MRAM product densities ranges from 256kb- 16Mb Spin-Torque MRAM technology is advancing rapidly toward manufacturability Enables higher densities and lower power Goal is to gain advantages of spin-torque writing while maintaining MRAM s unique characteristics of nonvolatility and unlimited endurance Everspin Technologies, Inc September 2010