Test and Reliability of Emerging Non-Volatile Memories

Transcription

1 Test and Reliability of Emerging Non-Volatile Memories Elena Ioana Vătăjelu, Lorena Anghel TIMA Laboratory, Grenoble, France

2 Outline Emerging Non-Volatile Memories Defects and Fault Models Test Algorithms and Design-for-Test Reliability Concerns Discussion 1

3 Introduction Traditional Computing Main Memory ALU Registers R L1,L2 Main Storage SRAM DRAM Flash CU 2

4 Introduction SRAM VQB [V] V Q [V] Emerging Memory Technologies Emerging Computing Paradigms DRAM 1,450nm Burj Khalifa 828m 10,000,000 1,000, ,000 Transistors (k) Clock Speed (MHz) Power (W) Perf/Clock (ILP) Transistor count rising 58nm Aspect ratio: m Aspect ratio: 6 10,000 1,000 Clock Speed Flattening ONO Tunnel Oxide Source n+ Flash WL P- Substrate Drain n+ Control Gate Floating Gate BL Power limits Instr./Clock flattening 3

5 Resistive Memory Types Phase Change Memory Resistive RAM Spin-Transfer Torque RAM 4

6 Resistive Memory Types STT device 5

7 Resistive Memory Types Resistive Device Corresponding binary oxide with bi-stable resistive switching Metal used for electrodes 6

8 Resistive Memory Types Resistive Device 7

9 Resistive Memory Types PC Device Crystalline State Amorphous State Electrode Heater Chalcogenide Glass (GeSbTe) Programmable Volume Current (ma) READ PROGRAM SET RESET ON OFF V T Crystalline Amorphous PCM Voltage (V) 8

10 Resistive Memory Array Architecture a) Crossbar Resistive Memory Array Word Lines (WL) b) Resistive Memory Array with 1T1R Bit-Cell Source Lines (SL) Word Lines (WL) Bit Lines (BL) 9

11 Resistive Memory Array Architecture 10

12 Main Characteristics of Resistive Memories 11

13 Ideal case Param2 Extreme variability & Defects Param2 Fail Fail OK Param1 Param1 Environmental conditions & noise Param2 Stress & Aging Param2 Fail Fail Param1 Param1 12

14 Outline Emerging Non-Volatile Memories Defects and Fault Models Test Algorithms and Design-for-Test Reliability Concerns Discussion 13

15 STT-MRAM fabrication and defects a) Fabrication steps: process schematic BL Non-standard Process (b) Lumped resistive open defects to model the physical defects in RRAM/STT-MTRAM cell BL MTJ / ResistiveMTJ Storage Standard Process Df5 via MTJ / MTJ Resistive Storage metal SL Df3 WL Df2 WL Gate Source Df4 Drain Df1 SL Df3 Df5 Df4, Df5 14

16 RRAM fabrication and defects Bottom electrode deposition affects the forming process can result in an open circuit like behavior. Resistive switching material deposition can cause defects such as thick or thin localized spots. Non-standard Process Standard Process SL Source MTJ / Resistive Storage Memristor BL via metal WL Gate Drain Df5 MTJ / Memristor e Storage Df3 Df1 BL Df4 Df2 WL SL Capping layer deposition can lead to large variations in the characteristics of the forming process and in the efficiency of the switching process. Top electrode deposition might induce parameter variations and defects. Pillar etching Improper etching causes wide resistance variations and resistive defects (shunt and contact). 15

17 Fault modeling STT-MRAM RRAM PCRAM SAP, SAAP, TR SA0, SA1, TR SA0, SA1, TR Incomplete Programming Fault Undefined Write Fault Undefined State Fault Program Disturb Fault Slow Write Fault Slow Write Fault Read Recovery Disturb Fault Read Disturb Fault Read Disturb Fault Read Disturb Fault Incorrect Read Fault Retention Fault 16

18 Outline Emerging Non-Volatile Memories Defects and Fault Models Test Algorithms and Design-for-Test Reliability Concerns Discussion 17

19 Test Algorithms Fault Cause Condition IC/Excitation/Detection SA0 (stuck at reset) Over heating /0 0/w1/r1 SA1 (stuck at set) Over heating /1 0/w0/r0 IPF (Incomplete Programming) Contaminants /1m X/w0/r0m PDF (Proximity Disturb) Thermal Coupling xw0; 0/1m/ 0/w0n/r0m RRDF (Read Recovery Disturb) Read Access Timing 1w0r0/0/1m 1/w0r0/r0m RDF (Read Disturb) Localized Heating 0r0/1m/0 0/r0/r0m *m = marginal state *n = neighbour 18

20 Design-for-Test for USF detection Weak Write Operation Short Write Time Low Write Voltage 19

21 Outline Emerging Non-Volatile Memories Defects and Fault Models Test Algorithms and Design-for-Test Reliability Concerns Discussion 20

22 STT-MRAM Reliability Process Variability R MTJ (KΩ) R MTJ (a.u) R H R H R L R L V DC (a.u.) V DC (V) Cell count Number of Occurrences R L R H R MTJ (KΩ) 0 Cell current I HL I LH I R1 I R0 21

23 STT-MRAM Reliability Thermal Instability Néel-Brown model: Néel relaxation time 22

24 STT-MRAM Reliability Time-Dependent Dielectric Breakdown 23

25 STT-MRAM Reliability 24

26 RRAM Reliability Process Variability 25

27 RRAM Reliability Endurance Degradation Over-SET The conductive path generated during the SET operation is larger than nominal à the path rupture difficult in RESET Over-RESET The tunneling gap resulting during the RESET operation is larger than nominal à conductive path formation difficult in SET 26

28 RRAM Reliability 27

29 PCM Reliability Resistance Drift Structural Relaxation (SR) thermally activated process local rearrangement of the atomic structure of the device in amorphous state. 28

30 PCM Reliability 29

31 Outline Emerging Non-Volatile Memories Defects and Fault Models Test Algorithms and Design-for-Test Reliability and Design-for-Reliability Discussion 30

32 Discussions envm Issues Main Trend Main Application PCM Large Write Current Modifying the cell structure Main Memories Device Scaling Data Stability RRAM Variability of Switching Controlling the filament fluctuation Data Storage Material Selection Endurance Cycles STT-MRAM High Current Densities Reduce latency and write power Cache and Main Memory Integration Density 31