CMP annual meeting, January 23 rd, 2014

Transcription

1 J.P.Nozières, G.Prenat, B.Dieny and G.Di Pendina Spintec, UMR-8191, CEA-INAC/CNRS/UJF-Grenoble1/Grenoble-INP, Grenoble, France CMP annual meeting, January 23 rd, 2014

2 ReRAM V wr0 ~-0.9V V wr1 V ~0.9V@5ns read ~0.3V

3 Power consumption is strongly increasing, with a large contribution of leakage Existing Solutions: Technology level (SOI, HiK...) Circuits level (dynamic logic...) System level (Multiple Threshold CMOS, Variable Threshold CMOS, Power Gating, Clock Gating ) Qualities of MTJs in terms of non-volatility, speed, power consumption and cyclability allows to ease these techniques «Normally-off electronics» T. Kawahara, in Design and Test of Computers, Volume 28, Issue 1, 2010

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5 MRAM IS AN ABOVE-IC PROCESS - MTJ used as a variable resistance - Resistance compatible with CMOS (~ kω) - «End-of-back-end» process - No trade-off with logic process -Easy / cheap to embedd - 0 to 3 add-masks - No HV required Magnetic element level CMOS logic level - Low-T BE process (T<350 C)

6 Intrinsically non-volatile High writing/reading speed ( ns) Endurance (>10 13 ) Writing voltage compatible with CMOS Radiation Hard Ferro 1 Insulator Ferro 2 R H TMR = R R R

7 Bit line Word line Transistor ON Transistor OFF Rmin Rmax Normalised Count >25σ Resistance

8 Replacement of DRAM or Cache 3 or 2 by STT MRAM without changing the overall architecture of electronic circuits Strong decrease in static power consumption (suppressed leakage in DRAM, power gating) No more need for DRAM refreshment 2GHz-500ps 3ns 30ns 1ns ALU CPU FF Registers Cache 1 Cache 2 ALU CPU FF Registers Cache 1 Hybrid cache proposed by toshiba for ultra-low power processors 100ns DRAM File Cache MRAM ms HDD SSD HDD SSD

9 Non-volatily can gates (Flip-flop, ALU ) introduction of Non-Volatility in the logic part / memory-in-logic Further decrease in power consumption Increased resilience (roll-back mechanisms ) Ultra-fast on-fly reconfigurability New functionalities 2GHz-500ps ALU CPU FF 1ns 3ns 30ns 100ns Registers Cache 1 Cache 2 DRAM File Cache NV-ALU NV-CPU NV-FF MRAM ms HDD SSD HDD SSD T.Kawahara, IEEE Design and test of computers, 52, Janv/Feb 2011)

10 Two logic differential data (magnetic and electronic parts) Latch/Flip-Flop can operate as a standard CMOS (nominal speed) Possibility to backup the electric content into the magnetic part Restoration of data in a few 100ps (during AZ phase, SRAM acts like a sense amplifier and copies the content of the MTJs in the latch) A set of NV FF has been designed, characterized by simulation and integrated as standard cells in a digital design flow W. C. Black Jr. and B. Das, Journal of Applied Physics, 87(9) :6674, May W. Zhao et al., in International Solide-State and Integrated Circuit Technology, Shanghai, China, N.Sakimura et al., IEEE-CICC, 2008 S. Kang et al., IEEE-NVMW, 2010

11 Circuit whose functionality can be changed keeping the same hardware Composed of elementary logic functions, called LUT (Look Up Tables) programmable by an operating code stored in a configuration memory Radiation hardness in traditional SRAM-based FPGAs : Duplicating circuits (Triple Modular Redundancy, TMR) Refreshing the SRAM content ( scrubbing ) to avoid errors accumulation

12 Configuration memory based on DRAM Local MRAM (intrinsically immune to radiations) acts as a reference to detect/correct errors Periodic refresh of DRAM using MRAM content (scrubbing) Advantages: High density (DRAM) No redundancy Low power (non-volatile, power gating) Shadowed reconfiguration O.Gonçalves thesis Same approach for interconnections : a full tile was designed

13 A 2-inputs LUT manufactured using the hybrid TowerJazz/Crocus- process 130 nm CMOS Magnetic materials in Back End above CMOS Tested on a digital tester at Spintec All possible 2-inputs functions successively programmed in the MRAM and transferred to the DRAM All the combinations of inputs tested and the corresponding output successfully checked

14 MRAM has a unique combined set of qualities, allowing to introduce Non- Volatility at any level of the memory hierarchy Reduce power consumption Improve reliability (endurance, rad-hard, ) Add new functionalities A full Process Design Kit has been developed by CMP and Spintec for the Crocus/TowerJazz 130nm technology, allowing to offer MPW service A silicon demonstrator of a radiation hardened LUT for space applications has been designed and fabricated atcrocus/towerjazz The circuit has been tested and is fully functional, proving the viability of this technology for logic applications