STM32 Seminar STM32F2 High-Performance. COMPEL/STM Seminar

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1 STM32 Seminar STM32F2 High-Performance COMPEL/STM Seminar Nov/Dec 2011

from Flash equivalent to 0-wait state performance Outstanding dynamic power consumption:

2 STM32 F2 Series highlights 1/2 Advanced technology and process from ST: Memory accelerator: ART Accelerator Multi AHB Bus Matrix 90nm process Outstanding results: 150DMIPS at 120MHz Execution from Flash equivalent to 0-wait state performance Outstanding dynamic power consumption: 188uA/MHz, less than 23mA in run mode from flash at 120MHz with peripherals OFF (running CoreMark benchmark). 2

speed 480Mbit/s Camera interface Crypto/hash processor 32-bit

3 STM32 F2 Series highlights 2/2 More Memory Up to 1MB Flash, up to 128kB SRAM New peripherals in the STM32 platform USB OTG High speed 480Mbit/s Camera interface Crypto/hash processor 32-bit random number generator (RNG) 32-bit RTC with calendar 32bit Timers 3

4 STM32 F2 block diagram Cortex M3 with MPU and Trace running at 120 MHz ART Accelerator TM and multi-level AHB Bus Matrix 1.65 to 3.6V Supply 1-MByte Flash, 128-KByte SRAM 4 Kbytes back up SRAM Ethernet, 2xUSB OTG with High Speed support, camera interface Crypto/Hash processor True random number generator Fast ADC 2MSPS 6

5 STM32 F2 Series product lines Notes: 1. HS requires an external PHY connected to ULPI interface 2. Crypto/hash processor on STM32F217x and STM32F215x V for WLCSP64 package only and 1.8 V for all other packages 7

6 STM32 F2 series portfolio 8

7 Real Time performance

8 High-performance enhancements A performance that cannot be outperformed: o ed 150DMIPS at 120MHz The Adaptive Real Time ART Accelerator allows to execute code from flash with a performance equivalent to 0 wait-state at 120MHz, making the STM32 F2 among the fastest Cortex M3 MCU on the market with 150DMIPS at 120MHz! No Cortex M3 microcontroller can offer more performance in the future in terms or DMIPS/MHz. The only possible improvement will come from CPU frequency increase. 10

9 ART Accelerator in detail Prefetch queue and branch cache principlep Stores the first instructions and constants of branch and interrupt events Pushes them to the prefetch queue the next time they occur, with no execution penalty

10 The proof by CoreMark [Iter/Sec] EEMBC Coremark v1.0 score STM32F2xx 100MHz) +8% vs LPC1768 STM32F2xx 120MHz +30% vs LPC PIC32 LPC PIC CortexR4 (52@24MHz) CortexM0 (33.77@24MHz) M16 (11.208@24MHz) PIC24 (74.48@40MHz) ColdFire (62.28@60MHz) Go to to access the scores MHz 12

11 32-bit multi-ahb bus matrix

12 Dual RAM The 128KB of SRAM is made of 2 blocks of SRAM, one 112KB and one 16KB Both can be accessed simultaneously by 2 masters in 0 WS CPU Th 16KB b d b ff DMAs for high speed peripherals like USB-HS, Ethernet, Camera, Ethernett without impacting the CPU USB HS performance The 16KB can be used as a buffer 14

13 Outstanding power efficiency

14 Outstanding gpower efficiency 188 μa/mhz, 22.5 ma at 120 MHz executing from Flash memory. Thannks to: ST s 90 nm process allowing the CPU core to run at only 1.2 V ART Accelerator reducing the number of accesses to Flash Additional contributions to power efficiency: Backup mode: ~3µA with RTC on, ~1uA with 4-Kbyte backed up SRAM, ~4uA with both on Standby mode current (typ)= 2uA (RTC OFF, backup SRAM OFF), 5uA (RTC ON, backup SRAM ON) Separate 1.2VDD input option (on WLCSP and BGA packages) for the core: allows to benefit from external high efficiency switch mode regulator. VDD min down to 1.65 V (on WLCSP package only), 1.8V on other packages 16

15 Superior and innovative peripherals

16 New IP New Peripheral Communication Peripherals USB 2.0 ON-THE-GO HIGH SPEED (OTG HS)

17 Main Features Fully compatible register level) with the full-speed USB OTG peripheral High-speed (480 Mbit/s), full-speed and low speed operation in host mode and High-speed/Full-speed in device mode Three PHY interfacing options Internal full-speed PHY (as for FS peripheral) I2C interface for full-speed di2cphy ULPI bus interface for high-speed PHY DMA support with a dedicated FIFO of 4Kbytes

18 Device mode Features USB DEVICE: Same as Full-speed mode with some extended/new features: Up to 5 IN bulk, interrupt or isochronous endpoints (Vs 3 in FS) Up to 5 OUT bulk, interrupt or isochronous endpoints (Vs 3 in FS) Separate NVIC interrupt vector for EP1_IN Separate NVIC interrupt vector for EP1_OUT USB HOST: Same as Full-speed mode features Up to 12 channels (Vs 8 channels in FS peripheral) High-speed protocol specific features PING protocol SPLIT protocol Multi-transaction

19 ULPI High Speed PHY connection

20 New IP DIGITAL CAMERA INTERFACE (DCMI)

21 DCMI Features The Digital Camera Interface offers: 8-, 10-, 12- or 14-bit parallel interface Continuous or snapshot mode Crop feature Supports the following data formats: 8/10/12/14- bit progressive scan: either monochrome or raw bayer YCbCr 4:2:2 progressive scan RGB 565 progressive video Compressed data: JPEG With a 48MHz PIXCLK and 8-bit parallel input data interface it is possible to receive: up to 15fps uncompressed data stream in SXGA resolution (1280x1024) 1024) with 16-bit per pixel up to 30fps uncompressed data stream in VGA resolution (640x480) with 16-bit per pixel 23

22 DCMI Block Diagram The digital camera interface is a synchronous parallel interface that can receive data flows, It consists s s of: up to 14 data lines DCMI_D[0..13] Pixel clock line DCMI_PIXCLK with a programmable polarity, rising/falling edge. The maximum AHB/PIXCLK ratio =2.5 (PIXCLK=48MHz max) Horizontal synchronization DCMI_HSYNC, indicates the start/end of a line Vertical synchronization DCMI_VSYNC, indicates the start/end of a frame DCMI Interrupt to NVIC DCMI Request to DMA Five interrupts flags, 1 global interrupt line DCMI IT_LINE Indicates the end of line IT_FRAME Indicates the end of frame capture IT_OVR indicates the overrun of data reception IT_VSYNC Indicates the synchronization frame IT_ERR Indicates the detection of an error in the embedded synchronization frame detection AH HB Bus DCMI_D[0..13] DCMI_PIXCLK DCMI_HSYNC DCMI_VSYNC 24

23 DCMI CROP feature The DCMI interface supports two types of capture: The DCMI can select a rectangular window from the received image The start coordinates and size are specified using two 32-bit registers DCMI_CWSTRT and DCMI_CWSIZE. The size of the window is specified in number of pixel clocks (horizontal dimension) and in number of lines (vertical dimension) Horizontal offset count Vertical start line count ount Vertical line co Capture count

(DCMI_DR) and then transferred through a generalpurpose DMA channel.

24 Camera to LCD Data transfer STM32F2xx LCD FSMC DMA C DCMI_D[0..13]Camera DCMI DCMI_PIXCLK DCMI_HSYNC DCMI_VSYNC The data are packed into a 32-bit data register (DCMI_DR) and then transferred through a generalpurpose DMA channel. The DMA can store the transferred data into internal SRAM or into External memory interfaced with the FSMC and then displayed on the LCD. All the transfer is done through the DMA with 0% CPU load.

25 New IP ENCRYPTION MODULES

26 Crypto/Hash Processor and RNG Encryption/Decryption DES/TDES (data encryption standard/triple data encryption standard): ECB (electronic codebook) and CBC (cipher block chaining) chaining algorithms, 64-,128- or 192-bit key AES (advanced encryption standard): ECB, CBC and CTR (counter mode) chaining algorithms, 128, 192 or 256-bit key Universal hash SHA-1 (secure hash h algorithm) MD5 True random number generator (RNG) that t delivers 32- bit random numbers produced by an integrated analog circuit. 28

27 New IP CRYPTOGRAPHIC PROCESSOR (CRYP)

28 CRYP algorithms principle p Sender has the message to be sent the secret key (symmetric) Receiver has the secret key Clear Data Sender Receiver Clear Data Cipher Encrypted Data Encrypted Data DeCipher Clear Data Symmetric key Symmetric key 30

29 CRYP Features (1/2) Suitable for AES, DES and TDES enciphering and deciphering operations Runs at the same frequency as the CPU, up to 120 MHz. DES/TDES Direct implementation of simple DES algorithms (a single key, K1, is used) Supports the ECB and CBC chaining algorithms Supports 64-, 128- and 192-bit keys (including parity) 64-bit initialization vectors (IV) used in the CBC mode 16 HCLK cycles to process one 64-bit block in DES 48 HCLK cycles to process one 64-bit block in TDES 31

30 CRYP Features (2/2) AES Supports the ECB, CBC and CTR chaining algorithms Supports 128-, 192- and 256-bit keys 128-bit initialization vectors (IV) used in the CBC and CTR modes 14, 16 or 18 HCLK cycles (depending on the key size) to transform one 128-bit block in AES Common to DES/TDES and AES IN and OUT FIFO (each with an 8-word depth, a 32-bit width, corresponding to 4 DES blocks or 2 AES blocks) Automatic data flow control with support of direct memory access (DMA) (using 2 channels, one for incoming data the other for processed data) Data swapping logic to support 1-, 8-, 16- or 32-bit data 32

31 CRYP algorithms overview Key sizes AES DES TDES 128, 192 or 256 bits 64 * bits 192 ***, 128 ** or 64 * bits * 8 parity bits Block sizes 128 bits 64 bits 64 bits Time to process one block 14 HCLK cycle for key = 128bits 16 HCLK cycle for key = 192bits 18 HCLK cycle for key = 256bits * 8 parity bits : Keying option 1 ** 16 parity bits: Keying option 2 ***24 parity bits: Keying option 3 16 HCLK cycles 48 HCLK cycles Type block cipher block cipher block cipher Structure First published 1998 Substitution-permutation network Feistel network 1977 (standardized on January 1979) Feistel network 1998 (ANS X9.52) 33

32 CRYP Block Diagram DMA request for incoming data transfer AES ECB CBC CTR DMA request for outgoing data transfer Key: 128-, 192- and 256-bit O put FIF In Data swa apping TDES DES ECB CBC Key: 64-, 128- and 192-bit ECB CBC Key: 64-bit Data swa apping Out tput FIF FO CRYPTO Processor INRIS IFEM IFNF BUSY OFFU OFNE OUTRIS Flags INIM INMIS OUTIM OUTMIS CRYPTO Global interrupt (NVIC) 34

33 CRYP throughput Throughput in MB/s at 120 MHz for the various algorithms and implementations AES-128 AES-192 AES-256 DES TDES HW Theoretical HW Without DMA HW With DMA Pure SW

34 New IP HASH PROCESSOR

35 HASH Function Definition arbitrary block of data Message (data to be encoded) Hash function fixed-size bit string Digest Interesting property of HASH Function: Small change on Message=> big change in Digest not reversible! 37

36 HASH Applications Verifying the integrity of files or messages Compare the HASH before and after transmission Verifying the authenticity of files or messages Signature: Sign the HASH of a message Receiver check signature and the HASH to ensure authenticity ti it One-Way-Encryption Encryption : Password stored as HASH value, not plain text To check password => compare the HASHs 38

37 HASH Main Features Suitable for Integrity check and data authentication applications, compliant with: FIPS PUB (Federal Information Processing Standards Publication 180-2) Secure Hash Standard specifications (SHA-1) IETF RFC 1321 (Internet Engineering Task Force Request For Comments number 1321) specifications (MD5) AHB slave peripheral p Fast computation of SHA-1 and MD5 : 66 HCLK clock cycles in SHA-1 50 HCLK clock cycles in MD bit words (H0, H1, H2, H3 and H4) for output message digest, reload able to continue interrupted message digest computation 39

38 HASH Block Diagram DMA request HASH O put FIF In t 6 x 32bi Data swa apping MD5 SHA-1 Message Digest HMAC H0..H4 15x32bit HASH Processor DINIS BUSY DMAS DCIS Flags DCIM DINIM HASH Global interrupt (NVIC) 40

39 HASH throughput Throughput in MB/s at 120 MHz for SHA-1 and MD5 algorithms with different implementations MD5 SHA1 HW Theoretical HW Without DMA HW With DMA Pure SW

40 Crypto/Hash Performance Summary Throughput at 120 Mhz for the various algorithms and implementations 120 Mhz /s MB/ AES-128 AES-192 AES-256 DES TDES MD5 SHA1 RNG HW Theoretical HW Without DMA HW With DMA Pure SW 42

41 New IP RANDOM NUMBER GENERATOR (RNG)

42 RNG Features 32-bit random numbers, produced by an analog generator (based on a continuous analog noise) Clocked by a dedicated clock (PLL48CLK) 40 periods of the PLL48CLK clock signal between two consecutive random numbers Can be disabled to reduce power-consumption Provide a success ratio of more than 85% to FIPS (Federal Information Processing Standards Publication 140-2) tests for a sequence of bits. 5 Flags 1 flag occurs when Valid random Data is ready 2 Flags to an abnormal sequence occurs on the seed. 2 flags for frequency error (PLL48CLK clock is too low). 1 interrupt To indicate an error (an abnormal sequence error or a frequency error) 44

43 RNG Block Diagram RNG_CLK 32bit random data register RNG LFSR (Linear Feedback Shift register) Error management Clock checker Fault detector Analog Seed Interrupt enable bit IM DRDY SECS SEIS CECS CEIS Flags RNG interrupt to NVIC 45

44 New IP System Peripherals REAL-TIME CLOCK (RTC)

45 RTC Features Calendar with seconds, minutes, hours, week day, date, month, and year. Daylight saving compensation programmable by software A second clock source (50 or 60Hz) can be used to update the calendar. Digital calibration circuit (periodic counter correction) to achieve 5 ppm accuracy 20 backup registers (80 bytes) which are reset when an tamper detection event occurs. Inputs: AFO_CALIB: 512 Hz clock output (with an LSE frequency of khz). AFO_ALARM: Alarm A or Alarm B or wakeup Inputs: AFI_TAMPER: tamper event detection. AFI_TIMESTAMP: timestamp event detection 47

RTC Block Diagram AFI_TAMPER Backup Registers and RTC Tamper Control registers Tamper Flag AFI_TIMESTAMP RTC Reference Clock RTCSEL [1:0] 512 Hz clock output Alarm A TimeStamp Registers TimeStamp

46 RTC Block Diagram AFI_TAMPER Backup Registers and RTC Tamper Control registers Tamper Flag AFI_TIMESTAMP RTC Reference Clock RTCSEL [1:0] 512 Hz clock output Alarm A TimeStamp Registers TimeStamp Flag AFO_CALIB HSE (1 MHz) LSE LSI RTCCLK ss, mm, HH/date Asynchronous = Alarm A Flag 7bit Prescaler Calendar RTC_CR_OSEL[1:0] PREDIV_A [6:0] Calibration Synchronous 13bit Prescaler Day/date/month/year HH:mm:ss (12/24 format) Alarm B = AFO_ALARM Alarm B Flag PREDIV_S [12:0] ss, mm, HH/date Asynchrone 4bit Prescaler Wake-Up WUCKSEL [2:0] 16bit autoreload Timer Periodic wake up Flag 48

47 Improved IPs FURTHER IMPROVMENTS

48 STM32 F2 System Improvement Low voltage: 1.8V to 3.6V VDD, down to 1.65V on one package More flexible remapping of the peripheral p to the pins Up to 140 GPIOS 4KB backup SRAM: can be used as EEPROM Additionnal Clock-Out Capability (MCO2) Independant output for CPU & USB clocks 50

49 More peripherals p improvements Flexible Static Memory Interface for external LCD, SRAM, PSRAM, NOR and NAND Flash, CompactFlash to expand memory space or support an external display: running at up to 60MHz remap capability on I/D code busses to increase execution performance 3 SPIs running at up to 30 Mbit/s, 6 USARTs running at up to 7.5Mbit/s Fast GPIO (60 MHz toggling speed) 51

50 ADC Improvements 3 ADCs : ADC1 (master), ADC2 and ADC3 (slaves). Maximum frequency of the ADC analog clock is 30MHz. 12-bits, 10-bits, 8-bits or 6-bits configurable resolution. ADC conversion rate with 12 bit resolution is up to: 2 M.sample/s in single ADC mode, 3,75 M.sapmle/s in dual interleaved ADC mode, 6 M.sample/s in Triple interleaved ADC mode. Conversion range: 0 to 3.6 V. ADC supply requirement: VDDA = 2.4V to 3.6V at full speed and down to 1.65V at lower speed. Up to 24 external channels. 3 ADC1 internal channels connected to: Temperature sensor, Internal voltage reference : VREFINT (1.2V typ), VBAT for internal battery monitoring. 52

51 Total Conversion Time Total conversion Time = T Sampling + T Conversion Resolution T Conversion 12 bits 12 Cycles 10 bits 10 Cycles 8bits 8 Cycles 6 bits 6 Cycles With Sample time= 3 ADC_ CLK = 30MHz total conversion time is equal to : resolution Total conversion Time 12 bits = 15cycles 0.5 us 2 Msps 10 bits = 13 cycles us 2.30 Msps 8 bits = 11 cycles us 2.72 Msps 6bits = 9 cycles 03us Msps

52 ADC conversion in single mode (12 bit resolution) 1st sample 2nd sample 3td sample Sampling ADC Conversion +2 This channel is sampled each 15 ADC CLK cycles. The sampling speed in this case is equal to: 0 30MHz/15 = 2Msps -2 With 30MHz is the maximum ADC CLK in STM32F2xx product ADC_CLK

53 ADC conversion in Triple Interleaved mode (12 bit resolution) 1st sample ADC Sampling ADC2 2nd sample th sample 5th sample 3 12 Conversion ADC3 3d sample th sample Cycle This channel is sampled each 5 ADC CLK cycles. The sampling speed in this case is equal to: 30MHz/5 = 6Msps -2 With 30MHz is the maximum ADC CLK in STM32F2xx product ADC_CLK 55

54 STM32F2xx Timer features overview Counter resolution Counter type Prescaler factor DMA Capture Compare Channels Complementary output Synchronization Master Config Slave Config Advanced TIM1 and TIM8 16 bit up, down and up/down YES 4 3 YES YES General purpose (1) TIM2 and TIM5 32 bit up, down and up/down YES 4 0 YES YES General purpose TIM3 and TIM4 16 bit up, down and up/down YES 4 0 YES YES Basics TIM6 and TIM7 16 bit up YES 0 0 YES NO 1 Channel (2) TIM and 16 bit up NO 1 0 TIM (2) 2 Channel(2) TIM9 and TIM12 YES(OC signal) 16 bit up NO 2 0 NO YES (1) New 32-Bit Timers (2) These Timers are identical to XXL Timers NO 56

55 Features overview General Purpose Feature 16/32-bit Counter Auto Reload Up, down and centered counting modes 4x 16 High resolution Capture Compare channels ETR Programmable direction of the channel: input/output Output Compare: Toggle, PWM Input Capture PWM Input Capture Synchronization Up to 8 IT/DMA Requests Motor Control Specific Feature OC Signal Management 6 Complementary outputs Dead-time management Repetition Unit Encoder Interface Hall sensor Interface Embedded Safety features Break sources: BKIN pin/ CSS Lockable unit configuration CH1 CH2 CH3 CH4 BKIN Clock ITR 1 ITR 2 ITR 3 ITR 4 Trigger/Clock Controller 16-Bit Prescaler +/- 16/32-Bit Counter Capture Compare Capture Compare Capture Compare Capture Compare Trigger Output Auto Reload REG CH1 CH1N CH2 CH2N CH3 CH3N CH4 57

56 Audio architecture Two PLLs are available for more flexibilty of the system: The main PLL (PLL) clocked by HSI or HSE used to generate the System clock (up to 120MHz), and 48 MHz clock for USB OTG FS, SDIO and RNG. A dedicated PLL (PLLI2S) used to generate an accurate clock to achieve high-quality audio performance on the I2S interface. 2xI2S peripherals with: Less than 0.5% error on sampling frequency Clock input in case an external high h quality audio PLL is needed 58

Clock Scheme I2S PLL OSC32_IN OSC32_OUT 32.

M HSE PLLCLK CSS SYSCLK 120 MHz max AHB Prescaler /1,2 512 /8 SysTick APB1 Prescaler /1,2,4,8,16 If (APB1 pres =1) x1

.14 VCO x N / P / Q PLL48CLK (USB FS, SDIO & RNG) APB2 Prescaler /1,2,4,8,16 If (APB2 pres =1) x1 Else x2 PCLK2 up to

57 Clock Scheme I2S PLL OSC32_IN OSC32_OUT KHz LSE OSc HSE /2, to 31 RTCCLK OSC_OUT OSC_IN LSI RC HSI RC 4-25 MHz HSE Osc ~32KHz 16MHz IWDGCLK TIM5 IC4 HSI / M HSE PLLCLK CSS SYSCLK 120 MHz max AHB Prescaler /1,2 512 /8 SysTick APB1 Prescaler /1,2,4,8,16 If (APB1 pres =1) x1 Else x2 HCLK up to 120MHz PCLK1 up to 30MHz TIMxCLK TIM2..7, VCO x N / P / Q PLL48CLK (USB FS, SDIO & RNG) APB2 Prescaler /1,2,4,8,16 If (APB2 pres =1) x1 Else x2 PCLK2 up to 60MHz TIMxCLK TIM1,8..11 / R PLL VCO / P Ext. Clock SPI2S_CKIN MCO1 /1..5 HSI HSE PLLCLK LSE xn PLLI2S / Q / R PLLI2SCLK I2SCLK MACTXCLK MACRXCLK MACRMIICLK USB HS ULPI clock MCO2 /1..5 SYSCLK HSE PLLCLK PLLI2S / 2, 20 Ethernet PHY USB2.0 PHY 59

58 Flash Read Protection (1/2) The user area in the Flash memory can be protected against read operations from an entrusted code. Level 0: Read protection disabled Activated t by writing 0xAA to the RDP byte register All operations from/to the Flash memory or the backup SRAM are possible in any boot configuration. Level 1: Read protection enabled Activated by writing any other value of 0xAA and 0xCC to the RDP byte register In debug mode, any Flash memory or backup RAM accesses are disabled. Debug is still permitted in system SRAM Level 2: Deviceis locked-up is Activated by writing 0xCC to the RDP option byte register All protections provided by Level 1 are active Debug features (CPU JTAG and single-wire) are disabled User options can no longer be changed. Boundary scan disabled 60

59 Flash Read Protection (2/2) RDP 0xAA and RDP 0xCC Other option(s) modified Level 1 RDP 0xCC RDP 0xAA Wit Write options including RDP=0xAA Write options including RDP = 0xCC Write options including RDP 0xAA and RDP 0xCC Level 2 RDP=0xCC Write options including RDP = 0xCC Level 0 RDP=0xAA RDP = 0xAA Other option(s) modified Option byte write (RDP level increase) includes: Option byte erase and New option byte programming Option byte write (RDP level l decrease) includes: Option byte erase, New option byte programming and Mass Erase Option byte write (RDP level identical) includes : Option byte erase and New option byte programming 61

60 Thank You! 68

Designing with STM32F2x & STM32F4

Designing with STM32F2x & STM32F4 Course Description Designing with STM32F2x & STM32F4 is a 3 days ST official course. The course provides all necessary theoretical and practical know-how for start developing