DisplayPort VIP Output Board Evaluation Board User Guide

Transcription

1 FPGA-EB March 08

2 Contents Acronyms in This Document.... Introduction..... Further Information Functional Description Switches DisplayPort Interface LVDS Translator Clock Interface High-Speed Headers Power Supply User LEDs and Headers Ordering Information... References... Technical Support Assistance... Appendix A. DisplayPort VIP Output Board Schematics... Appendix B. DisplayPort VIP Output Board Bill of Materials... 6 Revision History... 9 Figures Figure.. Top View of DisplayPort VIP Output Board... Figure.. Bottom View of DisplayPort VIP Output Board... 5 Figure. Functional Block Diagram... 6 Figure. Power Supply... 9 Figure A.. Block Diagram... Figure A.. DP Redriver and Connector I/F... Figure A.. Power, Debug LED, Header I/F... 5 Tables Table.. Connector J... 7 Table.. Connector J... 8 Table 5. User LEDs... 0 Table 6.. Reference Part Number Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at FPGA-EB

3 Acronyms in This Document A list of acronyms used in this document. Acronym Definition DP I C LDO LED LVDS mdp VIP DisplayPort Inter-Integrated Circuit Low Dropout Light-emitting Diode Low-Voltage Differential Signaling Mini DisplayPort Video Interface Platform 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB

4 . Introduction This document describes the Lattice Semiconductor DisplayPort VIP Output Board. This board is designed to work with the Lattice Video Interface Platform (VIP) board interconnect system. This user guide includes descriptions of board components, schematics, and bill of materials. Key features of the DisplayPort VIP Output Board include: Integrated Texas Instruments SN75DP0 DisplayPort : Redriver Mini DisplayPort (mdp) connector Two 60-pin Rugged High-Speed Headers Figure. shows the top view of the DisplayPort VIP Output Board and its key components. Figure. shows the bottom view of the board. User LEDs. V Power to mdp Connector (Not populated) User Header SN65MLVD00 System Reset Mini DisplayPort Connector 5 MHz Clock SN75DP0 Figure.. Top View of DisplayPort VIP Output Board 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at FPGA-EB

5 Downstream Connector (J) Downstream Connector (J) Figure.. Bottom View of DisplayPort VIP Output Board.. Further Information The following references provide detailed information on the DisplayPort VIP Output Board: Appendix A. DisplayPort VIP Output Board Schematics Appendix B. DisplayPort VIP Output Board Bill of Materials For more information on boards and kits available for the VIP (Video Interface Platform) system visit For details on the Texas Instruments SN75DP0, visit the Texas Instruments website at 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB

6 . Functional Description The DisplayPort VIP Output board receives up to -lanes of DisplayPort from the upstream processor board through connector J. The DisplayPort Main Link, Control and Aux Channel are sent through the TI DisplayPort re-driver, which regenerates the DisplayPort high-speed digital link to the mini DisplayPort connector. DisplayPort Main Link ( lanes) DisplayPort Main Link ( lanes) J HPD/CAD/Control Aux Channel SN75DP0 U HPD/CAD/Control Aux Channel mdp Connector CN Figure. Functional Block Diagram.. Switches The push button switch, SW, controls the reset signal RESET. Pressing SW provides logic 0 to the SN75DP0 RSTN pin. RESET is connected to GSRN on connecter J, allowing SW to control the reset signal for other connected boards... DisplayPort Interface The mini DisplayPort connector, CN, connects the DisplayPort VIP Output Board to a DisplayPort sink. If PWR Out is required on Pin 0, the user must populate the. V Low Dropout (LDO) regulator, U, and short jumper J... LVDS Translator The SN65MLV00 LVDS Driver/Receiver, U, can be used to translate the LVDS AUX Channel to single ended I/O. This can be used if the upstream processor board is unable to receive LVDS. The single ended I/O are routed to connector J... Clock Interface The 5 MHz LVDS clock, U, can be used as a reference clock for the upstream processor board. This clock is routed to connector J. 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 6 FPGA-EB

7 . High-Speed Headers The two 60-pin high-speed headers, connectors J and J, are used to connect to an upstream host processor board. Table.. Connector J J Connector Pin Signal Name SN75DP0 pin Description GND V CLK5_P 5 MHz LVDS Clock V 5 CLK5_N 5 MHz LVDS Clock 6 V 7 GND 8 V 9 AUX_P AUX_SRCp DisplayPort Auxiliary Data Channel AUX_N AUX_SRCn DisplayPort Auxiliary Data Channel GND GND 9 GND 0 GND 6 GND 8 RESET RSTN Global System Reset 0 HPD_SRC HPD_SRC Hot Plug Detect CAD_SRC CAD_SRC DP Cable Adapter Detect GND 6 TXP0_D0CH0 IN0p DisplayPort Main Link Lane 0 8 TXN0_D0CH0 IN0n DisplayPort Main Link Lane 0 0 GND SCL_CTL SCL_CTL IC Interface to SN75DP0 TXP0_D0CH INp DisplayPort Main Link Lane SDA_CTL SDA_CTL IC Interface to SN75DP0 TXN0_D0CH INn DisplayPort Main Link Lane 6 GND 8 TXP0_DCH0 INp DisplayPort Main Link Lane 50 TXN0_DCH0 INn DisplayPort Main Link Lane 5 GND 5 TXP0_DCH INp DisplayPort Main Link Lane 55 GND 56 TXN0_DCH INn DisplayPort Main Link Lane 58 GND 60 TP 0,, 5, 6, 7, 8,,,,, 5, 7, 9,,, 5, 7, 9, 5, 7, 9, 5, 5, 57, 59 Not Connected 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB

8 Table.. Connector J J Connector Pin Signal Name SN75DP0 pin Description.V.V.V.V 7 AUX_EN Aux Channel Translator Enable 8 LED User LED 9 AUX_OUT Aux Channel single ended Out 0 LED User LED AUX_IN Aux Channel single ended In LED User LED EN EN SN75DP0 Enable LED User LED 0 GND GND 0 SDA_DDC SDA_DDC IC Display Data Channel SCL_DDC SCL_DDC IC Display Data Channel 9 GND 0 GND HEADER User I/O Header J 6 HEADER User I/O Header J 8 HEADER User I/O Header J 50 HEADER User I/O Header J 5 HEADER5 User I/O Header J 5 GND 55 GND 56 GND 57.5V 58.5V 59.5V 60.5V 5, 6, 5, 6, 7, 8, 9,,,, 5, 6, 7, 8, 9,,,, 5, 6, 7, 8,,,, 5, 7, 9, 5, 5 Not Connected 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 8 FPGA-EB

9 . Power Supply Board power is supplied through connectors J and J. Figure. shows the power distribution scheme. To provide power to the mini DisplayPort connector, install a 5.0 V to. V LDO at U and add shunt to jumper J..5 V from J. V from J V from J Status LED D5 Status LED D7 Status LED D6 LDO* U. V, 500 ma J mdp Connector CN * Not Installed Figure. Power Supply 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB

10 5. User LEDs and Headers Four discrete LEDs (light-emitting diodes) are available to the user. These are driven by the upstream processor board through connector J. Table 5. User LEDs Signal LED # Connector J Pin Color LED D 8 Green LED D 0 Green LED D Green LED D Green An 8-pin 00-mil header, J, is available to the user. There are five user connections routed to the upstream connector J. Table 5. User Header Signal Header J Pin Connector J Pin V HEADER HEADER 6 HEADER 8 HEADER 5 50 HEADER5 6 5 RESET 7 GND 8 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 0 FPGA-EB

11 6. Ordering Information Please visit for the latest ordering information. Table 6.. Reference Part Number Description DisplayPort VIP Output Board Ordering Part Number DP-VIP-O-EVN 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB

12 References For more information, refer to Lattice Embedded Vision Development Kit User Guide (FPGA-UG-005) ECP5 VIP Processing Board (FPGA-EB-000) Technical Support Assistance Submit a technical support case through 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at FPGA-EB

13 Appendix A. DisplayPort VIP Output Board Schematics 5 D DisplayPort VIP Output Board D 5V,V,V5 OnBoard LDO C Downstream Connector & (pg&) IC DP AUX I/F X DP Data Control GPIO SN75DP0 (pg) GPIO I/F X DP Data (pg) LED & Header I/F (pg) Mini DP Connector C B (pg) B A Lattice Semiconductor Applications techsupport@latticesemi.com A Title Title & Index 5 Size Project B DisplayPort VIP Output Board Date: Friday, -Nov-6 Sheet Schematic Rev 0. Board Rev A of Figure A.. Block Diagram 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at FPGA-EB

14 5 V_TX V D C R.7k R R R TXP0_D0CH0.7k.7k.7k TXN0_D0CH0 SDA_DDC TXP0_D0CH SDA_DDC {} TXN0_D0CH SCL_DDC SCL_DDC {} TXP0_DCH0 TXN0_DCH0 SDA_CTL TXP0_DCH SCL_CTL TXN0_DCH C8 V AUX_P R8 R7 5E.9K C0 C R R.5K 5E 0uF 0.uF C 00nF C0 00nF C 00nF C 00nF 0.uF C C C6 C5 00nF 00nF 00nF 00nF SDA_DDC SCL_DDC CAD_SRC HPD_SRC U VCC VCC 6 VCC VCC 5 VCC VCC 6 E-PAD(GND) 0 R6 0 R7 0 R8 SDA_DDC SCL_CTL 5 0 R9 SCL_DDC SDA_CTL 0 0 R0 R 8 9 CAD_SRC 0 HPD_SRC 9 AUX_SRCp AUX_SRCn IN0p IN0n INp INn INp INn INp INn NC NC NC NC NC5 NC6 NC7 GND GND GND OUT0p OUT0n OUTp OUTn OUTp OUTn OUTp OUTn 5 RSTn EN 6 CAD_SINK HPD_SINK AUX_SINKp AUX_SINKn ADDR_EQ VDDD_DREG C C C8 C C R9 V_TX 00nF RESET {,} C7 uf R5 EN {} R R R5 R9 C 00nF 00nF 00nF C7 C5 C9 C6 SCL_CTL SDA_CTL CAD_SINK HPD_SINK C 00nF 00nF 00nF 00nF RST_N V R0 R 00K 00K HPD_SINK DP_V CAD_SINK R0 R 00K C9 uf M ML_LANE0P ML_LANE0N ML_LANEP ML_LANEN ML_LANEP ML_LANEN ML_LANEP ML_LANEN AUX_CHP AUX_CHN HPD DPPOWER CONFIG CONFIG GND GND GND GND GND5 GND6 Mini-DP CN D C SN75DP0SS 8 00nF 00nF uf AUX_N C5 0.uF C6 V AUX_EN {} B A CLK5_P CLK5_N AUX_P AUX_N SCL_CTL SDA_CTL J V HPD_SRC CAD_SRC TXP0_D0CH0 TXN0_D0CH0 TXP0_D0CH TXN0_D0CH TXP0_DCH0 TXN0_DCH0 TXP0_DCH TXN0_DCH TP 0.uF U D {} AUX_OUT R {} AUX_IN 5 GND VCC 8 DE RE# A 6 AUX_P B 7 AUX_N SN65MLVD00 RESET {,} V V_TX L 60ohms.A C8 C9 C0 C C 0uF uf 00nF 00nF 00nF V C 00nF V5 0 DNI 0 C 00nF R6 R7 C7 0.uF C5 00nF R8.7k 6 U VDD OUT_P EN NC E-PAD OUT_N 5 GND DSC0CE CLK5_P CLK5_N Lattice Semiconductor Applications techsupport@latticesemi.com B A 5 ERM L-DV-K-TR PLACE DE-CAPS CLOSE TO THEIR POWER PINS Title DP Redriver & Connector I/F Size Project B DisplayPort VIP Output Board Date: Friday, -Nov-6 Sheet Schematic Rev 0. Board Rev A of Figure A.. DP Redriver and Connector I/F 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at FPGA-EB

15 5 D NOTE : PLACE SWITCH IN THE TOP SIDE D V 700mA traces 0uF 0.uF C7 C6 U LT086CM-. Vin Vout GND TAB DNI 0uF C8 REG_V DPV 700mA traces L 60ohms 500mA 0.uF C9 U6 FUSE D8 J Jumper DP_V V EXTERNAL RESET R9 SW.7k SYS_RST RESET C0 RESET {} 0.uF DA-0WS-7 C C V V V V B A {} AUX_EN {} AUX_OUT {} AUX_IN {} EN EXT_V5 EXT_V EXT_V V L6 J R R R R 60ohms.A 0E 0E 0E 0E LED 9 0 LED D D D D LED Green Green Green Green LED LED LED LED 9 0 SDA_DDC {} LED SCL_DDC {} HEADER 5 6 HEADER V V V 7 8 HEADER 9 50 HEADER 5 5 HEADER5 R7 5 5 R R EXT_V5 K E K V5 D5 ERM L-DV-K-TR L8 Green TP 60ohms.A D6 D7 Green Green Q MMBTA R8 0K V5 V HEADER HEADER HEADER HEADER HEADER5 RESET J HEADER Lattice Semiconductor Applications techsupport@latticesemi.com B A Title Power,Debug LED,Header I/F 5 Size Project B DisplayPort VIP Output Board Date: Friday, -Nov-6 Sheet Schematic Rev Board Rev of 0. A Figure A.. Power, Debug LED, Header I/F 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at FPGA-EB

16 Appendix B. DisplayPort VIP Output Board Bill of Materials Item Reference Qty Value Comments Part Number Manufacturer Description CN Mini-DP 90- TE Connectivity MINI DISPLAYPORT REVERSE OFFSET C,C,C,C,C5,C6,C7,C8, C9,C0,C,C,C,C, C5,C nf Wurth CAP CER 0.UF 0V X7R 00 C7,C9,C,C9 uf GRM55R6A05KE5 D Murata CAP CER uf 0V 0% X5R 00 C8,C,C5,C6,C uf GRM55R6A0KA0 D Murata CAP CER 0.UF 0V X5R 00 5 C0,C8 0 uf GRMBR6A06KE9L Murata CAP CER 0UF 0V X5R C,C,C0,C,C,C, C,C nf GRM55R6A0KA0 D Murata CAP CER 0.UF 0V X5R 00 7 C6,C8 0 uf C608X5RE06M080A C TDK Corporation CAP CER 0UF 5V X5R C7,C9 0. uf CL05A0KA5NNNC Samsung CAP CER 0.UF 5V X5R 00 9 C0 0. uf Wurth CAP CER 0.UF 6V X7R 00 0 D,D,D,D,D5,D6,D7 7 Green LTST-C90KGKT LITE-On INC LED SUPER GREEN CLEAR 060 SMD D8 DA-0WS-7 DA-0WS-7 Diodes Incorporated J,J ERM L- DV-K-TR ERM L-DV-K- TR Samtec Inc TVS DIODE.VWM 0VC SOD Conn High Speed Edge Rate Terminal Strip HDR 60 POS 0.5mm Solder ST SMD T/R - J 8 HEADER General purpose 00 Mils header J Jumper General purpose 00 mils x Header 5 L 60 Ω 500 ma MMZ608Y600BTA00 TDK FERRITE BEAD 60 OHM 060 LN 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 6 FPGA-EB

17 Item Reference Qty Value Comments Part Number Manufacturer Description 6 L,L6,L8 60 Ω. A MPZ608Y600BTA00 TDK FERRITE BEAD 60 OHM 060 LN 7 Q MMBTA MMBTA,5 NXP Semiconductor TRANS NPN 0V 0.6A SOT 8 R,R,R,R,R8,R9 6.7 k CRCW060K70FKEA Vishay RES SMD.7K OHM % /0W R5,R6,R7,R8,R9,R0,R, R,R,R5,R9,R7,R9 0 RC060JR-070RL Yageo RES SMD 0.0OHM JUMPER /0W R6 0 DNL RC060JR-070RL Yageo RES SMD 0.0OHM JUMPER /0W 060 R7.9 K ERA-AEB9X Panasonic RES SMD.9KOHM 0.% /6W 00 R8,R 5E ERJ-GEJ50X Panasonic RES SMD 5 OHM 5% /0W 00 R0,R0,R 00 K ERA-AEB0X Panasonic RES SMD 00K OHM 0.% /6W 00 R M ERJ-GEJ05X Panasonic RES SMD M OHM 5% /0W 00 5 R.5 K ERJ-RKF50X Panasonic RES SMD.5K OHM % /0W 00 6 R,R,R,R,R6 5 0E CRCW000RFKED Vishay Dale RES SMD 0 OHM % /6W 00 7 R5 K RC060FR-07KL Yageo RES SMD K OHM % /0W R7 K RMCF00JTK00 Stackpole Electronics Inc RES SMD K OHM 5% /6W 00 9 R8 0 K ERJ-EKF00V Panasonic RES SMD 0K OHM % /0W SW SYS_RST Wurth SWITCH TACTILE SPST-NO 0.05A V TP,TP TEST POINT Molex Test Point 0." U SN75DP0SS SN75DP0SSRGZR Texas Instruments IC DISPLYPRT : REDRIVR 8VQFN U SN65MLVD00 SN65MLVD00AD Texas Instruments IC LVDS LINE DVR/RCVR 8-SOIC 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at FPGA-EB

18 Item Reference Qty Value Comments Part Number Manufacturer Description U DSC0CE DSC0CE Microchip Technology Inc Standard Clock Oscillators -0C - 70C 5 ppm MHz 5 U LT086CM-. DNI LT086CM-.#TRPBF Linear Tech IC REG LDO.V.5A DPAK 6 U6 FUSE 0500.DRT Littelfuse Inc. FUSE BRD MNT A 5VAC/VDC SMD 7 DISPLAYPORT-VIP-OUTPUT BOARD REV PCB 05-PD-6-0XXX PACTRON 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at 8 FPGA-EB

19 Revision History Date Version Change Summary March 08.0 Initial release. 08 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-EB

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