Statistical and Systematic Impacts of Multiplexing Technologies

Transcription

1 Statistical and Systematic Impacts of Multiplexing Technologies Zeesh Ahmed, Adam Anderson, Shawn Henderson, Johannes Hubmayr ANL S4 Meeting 5 March 2018

2 In an fmux readout, bolometers are multiplexed together by placing each in series with capacitor C creating a unique frequency resonance (see Figure 1). The LCRbolo segments a with each other. A sinusoidal voltage bias is tuned to the resonant frequency of each bolo together into a single waveform (referred to as the comb of carriers) and input on a pair of w amplitude modulates each carrier and appears as sidebands in the resulting current. Becau each bolometer occupy a unique frequency band, the signals from each of the bolometers ar single pair of wires. fmux Status The summed bolometer signals are amplified using Superconducting Quantum Interferenc The SQUID is a low-noise, low input-impedance transimpedance amplifier. After the SQUID goes additional stages of amplification and signal processing in the room temperature elec digitized and demodulated down to baseband. MHz AC bias for TESs at unique frequencies selected by comb of LC Inductive-Capacitive Resonators filters ICE Motherboard FPGA Platform McGill s legacy digital fmux readout platform was based on a custom Virtex-4 motherboard first commissioned in FPGA technology has progressed rapidly since then. To reduce cost, increase channel density, and take advantage of newer FPGAs, we have developed and built a new family of readout hardware. This family includes backplane/crate hardware, FPGA motherboards, and daughtercards based on the FPGA Mezzanine Card (FMC) standard. In this section, we provide a brief technical description of the CPU and FPGA subsystems on the new ICE motherboard. Currently deployed for SPT-3G (68x), planned for Polarbear 2 (40x), used on SPT/SPTpol, Polarbear (12x) Existing warm electronics support 128x MUX factor, but only 64x tested LC be Cold electronics could scaled to 128x, circuit f = R&D 1.6 MHz 5 MHz but would require modest in -LC L= 60 μη fabrication ΔC = 0.6 pf min Q ~ 5000 (ESR ~ 0.1 Ω) MUX factor can impact cost,perbut 68 devices v chipdoes Al on Si substrate not directly impact sensitivity/ Fabricated at LBNL+UCB systematics (except indirectly through Comb design & cost) characterization at ANL The CPU subsystem is a stand-alone ARM Cortex-A8 processor, connected to 1 GB DDR3 SDRAM and dual gigabit Ethernet ports. The CPU manages the many small sensors (temperature, voltage) and interfaces (mezzanine power switches, backplane control, various SPI, USB, and I2C buses). It communicates with the FPGA via high-speed SPI, JTAG, and a PCIe link. The CPU boots from a network or from an SD flash card, and manages the FPGA s boot-up and command interactions. The FPGA subsystem centers around a Xilinx Kintex-7 420T FPGA. The FPGA s 28 high-speed serial (GTX) ports are committed to two QSFP ports, one selectable SFP or PCIe port, and a 19-channel backplane interconnect. The bulk of the FPGA s I/O is committed to hosting two high-pin-count (HPC) FPGA Mezzanine Card (FMC) sockets for daughtercards. Like the previous FPGA platform, the ICE motherboard uses only a single clock reference for all of its onboard systems. This clock is typically sourced from a backplane, although it can also be generated on-board or supplied via an SMA connector. Single-sourced clocking is critical to avoid aliased noise from contaminating the analog data. Figure 1. Schematic overview of the 64 channel digital frequency domain multiplexing rea One significant challenge in increasing the number of bolometers multiplexed together is the multiplexing factor increases the dynamic range of the SQUID quickly becomes a limiti sky signal is modulated into the carrier sidebands, the SQUID dynamic range requirements reduced by injecting an inverted copy of the carrier comb with a 180 degree phase shift prior coil (the nuller ). In the legacy version of the digital fmux readout, statically applying the nu ensure that the remaining current into the SQUID coil met the dynamic range requirement. nulling method is no longer sufficient when the multiplexing factor increases to 64. Instead loop referred to as Digital Active Nulling (DAN)8 nulls both the carriers and sidebands for The dynamic range of the synthesizer chain also limits the number of channels that together. A typical bolometer for a ground-based telescope has a saturation power of 15 p a voltage bias of about 3 µvrms for Rbolo = 1, corresponding to a current of 3 µarm dynamic range at the bolometer from the synthesizer chain is derived from the properties of Figure 3. The ICE motherboard, McGill s new FPGA platform. The black heat sink covers the FPGA; the CPU, converter a PHYs current source, paired the requirement thathigh-speed the total noise contrib DDR3 RAM,(DAC), and Ethernet are visible on the right. The with red mezzanines are two FMC-compliant data-acquisition boards Mezzanine Interface The mezzanine board (see Figure 2) interfaces between the ICE FPGA motherboard and SQUID controller board. The mezzanines host the following subsystems: Digital-to-Analog Converters (DACs) for synthesizing carrier and nuller waveforms, Bolometers SQUID 18

3 fmux Performance Excess readout noise has been recent challenge: mitigated in 3G/PB2 with low-inductance SQUIDs (NIST SA13a L~60nH, StarCryo L~10nH) Early on-sky data from 3G shows readout noise pa/rthz vs pa/rthz expected, less than photon noise by factor of ~2 Optimization needed, but 10nH SQUIDs, 0.5Ohm bolometers would require modest R&D and would have much large safety factor than 3G for readout noise All components have >95% fabrication yields, main losses in cryogenic cycling of integrated modules SPT-3G Crosstalk can be tuned to the % level or better by controlling LC and wiring design

4 umux Status Transduce signal from TES into the frequency shift of a microwave resonator. From the readout perspective, the TES array looks very much like an MKID array. Multiplexing factor of 2000x (4-8 GHz) under development, baseline for SO, 64x demonstrated on-sky with MUSTANG2 Similar warm electronics have been demonstrated on sky for MKIDs, umux in lab-testing SLAC warm electronics, similar at FNAL NIST MUX chips

5 umux Performance Lab demonstration of 64x MUX factor with 30 pa/rthz noise, 0.1% crosstalk, 1/f knee at Hz (Dober, et al. 2017) With DC-biased TESs and flux-ramp modulation, readout noise should be very low >95% yield on 512x MUX devices Fig. 3 Dober et al. (2017) Lab demonstration of 512x MUX using prototype SLAC electronics, but still in testing and characterizing noise performance Yield and integration issues for large arrays not yet known, but fewer interconnects usually better, 2000x base-lined for SO Frequency survey of 512 readout channels with 95% yield. Dips are not noise/interference!

6 Pros Measured on-sky noise performance at 64x, straightforward to extend to 128x, will be demonstrated on 3G and PB2 Lab demonstrations of crosstalk ~ 0.1% SQUIDs and LC chips fabricated with very high yield fmux Cons Temperature, low-frequency stability to be demonstrated on sky with 64x (LC and warm electronics) Stability requirement on bolometer resistance leaves little margin on readout noise Designing wiring for control of parasitics is hard Lab-demo noise is acceptable (white + 1/f) umux Significant R&D (warm and cold electronics) required for MUX factors > 128x Warm electronics not tested on-sky Lab-demo crosstalk is <0.1% More margin on readout noise Prototype warm electronics exist, currently being refined May have SO as prototype for S4 System architecture less mature, still indevelopment Unknown unknowns DC bias cannot be optimized for individual bolometers; puts a stricter constraints on fab tolerance tmux? Heritage, experience, well-understood performance Aliased noise can be non-negligible Wiring and integration complexity, may impact yield