MIL-PRF SUMMARY OF CHANGES FOR DRAFT REVISION L 01 February, 2019

Transcription

1 The following table summarizes changes to MIL-PRF Revision K that are currently being proposed for MIL-PRF Revision L. 1 TOC Paragraph 4. Correct spelling from VERIFICAITON to VERIFICATION Editorial iii 2 TOC Paragraph Correct spelling from DEVCIE to DEVICE Editorial viii C.5 3 TOC Paragraph Correct spelling from PROCEFURES to PROCEDURES Editorial xv F , 2.2.2, A.2.2.1, C.2.2.1, D.2.2.1, E.2.2.1, F.2.2.1, G Update From: (Copies of these documents are available online at To: (Copies of these documents are available online at The url has changed from to 2, 22, 35, 94, 1, 151, 5 TABLE I Correct Row 3 Column 3 from: Required I accordance with the applicable device To: Required in accordance with the applicable device Update from: Inspection lot formation. Inspection lot formation is required if the inspection lot is to be formally accepted by the lot related CI and PI testing of this specification or method 5005 of MIL-STD-883. If the in-line process verification testing alternative is used, inspection lot formation is not required. To: Inspection lot formation. Inspection lot formation is required if the inspection lot is to be formally accepted by the lot related CI and PI testing of this specification (option 2 end-of-line inspection) or method 5005 of MIL-STD-883. If in-line process verification testing (option 1 in-line inspection) is used, inspection lot formation is not required. 154 Editorial 5 To clarify when to apply Option 1 in-line inspection vs Option 2 end-of-line inspection C Add MIL-STD Design, Manufacturing and Quality Standards for Custom Electromagnetic Devices for Space Applications. under Department of Defense Standards section. 8 C.2.3 Add JESD213 Standard Test Method Utilizing X-RAY Fluorescence (XRF for Analyzing Component Finishes and Solder Alloys to Determine Tin (Sn) Lead (Pb) Content. under JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) section. MIL-STD-981 is referenced throughout the Element Evaluation tables. JESD213 is referenced throughout the Element Evaluation tables

2 9 Table C-I Update table element from: Microcircuit and semiconductor dice, Table C-II to Microcircuit dice, Table C-II and add new table element Semiconductor dice, Table C-II-1 Editorial update to summary TABLE C-I. Element evaluation summary. To include all new Element evaluation tables Remove element Passive elements, Table C-III proposed by JC-13.5 TG 158. Insert the following new table elements: - Wire Bondable and Surface Mount Resistors, Table C-III - Chip Capacitors, Ceramic, Table C-III-1 - Chip Capacitors, Solid Tantalum, Table C-III-2 - Capacitors, MOS NMOS, Table C-III-3 - Coils, transformers, Table C-III-4 10 C.3.3 Update From: in accordance with table C-II and C through C To:...in accordance with tables C-II, C-II-1 and C through C C Update from: in accordance with table C-II, subgroups 3 through 6 To: in accordance with tables C-II and C-II-1, subgroups 3 through 6 12 C Update from, C Test sample preparation. Test samples may be assembled such that similar assembly methods and conditions the element will see during normal production assembly will be simulated. Electrical probe testing may be performed in lieu of assembly. To, C Test sample preparation. All test samples being assembled by the hybrid manufacturer shall use the same methods and conditions used during normal production of the device. If the test samples are not being prepared by the hybrid manufacturer, then they shall be prepared using similar assembly methods and conditions that simulate actual production of the device. Electrical probe testing may be performed in lieu of assembly. Table C-II was split into two Table C-II and C-II-1 Table C-II was split into two Table C-II and C-II-1 Clarification. The intent is to have elements assembled in the test samples with the same methods that will be used during normal production. 38 2

3 13 Appendix C Section C.3.3 Remove Table C II Microcircuit and semiconductor dice evaluation requirements. along with footnotes 1/ MIL-STD-750 methods. 2/ For Class K sample sizes, see C JC-13.5 TG 158 Insertion of Element Evaluation tables Insert tables TABLE C-II. Microcircuit dice evaluation requirements. with footnotes 1/, 2/, 3/, 4/, 5/ TABLE C-II-1. Semiconductor dice evaluation requirements. with footnotes 1/, 2/, 3/, 4/, 5/, 6/, 7/ 14 C.3.4 Update from: in accordance with table C-III and C through C To: in accordance with tables C-III, C-III-1, C-III-2, C-III-3 C- III-4, and C through C C Update from: Test sample preparation for subgroups 3 and 4. To: Test sample preparation for subgroups 3 through Appendix C Section C.3.4 Replace/remove TABLE C-III. Passive element evaluation requirements. JC-13.5 TG 158 Table C-III was split into five Table C-III, C-III-1, C-III-2, C-III- 3, and C-III-4 Tables C-III-1 and C-III-2 define additional Test sample preparations of subgroups 5, 6, and 7. Insertion of Element Evaluation tables Insert the following tables: TABLE C-III. Wire Bondable and Surface Mount Resistors. with footnotes 1/, 2/, 3/, 4/, 5/ TABLE C-III-1. Chip Capacitors, Ceramic. with footnotes 1/, 2/, 3/, 4/, 5/, 6/, 7/, 8/, 9/, 10/, 11/ TABLE C-III-2. Chip Capacitors, Solid Tantalum. with footnotes 1/, 2/, 3/, 4/ TABLE C-III-3. Capacitors, MOS NMOS. with footnotes 1/, 2/ TABLE C-III-4. Coils, transformers. with footnotes 1/, 2/ 17 Table C-VII-1 Correct typo in te 2 of Table C-VII-1. Change reference paragraph from: C to: C Correction to typo and update hyperlink from table of contents to Table C-VII

4 18 C Update from, C Inspection lot formation. Inspection lot formation is required if the inspection lot is to be formally accepted by the lot related CI and PI testing of this specification or method 5005 of MIL-STD-883. If the in-line process verification testing alternative is used, inspection lot formation is not required. To, C Inspection lot formation. Inspection lot formation is required if the inspection lot is to be formally accepted by the lot related CI and PI testing of this specification (option 2 end-of-line inspection) or method 5005 of MIL-STD-883. If in-line process verification testing (option 1 in-line inspection) is used, inspection lot formation is not required. To clarify when to apply Option 1 in-line inspection vs Option 2 end-of-line inspection C Update paragraph C with proposed wording from JEDEC TG. (See initial draft) 20 C Update C a. From Group C sample selection: Samples for group C will be drawn from the first inspection lot submitted To: Group C sample selection: Samples for group C will be drawn from the first inspection lot submitted and periodically per the requirements of section C herein for Class K processes and products. 21 C Insert the following wording into C ( present in the device. Each 15 piece sample of wires will contain an even distribution of all wire sizes that can be qualified by that sample. ) And ( required wire sample size, except for periodic requalification of Class K processes and products per the requirements of section C herein which shall only test two devices regardless of quantity of wirebonds contained in the devices. ) 22 C Insert the following wording into C (.element sample size, except for periodic requalification of Class K processes and products per the requirements of section C herein which shall only test two devices regardless of quantity of elements contained in the devices. ) Changes to periodicity for Group C QML for class K devices. Update to reflect changes in periodicity of group C QML for class K devices. Update to clarify changes to wire bond strength testing for QML qualification. Update to clarify changes to element shear testing for QML qualification

5 23 D.2.3 Update From: (Copies of this document are available online at To: (Copies of these documents are available online at The url has changed from to D Remove e. Printed wiring boards: MIL-PRF Printed Wiring Board, Rigid Multilayered Thermosetting Resin Base Material, with or without Blind and Buried Plated-Through Holes, for Soldered Part Mounting. 25 TABLE D-XVI Correct 2 places in TABLE DVI, Steady state temperature humidity bias life test (85/85) Method reference JESD22-A101 from 49.1 psia to kpa 26 G Correct lettering of sub sections paragraphs to include h 27 TABLE G-V Update the following: Subgroup 2, column 1. Replace G with G Subgroup 2, column 2. Replace G with NA Subgroup 3 column 1. Replace G with G Voltage conditioning and aging are not applicable to printed wiring boards Typo correction to match information as listed in JESD22- A101 Editorial correction. Subsections 156- originally missing h item. 157 Editorial