The GBT-based Expandable Front-End (GEFE)

Transcription

1 The GBT-based Expandable Front-End (GEFE) Manoel Barros Marin (on behalf of the GEFE team) Beam Instrumentation Technical Board (03/12/2015)

2 The GBT-based Expandable Front-End (GEFE) Outline: Introduction First contact with the GEFE board Radiation campaign at PSI Status & Outlook

3 The GBT-based Expandable Front-End (GEFE) Introduction

4 Introduction What is the GBT-based Expandable Front-End (GEFE) General purpose FPGA-based radiation tolerant board Target Total Ionizing Dose (TID): up to 75 krad Rad-Hard FPGA ProAsic3 (ACLA3PE3000-FGG896) from Microsemi Features different components of the GBT-Versatile Link ecosystem from CERN PH-ESE Optical & Electrical interfaces Upgradable: FPGA Mezzanine Card (FMC) High-Pin Count (HPC) connector 2x GPIO connectors (24 & 13 user I/Os) Flexible schemes for: Clocks Resets FPGA programming Slow Control (SC) E-link Power Back-End System Timing/Trigger/Ctrl (TTC/BST) Data Acquisition (DAQ) Radiation Front-End Cards 4

5 The GBT-based Expandable Front-End (GEFE) First contact with the GEFE board

6 The GEFE at a glance First contact with the GEFE board (1 of 7] 200 mm 100 mm Block diagram 6

7 First contact with the GEFE board (2 of 7) Main components VTRx Rad-Hard Powering FMC HPC GBTx ProAsic3 FPGA Block diagram 7

8 First contact with the GEFE board (3 of 7) Secondary components RX TX Low-Speed Electrical Link GPIO Connectors A & B Block diagram 8

9 First contact with the GEFE board (4 of 7) Auxiliary components GPIO Lemo Board ID Connector JTAG LEDs (x6) DIP Switch & Push Button GPIO/CLK MMCX GEFE Config. ID Resistors Block diagram 9

10 Test setup First contact with the GEFE board (5 of 7) Back-End board (GLIB) Patt. Check. FPGA Patt. Gen. GBT-FPGA VTRx GBTx On-board Connectors FPGA FMC HPC 10

11 FPGA Firmware First contact with the GEFE board (6 of 7) GEFE RX ProAsic3 FPGA VTRx System Core Top User Logic HDL (Verilog) example GBTx Test Routines FMC HPC TX GPIO Connectors A & B 11

12 First test results Form factor: First contact with the GEFE board (7 of 7) PCB too thick for being inserted in crate (2.2 mm instead of 1.8 mm) (to be corrected in v2) Main components: Rad-Hard Powering (1.5, 2.5 and 3.3 V) presents very low ripple (< 10 ICs pins) High-Speed Optical Link (VTRx Gbps fully operational GBtx from/to ProAsic3 communication (E-Links) operational with comments: o Downstream E-Links (GBtx-to-ProAsic3) fully operational o Upstream E-Links (ProAsic3-to-GBTx) operational but high GBTx temperature (~70 C) Missing resistor network for ProAsic3 LVDS drivers (GBTx receives 2.5 V of common signal instead of 1.2 V) FMC HPC user I/O and DP lines successfully 160 Mbps using CMOS 2.5 V levels (Resistor network for ProAsic3 LVDS driver not presented on GEFE (shall be featured on FMC)) Secondary components: Low-Speed Electrical Link not tested yet GPIO Connectors successfully 160 Mbps Auxiliary components (e.g. LEDs, Crystal Oscillator, etc.) successfully tested Some special functions (e.g. FMC JTAG, FMC I2C, etc.) not tested yet 12

13 The GBT-based Expandable Front-End (GEFE) Radiation campaign at PSI

14 The radiation campaign Collaboration between CERN BE-BI & RadWG Radiation campaign at PSI Carried out in October 2016 at the Paul Scherrer Institut (PSI) In beamline of COMET cyclotron: Proton beam 250 MeV Radiation levels: Total Ionizing Dose (TID) = 75 krad Fluence = 9.31*10^11 p/cm 2 Active components tested for the GEFE project: Dual-bit transceiver (SN74LVC2T45DCTT) (test passed) Dual diode (BA99) (test passed) Crystal oscillator (25 MHz) (SPXO018077) (test passed) COMET cyclotron (1 of 2) 14

15 Radiation campaign at PSI Radiation tolerance of GEFE s active components (2 of 2) Qualified up to 75 krad Qualified bellow 75 krad Not Qualified 15

16 The GBT-based Expandable Front-End (GEFE) Status & Outlook

17 Status Status & Outlook (1 of 2) The GEFE board GEFE v1 almost fully tested (Main features operational) Low-Speed Electrical Link and some special functions to be tested Minor modifications required for pre-production prototype (GEFE v2) Radiation hardness qualification required for two active components & full GEFE board The GEFE community Specification in version (may be used as User Guide) Open HardWare Repository (OHWR) Wiki and Lists (OHWR & CERN e-group) Projects in the GEFE community: - New Multi-Orbit POsition System SPS (MOPOS SPS) (): Requested 300 pieces - Motor Controller Optical Interface (MCOI) (BE-BI-PM): Requested 25 pieces - Advanced Wakefield Experiment BPM (AWAKE BPM) (): Interested - CLIC Acquisition and Control Module (CLIC-ACM) (BE-CO): Interested - Rad-tol high-bandwidth fieldbus devkit (BE-CO): Interested - Function Generator Controller Lite (FGClite) (TE-EPC): Interested - Beam Wire Scanners (BE-BI-BL): Interested - CHARM test board (EN-STI): Interested - Beam Gas Ionization (BGI) monitors (BE-BI-BL): Interested 17

18 Outlook Status & Outlook (2 of 2) The GEFE board Update of schematics & PCB layout for pre-production prototype (GEFE v2) (January 2016) - Addition of on-board GBTx-SCA ASIC for remote FPGA programming??? Radiation hardness qualification of: - NMOS transistor (BST82) to be qualified up to 75 krad (December 2015) - LVDS receiver (SN65LVDS2DBVR) & full GEFE board (First half of 2016) Ph.D. Student (Christophe Donat Godichal) in charge of the radiation tests Pre-productionstage (First half of 2016) Design and implementation of a fully automated test bench for production testing (First half of 2016) Production stage (Second half of 2016) The GEFE community Discuss whether to assembly the two GEFE v1 PCBs available Organise periodical meetings Update specifications after testing the first GEFE v1 prototypes Update Open HardWare Repository (OHWR) Wiki Receive small orders of pre-production GEFE v2 for prototyping (First half of 2016) Organise production of GEFE for the different projects (Second half 2016) 18

19 The GEFE team Andrea Boccardi Christophe Donat Godichal Jose Luis Gonzalez Thibaut Lefevre Tom Levens Balint Szuk Manoel Barros Marin Acknowledgements Acknowledgements Paschalis Vichoudis, Pedro Leitao & other colleagues from my old group PH-ESE Juan Boix Gargallo, Thierry Bogey and the rest of my section () Tullio Grassi (PH-UCM) Slawosz Uznanski & other colleagues from TE-EPC Felix Andreas Arnold, Stephane Burger & other colleagues from BE-BI-PM Javier Serrano, Erik Van Der Bij, Evangelia Gousiou & other colleagues from BE-CO Bartosz Przemyslaw Bielawski & other colleagues from BE-RF Markus Brugger, Salvatore Danzeca, Georgios Tsiligiannis, Raffaello Secondo & other colleagues from RadWG Special thanks to Fernando Carrio Argos (PH-UAT) for his simulations of GEFE s Power Distribution Network

20 Thank you

21 References The GEFE project web page: The VFC-HD project web page: The GBT project web page: The GBTx ASIC manual: gbtxmanual.pdf The VTRx application note: Application Note V2.4.pdf FEASTMP project web page: ST LHC4913 data sheet: ANSI/VITA specifications web page: Microsemi web page: Microsemi ProAsic3E FPGA Fabric user s guide: PA3E_UG.pdf Microsemi ProAsic3E Flash Family FPGAs datasheet: PA3E_DS_v14.pdf Microsemi application note AC380: LPF_AC380_AN.pdf 21

22 GEFE board Detailed Block Diagram GEFE Osc. (25MHz) Push Button Board ID Connector (13-bit) MMCX GPIO (x4) Prog. clocks (x1) GEFE Config. ID Resistors (10-bit) GPIO Connector B (24 user pins) GPIO Connector A (13 user pins) SMA ESLT SMA RSSI I2C Connector VTRx MMCX (LVDS) SecRefClk I2C Reset GBTx Prog. clocks (x4) E-links clocks (x3) E-links (40 Bidirectional) SCA E-link Core FPGA (ProAsic3) IOs IOs (La/Ha) (Hb) Std. IOs Std. IOs FMC DP (40 pins) JTAG FMC HPC (160 pins) GBT M2C clocks (x2) M2C clocks (x2) BIDIR clocks (x2) FMC HPC LEDs VTRx Power SFP+ Power GPIO SW (8-bit) MMXC (LVDS) GPIO/Clk IO VioB M2c Vadj Main Power Connector FEASTMP 1.5V FEASTMP 2.5V LDO Regulator 3.3V V12p0 Power Connector V12p0 V3p3 & V3p3Aux

23 GEFE board VTRx & GBTx Main components of the new Rad-Hard Optical Link for Experiments Widely used at CERN (Experiments & Accelerators) and External institutions (Desy, etc.) Developed at CERN by PH-ESE VTRx Rad-Hard Optical Transceiver Bidirectional Link at 4.8 Gbps (Versatile Link) GBTx Rad-Hard ASIC Single Electrical Link with VTRx at 4.8 Gbps Multiple Electrical Links with Front-End Electronics (E-Links) Mbps Mbps Mbps One dedicated E-Link for slow control 80 Mbps 17 mm VTRx GBTx ASIC 17 mm

24 GEFE board GBTx-SCA ASIC

25 GEFE board Particularities of the FMC connector in GEFE High-pin count (HPC) socket Single width conduction cooled FMC Module Accessible from the rear of the board The different control signals of the FMC standard are supported The targeted user-specific I/O data rate is up to 700 Mbps Up to 160 Single-Ended (or 80 Bidirectional) user-specific I/Os 6 differential clock lines (4 inputs and 2 bidirectional) The high-speed lanes (DP) connected to user-specific I/Os Resistor network required on FMC when driving LVDS signals from ProAsic3 FPGA Special functions of DP lanes: Direct SC e-link between GBTx and the FMC HPC connector FPGA programming by JTAG master (e.g. SCA) placed on FMC Direct signals from GPIO connector A to FMC HPC connector Bpm Digital front-end Fmc (BDF)

26 GEFE board FPGA (ProAsic3) 26

27 GEFE board Powering FEASTMP 27

28 GEFE board Slow Control (SC) E-Link Single 80 Mbps GEFE FmcDpM2c_p/n[5:7] VTRx GBTx GbtxElinkScXx_p/n Resistors Network FmcDpM2c_p/n_Fpga[5:7] GbtxElinkScXx_p/n_Fpga FPGA (ProAsic3) FMC HPC 28

29 GEFE board Low-Speed Electrical Link Tested up to 10 Mbps over 2 Km of coper cable GEFE SMA SMA Low-Speed Electrical Link FPGA (ProAsic3) 29

30 GEFE board Clocking Scheme (1 of 2) GEFE Osc. 25MHz MMCX GPIO (x4) La_cc[00,01,17,18] VTRx CDR GBTx Osc. 40MHz CLOCKDES[0:3] DCLK[0:2] FPGA (ProAsic3) Ha_cc[00,01,17,18] Hb_cc[00,06,17] GBTCLK_M2C[0:1] FMC HPC MMCX (LVDS) REFCLK SCCLK CLK_M2C[0:1] CLK_BIDIR[2:3] CLOCKDES[4] MMXC (LVDS) GPIO/Clk IO FmcDpM2c[5] FmcDpC2m[8] 30

31 GEFE board Clocking Scheme DCLK[0] MmcxGpio[7] MmcxGpio[0] MmcxGpio[6] CLOCKDES[0] MmcxGpio[5] (2 of 2) La_cc[18] CLK_BIDIR[3] La_cc[0] La_cc[17] CLK_M2C[1] Ha_cc[17] DCLK[1] CLOCKDES[1] La_cc[1] CLK_BIDIR[2] SCCLK ClkFeedback ClkM2c[0] GBTCLK_M2C[0] MmcxClkIo CLOCKDES[2] Ha_cc[18] Osc25MHz DCLK[2] MmcxGpio[3] CLOCKDES[3] MmcxGpio[2] MmcxGpio[4] MmcxGpio[1] Clock Source A Clock Source B Clock Source C Ha_cc[0] Hb_cc[0] Ha_cc[1] Hb_cc[6] GBTCLK_M2C[1] Hb_cc[17] 31

32 GEFE board Resets Scheme GEFE GPIO Connector B (24 user pins) GPIO Connector A (13 user pins) Reset VTRx RSSI POR/PPR GBTx Reset Button Reset Logic FPGA (ProAsic3) FMC HPC 32

33 GEFE board FPGA Programming Scheme GEFE Std. IOs JTAG Prog. FPGA (ProAsic3) FmcDpM2c_p_r_Fpga[0:4] ConnXxx FpgaXxx FmcDpM2c_p[0:4]_Xxx Jumpers JTAG Connector Voltage Translator (Vadj from/to V3p3) Jumpers FmcDpM2c_p_r[0:4] FMC HPC 33

34 Application Examples (1 of 2) Multi-Orbit POsition System SPS (MOPOS SPS) () STANDARD BACK-END (VFC-HD) FPGA USER LOGIC GBT-FPGA GEFE VTRx GBTx FPGA F BPM M DIGITAL FE C FMC BPM ANALOG FE BPM Motor Controller with Optical Interface (MCOI) (BE-BI-PM) STANDARD BACK-END (VFC-HD) FPGA USER LOGIC GBT-FPGA VERSA EUROPE 3U GEFE GEFE VTRx GBTx FPGA F M C PM DIGITAL FE FMC BACKPLANE MOTOR 34

35 Application Examples (1 of 2) Multi-Orbit POsition System SPS (MOPOS SPS) () STANDARD BACK-END (VFC-HD) FPGA USER LOGIC GBT-FPGA GEFE VTRx GBTx FPGA F BPM M DIGITAL FE C FMC BPM ANALOG FE BPM BPM Digital Front-End FMC (BDF) Motor Controller with Optical Interface (MCOI) (BE-BI-PM) STANDARD BACK-END (VFC-HD) FPGA USER LOGIC GBT-FPGA VERSA EUROPE 3U GEFE GEFE VTRx GBTx FPGA F M C PM DIGITAL FE FMC BACKPLANE MOTOR 35

36 Application Examples (1 of 2) Multi-Orbit POsition System SPS (MOPOS SPS) () STANDARD BACK-END (VFC-HD) FPGA USER LOGIC GBT-FPGA GEFE VTRx GBTx FPGA F BPM M DIGITAL FE C FMC BPM ANALOG FE BPM BPM Digital Front-End FMC (BDF) Motor Controller with Optical Interface (MCOI) (BE-BI-PM) Motor Driver Interface (MDI) board STANDARD BACK-END (VFC-HD) FPGA USER LOGIC GBT-FPGA VERSA EUROPE 3U GEFE GEFE VTRx GBTx FPGA F M C PM DIGITAL FE FMC BACKPLANE MOTOR 36

37 Application Examples New rad-tol high-bandwidth fieldbus devkit (BE-CO) STANDARD BACK-END (VFC-HD) FPGA USER LOGIC GBT-FPGA GEFE VTRx GBTx FPGA F M C WorldFIP DIGITAL FE FMC (2 of 2) WorldFIP FE WorldFIP FE WorldFIP FE Advanced Wakefield Experiment BPM (AWAKE BPM) () WorldFIP FE STANDARD BACK-END (VFC-HD) FPGA SMA SMA GEFE Low-Speed Electrical Link USER LOGIC VTRx GBTx FPGA F DIGITAL FE M FMC C BPM ANALOG FE BPM 37