SP605 GTP IBERT Design Creation
|
|
|
- Avis Robbins
- 5 years ago
- Views:
Transcription
1 SP605 GTP IBERT Design Creation January 2010 Copyright 2009, 2010 Xilinx XTP066
2 Note: This Presentation applies to the SP605 SP605 IBERT Overview Xilinx SP605 Board Software Requirements Setup for the SP605 IBERT Designs Running the SP605 IBERT Design SP605 IBERT Design Creation Create IBERT CORE Generator Project Create IBERT Design Create IBERT ACE File References
3 SP605 IBERT Overview Description The LogiCORE Integrated Bit Error Ratio (IBERT) core is used to create a pattern generation and verification design to exercise the Spartan-6 GTP transceivers. A graphical user interface is provided through the IBERT console window of the ChipScope Pro Analyzer Reference Design IP LogiCORE IBERT Example Designs PCIe (1), SMA (1), SFP (1), FMC_LPC (1) ChipScope Pro Analyzer ChipScope Pro 11.4 Software and Cores User Guide (UG029)
4 Xilinx SP605 Board Note: Presentation applies to the SP605
5 Software Requirements Xilinx ISE 11.4 software
6 Software Requirements Spartan-6 GTP ACE Files ACE files for Spartan-6 GTP Designs requires an environment variable set Set XIL_CONFIG_USE_ISC_DISABLE=true See AR 33575
7 ChipScope Pro Software Requirement Xilinx ChipScope Pro 11.4 software
8 Setup for the SP605 IBERT Designs
9 Setup for the SP605 IBERT Designs Unzip the rdf0036.zip file to your C:\ drive
10 Setup for the SP605 IBERT Designs Connect a USB Type-A to Mini-B cable to the USB JTAG connector on the SP605 board Connect this cable to your PC
11 Setup for the SP605 IBERT Designs SMA Cable P/N: ASPI-024-ASPI-S402
12 Setup for the SP605 IBERT Designs Using the SMA cables: Connect J32 to J34
13 Setup for the SP605 IBERT Designs Using the SMA cables: Connect J33 to J35
14 Setup for the SP605 IBERT Designs Connect Optical Loopback Adapter SFP Loopback Adapter, 3.5 db Attenuation Part # Alternatively, use an SFP transceiver with a fiber optic cable Insert into the SFP Connector on the SP605 board Connect the SP605 Power and turn the SP605 on
15 Running the SP605 IBERT Design
16 Running the SP605 IBERT Design Open ChipScope Pro and click on the Open Cable Button (1) Click OK (2) 1 2
17 Running the SP605 IBERT Design Select Device DEV:1 MyDevice1 (XC6SLX45T) Configure Select <Design Path>\sp605_ibert.bit
18 Running the SP605 IBERT Design Select File Open Project Select <Design Path>\sp605_ibert.cpj
19 Running the SP605 IBERT Design Click Yes on this Dialog
20 Note: Left to right: PCIe, SMA, SFP, FMC_LPC Running the SP605 IBERT Design The line rate is 2.5 Gbps for all four GTPs (1) Near-End PMA is selected for the PCIe and FMC GTPs (2) 1 2 2
21 Running the SP605 IBERT Design TX Diff Output Swing = 695 mv (0100) TX Pre-emphasis = 1.7 db (010)
22 Running the SP605 IBERT Design TX/RX Data Patterns are set to PRBS 7-bit (1) Click BERT Reset buttons (2) 1 2
23 Running the SP605 IBERT Design View the RX Bit Error Count (1) 1
24 SP605 IBERT Design Creation
25 Create IBERT CORE Generator Project Open the CORE Generator Start All Programs Xilinx ISE Design Suite 11 ISE Accessories CORE Generator Create a new project; select File New Project
26 Create IBERT CORE Generator Project Create a project directory: sp605_ibert Name the project: sp605_ibert.cgp The Project options will appear Set the Part (as seen here): Family: Spartan6 Device: xc6slx45t Package: fgg484 Speed Grade: -3
27 Create IBERT CORE Generator Project Select Generation Set the Design Entry to Verilog Click OK
28 Create IBERT Design Right click on the IBERT Spartan6 GTP (ChipScope Pro - IBERT, Version 2.00a Select Customize
29 Create IBERT Design Make the following settings: Component name: sp605_ibert Set the number of Line Rates: 1 Set the line rate to Max Rate: 2.5 Gbps Set the RefClk frequency to: 125 MHz Click Next
30 Create IBERT Design Select both GTPs: GTPA_DUAL_X1_Y0 GTPA_DUAL_X0_Y0 Connect both Refclks to: REFCLK0 X1Y0 This connects both GTPs to the 125 MHz SFP Clock Click Next
31 Create IBERT Design Leave this screen as is Click Next
32 Create IBERT Design Select the following settings: Use External Clock source Frequency (MHz): 200 Location: K21 Click Next
33 Create IBERT Design Click Generate
34 Create IBERT Design After the IBERT core finishes generating, click Close on the Datasheet window
35 Create IBERT ACE File (Optional) Type these commands in a windows command shell: cd C:\sp605_ibert\ready_for_download make_ace.bat
36 References
37 References ChipScope Pro ChipScope Pro 11.1 ChipScope Pro Software and Cores User Guide xilinx11/chipscope_pro_sw_cores_ug029.pdf
38 Documentation
39 Documentation Spartan-6 Spartan-6 FPGA Family SP605 Documentation Spartan-6 FPGA SP605 Evaluation Kit SP605 Hardware User Guide SP605 Reference Design User Guide
SP605 GTP IBERT Design Creation
SP605 GTP IBERT Design Creation October 2010 Copyright 2010 Xilinx XTP066 Revision History Date Version Description 10/05/10 12.3 Recompiled under 12.3. ARs Present in Spartan-6 IBERT Design: AR36775 Delay
ML605 GTX IBERT Design Creation
ML605 GTX IBERT Design Creation December 2010 Copyright 2010 Xilinx XTP046 Revision History Date Version Description 12/21/10 12.4 Recompiled under 12.4. 10/05/10 12.3 Recompiled under 12.3. AR36576 fixed.
KC705 GTX IBERT Design Creation October 2012
KC705 GTX IBERT Design Creation October 2012 XTP103 Revision History Date Version Description 10/23/12 4.0 Regenerated for 14.3. 07/25/12 3.0 Regenerated for 14.2. Added AR50886. 05/30/12 2.1 Minor updates.
SP605 MIG Design Creation
SP605 MIG Design Creation December 2009 Copyright 2009 Xilinx XTP060 Note: This presentation applies to the SP605 Overview Spartan-6 Memory Controller Block Xilinx SP605 Board Software Requirements SP605
KC705 Ethernet Design Creation October 2012
KC705 Ethernet Design Creation October 2012 XTP147 Revision History Date Version Description 10/23/12 4.0 Regenerated for 14.3. 07/25/12 3.0 Regenerated for 14.2. Added AR50886. 05/08/12 2.0 Regenerated
ZC706 GTX IBERT Design Creation June 2013
ZC706 GTX IBERT Design Creation June 2013 XTP243 Revision History Date Version Description 06/19/13 4.0 Recompiled for Vivado 2013.2. 04/16/13 3.1 Added AR54225. 04/03/13 3.0 Recompiled for 14.5. 01/18/13
ZC706 GTX IBERT Design Creation November 2014
ZC706 GTX IBERT Design Creation November 2014 XTP243 Revision History Date Version Description 11/24/14 10.0 Regenerated for 2014.4. 10/08/14 9.0 Regenerated for 2014.3. 06/09/14 8.0 Regenerated for 2014.2.
ML605 PCIe x8 Gen1 Design Creation
ML605 PCIe x8 Gen1 Design Creation March 2010 Copyright 2010 Xilinx XTP044 Note: This presentation applies to the ML605 Overview Virtex-6 PCIe x8 Gen1 Capability Xilinx ML605 Board Software Requirements
VCU110 GT IBERT Design Creation
VCU110 GT IBERT Design Creation June 2016 XTP374 Revision History Date Version Description 06/08/16 4.0 Updated for 2016.2. 04/13/16 3.0 Updated for 2016.1. Updated for Production Kit. 02/03/16 2.1 Updated
ML631 U2 DDR3 MIG Design Creation
ML631 U2 DDR3 MIG Design Creation March 2012 Copyright 2012 Xilinx XTP129 Revision History Date Version Description 03/16/12 13.4 Updated for 13.4 10/26/11 13.3 Updated for 13.3. 08/30/11 13.2 Initial
ML631 U1 DDR3 MIG Design Creation
ML631 U1 DDR3 MIG Design Creation October 2011 Copyright 2011 Xilinx XTP112 Revision History Date Version Description 10/26/11 13.3 Updated for 13.3. 08/30/11 13.2 Initial version. Copyright 2011 Xilinx,
ML605 PCIe x8 Gen1 Design Creation
ML605 PCIe x8 Gen1 Design Creation October 2010 Copyright 2010 Xilinx XTP044 Revision History Date Version Description 10/05/10 12.3 Recompiled under 12.3. AR35422 fixed; included in ISE tools. 07/23/10
ML605 Restoring Flash Contents
ML605 Restoring Flash Contents March 2011 Copyright 2011 Xilinx XTP055 Revision History Date Version Description 03/01/11 13.1 Regenerated contents for 13.1. 12/21/10 12.4 Regenerated contents for 12.4.
KC705 Si5324 Design October 2012
KC705 Si5324 Design October 2012 XTP188 Revision History Date Version Description 10/23/12 4.0 Recompiled for 14.3. 07/25/12 3.0 Recompiled for 14.2. Added AR50886. 05/08/12 2.0 Recompiled for 14.1. 02/14/12
SP623 IBERT Getting Started Guide (ISE 13.4) UG752 (v6.0) February 29, 2012
SP623 IBERT Getting Started Guide (ISE 13.4) Copyright 2010 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks
Virtex-6 FPGA Connectivity Kit
Virtex-6 FPGA Connectivity Kit Getting Started Guide XPN 0402826-01 Xilinx is disclosing this user guide, manual, release note, and/or specification (the Documentation ) to you solely for use in the development
SP623 IBERT Getting Started Guide (ISE 12.1) UG752 (v2.0.1) January 26, 2011
SP623 IBERT Getting Started Guide (ISE 12.1) Xilinx is providing this product documentation, hereinafter Information, to you AS IS with no warranty of any kind, express or implied. Xilinx makes no representation
ML605 FMC Si570 Programming June 2012
ML605 FMC Si570 Programming June 2012 XTP076 Revision History Date Version Description 06/15/12 1.0 Initial version for 13.4. Copyright 2012 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the
SP601 Standalone Applications
SP601 Standalone Applications December 2009 Copyright 2009 Xilinx XTP053 Note: This presentation applies to the SP601 Overview Xilinx SP601 Board Software Requirements SP601 Setup Multi-pin Wake-up GPIO
KC705 Si570 Programming
KC705 Si570 Programming March 2012 Copyright 2012 Xilinx XTP186 Revision History Date Version Description 03/02/12 13.4 Initial version. Copyright 2012 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx
SP623 IBERT Getting Started Guide (ISE 13.1) UG752 (v4.0) May 5, 2011
SP623 IBERT Getting Started Guide (ISE 13.1) Copyright 2010 2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks
Spartan-6 & Virtex-6 FPGA Connectivity Kit FAQ
1 P age Spartan-6 & Virtex-6 FPGA Connectivity Kit FAQ April 04, 2011 Getting Started 1. Where can I purchase a kit? A: You can purchase your Spartan-6 and Virtex-6 FPGA Connectivity kits online at: Spartan-6
English Japanese
Spartan -6 FPGA Consumer Video Kit FAQ General Questions: Q: What is the Spartan -6 FPGA Consumer Video Kit? A: The Spartan-6 FPGA Consumer Video Kit (CVK) consists of a Spartan-6 LX150T base board, four
ML623 IBERT Getting Started Guide (ISE 13.4) UG725 (v6.0) February 29, 2012
ML623 IBERT Getting Started Guide (ISE 13.4) Copyright 2010 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks
SP605 Standalone Applications
SP605 Standalone Applications July 2011 Copyright 2011 Xilinx XTP064 Revision History Date Version Description 07/06/11 13.2 Up-rev 13.1 GPIO_HDR Design to 13.2. 03/01/11 13.1 Up-Rev 12.4 GPIO_HDR Design
ML623 IBERT Getting Started Guide (ISE 12.1) UG725 (v2.0.1) January 28, 2011
ML623 IBERT Getting Started Guide (ISE 12.1) Xilinx is disclosing this user guide, manual, release note, and/or specification (the Documentation ) to you solely for use in the development of designs to
SP605 MultiBoot Design
SP605 MultiBoot Design December 2009 Copyright 2009 Xilinx XTP059 Note: This presentation applies to the SP605 Overview Spartan-6 MultiBoot Capability Xilinx SP605 Board Software Requirements SP605 Setup
SP605 Built-In Self Test Flash Application
SP605 Built-In Self Test Flash Application March 2011 Copyright 2011 Xilinx XTP062 Revision History Date Version Description 03/01/11 13.1 Up-rev 12.4 BIST Design to 13.1. 12/21/10 12.4 Up-rev 12.3 BIST
ML623 IBERT Getting Started Guide (ISE 13.2) UG725 (v5.0) July 6, 2011
ML623 IBERT Getting Started Guide (ISE 13.2) Copyright 2010 2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks
SATA Storage Duplicator Instruction on KC705 Rev Sep-13
SATA Storage Duplicator Instruction on KC705 Rev1.0 24-Sep-13 This document describes the step to run SATA Duplicator Demo for data duplication from one SATA disk to many SATA disk by using Design Gateway
KC705 PCIe Design Creation with Vivado August 2012
KC705 PCIe Design Creation with Vivado August 2012 XTP197 Revision History Date Version Description 08/20/12 1.0 Initial version. Added AR50886. Copyright 2012 Xilinx, Inc. All Rights Reserved. XILINX,
Virtex-7 FPGA VC7215 Characterization Kit IBERT
Virtex-7 FPGA VC7215 Characterization Kit IBERT Getting Started Guide Vivado Design Suite 2013.3 DISCLAIMER The information disclosed to you hereunder (the Materials ) is provided solely for the selection
SP605 MultiBoot Design
SP605 MultiBoot Design October 2010 Copyright 2010 Xilinx XTP059 Revision History Date Version Description 10/05/10 12.3 Recompiled under 12.3. 07/23/10 12.2 Recompiled under 12.2. Copyright 2010 Xilinx,
ML605 Built-In Self Test Flash Application
ML605 Built-In Self Test Flash Application July 2011 Copyright 2011 Xilinx XTP056 Revision History Date Version Description 07/06/11 13.2 Up-rev 13.1 BIST Design to 13.2. 03/01/11 13.1 Up-rev 12.4 BIST
SP601 Built-In Self Test Flash Application
SP601 Built-In Self Test Flash Application December 2009 Copyright 2009 Xilinx XTP041 Note: This presentation applies to the SP601 Overview Xilinx SP601 Board Software Requirements SP601 Setup SP601 BIST
Spartan-6 and Virtex-6 FPGA Embedded Kit FAQ
Spartan-6 and Virtex-6 FPGA FAQ February 5, 2009 Getting Started 1. Where can I purchase an Embedded kit? A: You can purchase your Spartan-6 and Virtex-6 FPGA Embedded kits online at: Spartan-6 FPGA :
ZC702 Si570 Programming June 2012
June 2012 XTP181 Revision History Date Version Description 05/25/12 1.0 Initial version for 14.1. Copyright 2012 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated
ML605 Built-In Self Test Flash Application
ML605 Built-In Self Test Flash Application October 2010 Copyright 2010 Xilinx XTP056 Revision History Date Version Description 10/05/10 12.3 Up-rev 12.2 BIST Design to 12.3. Added AR38127 Added AR38209
AC701 Ethernet Design Creation October 2014
AC701 Ethernet Design Creation October 2014 XTP223 Revision History Date Version Description 10/08/14 9.0 Regenerated for 2014.3. 06/09/14 8.0 Regenerated for 2014.2. 04/16/14 6.0 Regenerated for 2014.1.
ChipScope Pro Software and Cores
í ChipScope Pro Software and Cores User Guide [] [] Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs
AC701 Ethernet Design Creation June 2014
AC701 Ethernet Design Creation June 2014 XTP223 Revision History Date Version Description 06/09/14 8.0 Regenerated for 2014.2. 04/16/14 6.0 Regenerated for 2014.1. 12/18/13 5.0 Regenerated for 2013.4.
Virtex 6 FPGA Broadcast Connectivity Kit FAQ
Getting Started Virtex 6 FPGA Broadcast Connectivity Kit FAQ Q: Where can I purchase a kit? A: Once the order entry is open, you can purchase your Virtex 6 FPGA Broadcast Connectivity kit online or contact
í ChipScope Pro Software and Cores User Guide [] UG029 (v14.2) July 25, 2012
![í ChipScope Pro Software and Cores User Guide [] UG029 (v14.2) July 25, 2012](/thumbs/89/97719730.jpg "í ChipScope Pro Software and Cores User Guide [] UG029 (v14.2) July 25, 2012")
í ChipScope Pro Software and Cores User Guide [] [] Notice of Disclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx products. To
SP601 MultiBoot Design
SP601 MultiBoot Design December 2009 Copyright 2009 Xilinx XTP038 Note: This presentation applies to the SP601 Overview Spartan-6 MultiBoot Capability Xilinx SP601 Board Software Requirements SP601 Setup
SATA-IP Bridge Demo Instruction on AC701 Rev1.0 9-May-14
SATA-IP Bridge Demo Instruction on AC701 Rev1.0 9-May-14 This document describes SATA-IP Bridge evaluation procedure using bit file from Bridge reference design on AC701 board. 1 Environment For real board
S2C K7 Prodigy Logic Module Series
S2C K7 Prodigy Logic Module Series Low-Cost Fifth Generation Rapid FPGA-based Prototyping Hardware The S2C K7 Prodigy Logic Module is equipped with one Xilinx Kintex-7 XC7K410T or XC7K325T FPGA device
Virtex-6 FPGA Connectivity Kit
Virtex-6 FPGA Connectivity Kit Getting Started Guide XPN 0402826-03 Notice of Disclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx
JESD204B Xilinx/IDT DAC1658D-53D interoperability Report
[Interoperability Report] Rev 0.4 Page 1 of 14 JESD204B Xilinx/IDT DAC1658D-53D interoperability Report [Interoperability Report] Rev 0.4 Page 2 of 14 CONTENTS INTRODUCTION... 3 SCOPE... 3 HARDWARE...
LogiCORE IP Spartan-6 FPGA GTP Transceiver Wizard v1.9
LogiCORE IP Spartan-6 FPGA GTP Transceiver Wizard v1.9 Getting Started Guide Xilinx is providing this product documentation, hereinafter Information, to you AS IS with no warranty of any kind, express
VCU110 Software Install and Board Setup October 2015
VCU110 Software Install and Board Setup October 2015 XTP380 Revision History Date Version Description 11/20/15 1.2 Modified to match VCU110 Kit hardware. 10/22/15 1.1 Added ExaMax and Interlaken setup.
Spartan-6 FPGA Connectivity Kit
Spartan-6 FPGA Connectivity Kit Getting Started Guide XPN 0402823-03 Copyright 2009 2013 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included
Avnet S6LX16 Evaluation Board and Maxim DAC/ADC FMC Module Reference Design
Avnet S6LX16 Evaluation Board and Maxim DAC/ADC FMC Module Reference Design By Nasser Poureh, Avnet Technical Marketing Manager Mohammad Qazi, Maxim Application Engineer, SP&C Version 1.0 August 2010 1
Arria 10 FPGA Development Kit User Guide
Arria 10 FPGA Development Kit User Guide Subscribe UG-20007 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Arria 10 FPGA Development Kit Contents Arria 10 FPGA Development Kit Overview...
Virtex-5 GTP Aurora v2.8
0 DS538 October 10, 2007 0 0 Introduction The Virtex -5 GTP Aurora core implements the Aurora protocol using the high-speed serial GTP transceivers in Virtex-5 LXT and SXT devices. The core can use up
SATA-IP Device Demo Instruction on AC701 Rev Apr-14
SATA-IP Device Demo Instruction on AC701 Rev1.0 11-Apr-14 This document describes SATA-IP Device evaluation procedure on AC701 using SATA-IP Device reference design bit-file. 1 Environment For real board
Spartan -6 LX150T Development Kit Hardware Co-Simulation Reference Design Tutorial
Spartan -6 LX150T Development Kit H/W Co-Simulation Reference Design Tutorial Spartan -6 LX150T Development Kit Hardware Co-Simulation Reference Design Tutorial Version 1.0 Revision History Version Description
Virtex-6 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.4
DS710 April 19, 2010 Introduction The LogiCORE IP Virtex -6 FPGA Embedded Tri- Mode Ethernet MAC Wrapper automates the generation of HDL wrapper files for the Embedded Tri- Mode Ethernet MAC (Ethernet
Terasic THDB-SUM SFP. HSMC Terasic SFP HSMC Board User Manual
Terasic THDB-SUM SFP HSMC Terasic SFP HSMC Board User Manual Document Version 1.00 AUG 12, 2009 by Terasic Introduction Page Index INTRODUCTION... 1 1.1 1.1 FEATURES... 1 1.2 1.2 ABOUT THE KIT... 2 1.3
Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC Wrapper v1.7
DS550 April 19, 2010 Virtex-5 FPGA Embedded Tri-Mode Wrapper v1.7 Introduction The LogiCORE IP Virtex -5 FPGA Embedded Tri-Mode Wrapper automates the generation of HDL wrapper files for the Embedded Tri-Mode
SFPFMC User Manual Rev May-14
SFPFMC User Manual Rev1.0 15-May-14 1 Introduction Thank you for choosing SFPFMC board [Part Number: AB15-SFPFMC]. SFPFMC board is compliant with FMC standard (HPC) and provides four SFP+ channels, so
Programming Xilinx SPARTAN 3 Board (Simulation through Implementation)
Programming Xilinx SPARTAN 3 Board (Simulation through Implementation) September 2008 Prepared by: Oluwayomi Adamo Class: Project IV University of North Texas FPGA Physical Description 4 1. VGA (HD-15)
SATA-IP Host Demo Instruction on SP605 Rev Jan-10
SATA-IP Host Demo Instruction on SP605 Rev1.0 21-Jan-10 This document describes SATA-IP Host evaluation procedure using SATA-IP Host reference design bit-file. 1 Environment For real board evaluation of
Virtex-6 FPGA GTX Transceiver OTU1 Electrical Interface
Virtex-6 FPGA GTX Transceiver OTU1 Electrical Interface Characterization Report Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for
Detector interface updates (SVD,ECL,EPID)
Detector interface updates(svd,ecl,epid) M. Nakao p.1 Detector interface updates (SVD,ECL,EPID) Mikihiko Nakao(KEK-IPNS) mikihiko.nakao@kek.jp December 16, 2010 Belle II DAQ meeting, KEK Detector interface
Pico ChipScope Documentation
Pico ChipScope Documentation Contents 1 Disclaimer 1 2 Overview 1 3 Firmware 2 4 Pico Module 6 4.1 M-503 Cables...................................................... 6 4.2 M-505 Cables......................................................
AC701 Built-In Self Test Flash Application April 2015
AC701 Built-In Self Test Flash Application April 2015 XTP194 Revision History Date Version Description 04/30/14 11.0 Recompiled for 2015.1. Removed Ethernet as per CR861391. 11/24/14 10.0 Recompiled for
A Real Time Implementation of High Speed Data Transmission using Aurora Protocol on Multi-Gigabit Transceivers in Virtex-5 FPGA
A Real Time Implementation of High Speed Data Transmission using Aurora Protocol on Multi-Gigabit Transceivers in Virtex-5 FPGA T.Vijaya Bhaskar Reddy Computers and Communications (M.tech ), ECE Department,
H-tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
H-tile Hard IP for Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
Accelerating System Designs Requiring High-Bandwidth Connectivity with Targeted Reference Designs
White Paper: Spartan-6 and Virtex-6 FPGAs WP359 (v1.0) December 8, 2009 Accelerating System Designs Requiring High-Bandwidth Connectivity with Targeted Reference Designs By: Navneet Rao FPGAs that provide
LogiCORE IP Spartan -6 FPGA GTP Transceiver Wizard v1.8
LogiCORE IP Spartan -6 FPGA GTP Transceiver Wizard v1.8 Getting Started Guide Xilinx is providing this product documentation, hereinafter Information, to you AS IS with no warranty of any kind, express
LogiCORE TM IP Aurora 8B/10B v5.3
LogiCORE TM IP Aurora 8B/10B v5.3 User Guide Xilinx is providing this product documentation, hereinafter Information, to you AS IS with no warranty of any kind, express or implied. Xilinx makes no representation
Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
Low Latency 100G Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
IGLOO2 Evaluation Kit Webinar
Power Matters. IGLOO2 Evaluation Kit Webinar Jamie Freed jamie.freed@microsemi.com August 29, 2013 Overview M2GL010T- FG484 $99* LPDDR 10/100/1G Ethernet SERDES SMAs USB UART Available Demos Small Form
January 19, 2010 Product Specification Rev1.0. Core Facts. Documentation Design File Formats. Slices 1 BUFG/
January 19, 2010 Product Specification Rev1.0 Design Gateway Co.,Ltd 54 BB Building 13 th Fl., Room No.1302 Sukhumvit 21 Rd. (Asoke), Klongtoey-Nua, Wattana, Bangkok 10110 Phone: (+66) 02-261-2277 Fax:
QPairs QTE/QSE-DP Multi-connector Stack Designs In PCI Express Applications 16 mm Connector Stack Height REVISION DATE: OCTOBER 13, 2004
Application Note QPairs QTE/QSE-DP Multi-connector Stack Designs In PCI Express Applications 16 mm Connector Stack Height REVISION DATE: OCTOBER 13, 2004 Copyrights and Trademarks Copyright 2004 Samtec,
Virtex-6 FPGA ML605 Evaluation Kit FAQ June 24, 2009
Virtex-6 FPGA ML605 Evaluation Kit FAQ June 24, 2009 Getting Started Q: Where can I purchase a kit? A: Once the order entry is open, you can purchase your ML605 kit online at: http://www.xilinx.com/onlinestore/v6_boards.htm
ISE Design Suite Software Manuals and Help
ISE Design Suite Software Manuals and Help These documents support the Xilinx ISE Design Suite. Click a document title on the left to view a document, or click a design step in the following figure to
Absolute Maximum Ratings Parameter Symbol Min Max Unit Supply Voltage Vcc V Storage Temperature Ts C Technical Specifications Parameter
10G SFP+ AOC Checker Features 8.5G 9.95~11.1Gbps BERT Optical Power Meter:1270~1610nm SFP+ status checker Friendly graphic user interface (GUI) 2 SFP+ ports 5V DC power supply Small form & full metal case
Virtex-6 FPGA GTX Transceiver Characterization Report
Virtex-6 FPGA GTX Transceiver Characterization Report PCI Express 2.0 (2.5 and 5.0 Gb/s) Electrical Standard Xilinx is disclosing this user guide, manual, release note, and/or specification (the Documentation
RocketIO X BERT Reference Design User Guide
ocketio X BERT Reference Design User Guide MK32x Development Platforms R "Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved.
Adding the ILA Core to an Existing Design Lab
Adding the ILA Core to an Existing Introduction This lab consists of adding a ChipScope Pro software ILA core with the Core Inserter tool and debugging a nonfunctioning design. The files for this lab are
ASNT_MUX64 64Gbps 2:1 Multiplexer
ASNT_MUX64 64Gbps 2:1 Multiplexer 105ps data phase shift capability for both data inputs VCO s from 20GHz to 32.1GHz User selectable clock divide by 2 to 512 sync output for scope triggering 17ps Rise/Fall
Fibre Channel Arbitrated Loop v2.3
- THIS IS A DISCONTINUED IP CORE - 0 Fibre Channel Arbitrated Loop v2.3 DS518 March 24, 2008 0 0 Introduction The LogiCORE IP Fibre Channel Arbitrated Loop (FC-AL) core provides a flexible, fully verified
Spartan -6 LX150T Development Kit Hardware Co-Simulation Reference Design User Guide
Spartan -6 LX150T Development Kit H/W Co-Simulation Reference Design User Guide Spartan -6 LX150T Development Kit Hardware Co-Simulation Reference Design User Guide Version 0.8 Revision History Version
Virtual Input/Output v3.0
Virtual Input/Output v3.0 LogiCORE IP Product Guide Vivado Design Suite Table of Contents IP Facts Chapter 1: Overview Feature Summary..................................................................
The FPGA Design and Implementation of Reflective Memory Card Based on the PCIE Bus
2016 International Congress on Computation Algorithms in Engineering (ICCAE 2016) ISBN: 978-1-60595-386-1 The FPGA Design and Implementation of Reflective Memory Card Based on the PCIE Bus Zheng Bian,
SATA Host-IP Demo Instruction Rev Jan-18
SATA Host-IP Demo Instruction Rev1.6 15-Jan-18 This document describes the instruction to run SATA Host-IP demo on FPGA development board and AB09-FMCRAID board. The demo is designed to write/verify data
AccelDSP tutorial 2 (Matlab.m to HDL for Xilinx) Ronak Gandhi Syracuse University Fall
AccelDSP tutorial 2 (Matlab.m to HDL for Xilinx) Ronak Gandhi Syracuse University Fall 2009-10 AccelDSP Getting Started Tutorial Introduction This tutorial exercise will guide you through the process of
Muon Port Card Upgrade Status May 2013
CSC Endcap Muon Port Card and Muon Sorter Upgrade Status May 2013 MPC Upgrade Requirements Be able to deliver all 18 trigger primitives from the EMU peripheral crate to the upgraded Sector Processor Preserve
TOE1G-IP Two-Port Demo Instruction
TOE1G-IP Two-Port Demo Instruction Rev1.2 2-Sep-16 1 Environment Setup As shown in Figure 1 Figure 2, to run TOE1G-IP FTP demo, please prepare 1) FPGA Development board (AC701/KC705/ZC706) 2) ISE ver 14.4
SerDes Channel Simulation in FPGAs Using IBIS-AMI
White Paper: Virtex-6 FPGA Family WP382 (v10) December 9, 2010 SerDes Channel Simulation in FPGAs Using IBIS-AMI By: Romi Mayder The IBIS Algorithmic Modeling Interface (IBIS-AMI) was developed to enable
SDRAM Interface Clocking for the NanoBoard 2
SDRAM Interface Clocking for the NanoBoard 2 NB2 + DB30 Xilinx Spartan 3 DaughterBoard 1. Schematic wiring for Xilinx DCM clocks. 2. Shared Memory Port Plugin wiring. NB2 + DB31 Altera Cyclone II DaughterBoard
Arria V GX Transceiver Starter Kit
Page 1 of 4 Arria V GX Transceiver Starter Kit from Altera Ordering Information Transceiver Starter Kit Contents Starter Board Photo Related Links The Altera Arria V GX Transceiver Starter Kit provides
Validating ADI Converters inter-operability with Xilinx FPGA and JESD204B IP
Validating ADI Converters inter-operability with Xilinx FPGA and JESD204B IP Introduction ADI continues to develop world class converter technologies and as a result requires us to develop high throughput
Intel Stratix 10 Low Latency 40G Ethernet Design Example User Guide
Intel Stratix 10 Low Latency 40G Ethernet Design Example User Guide Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Quick Start Guide...
Xilinx ISE8.1 and Spartan-3 Tutorial EE3810
Xilinx ISE8.1 and Spartan-3 Tutorial EE3810 1 Part1) Starting a new project Simple 3-to-8 Decoder Start the Xilinx ISE 8.1i Project Navigator: Select File > New Project in the opened window 2 Select a
Hardware Demonstration Design
Hardware Demonstration Design JESD204 Hardware Demonstration User Guide 1 A hardware demonstration design, targeting the Kintex-7 KC705, Zynq-7000 ZC706, Virtex-7 VC709 or Artix-7 AC701 evaluation platforms,
Lab 3: Xilinx PicoBlaze Flow Lab Targeting Spartan-3E Starter Kit
Lab 3: Xilinx PicoBlaze Flow Lab Targeting Spartan-3E Starter Kit Xilinx PicoBlaze Flow Demo Lab www.xilinx.com 1-1 Create a New Project Step 1 Create a new project targeting the Spartan-3E device that
ECT 224: Digital Computer Fundamentals Using Xilinx StateCAD
ECT 224: Digital Computer Fundamentals Using Xilinx StateCAD 1) Sequential circuit design often starts with a problem statement tat can be realized in the form of a state diagram or state table a) Xilinx
Vivado Design Suite Tutorial:
Vivado Design Suite Tutorial: Programming and Debugging Notice of Disclaimer The information disclosed to you hereunder (the Materials ) is provided solely for the selection and use of Xilinx products.