Pro Asic3 - Radiation test at CHARM. Christophe Godichal BE/BI/QP
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1 Pro Asic3 - Radiation test at CHARM Christophe Godichal BE/BI/QP christophe.godichal@cern.ch 1
2 Test Setup CHAM Beam room CHARM Maze CHARM control room GEFE Optical Power Cable Patch Panel Patch Panel Optical Back-End board Ethernet Power supply Power supply PS 1 PS 2 2
3 Test Setup CHAM Beam room CHARM Maze CHARM control room GEFE Optical Power Cable Patch Panel Patch Panel Optical Back-End board Ethernet Power supply Power supply PS 1 PS 2 40 GBTx Elinks GBTx GBTx Clock 40 Elinks GBTx To FPGA 40 Elinks FPGA To GBTx ProAsic3e 80 lines in the FPGA 2 use for Reset, Enable flag 78 use for the test logic 3
4 FPGA Configuration Test Logic used 52% of the FPGA Test Logic DDR TO SDR SDR TO DDR Test Logic 4
5 Test Logic 16 Shift-Register with different combinaison of logic gate between register Without logic gate between registers NOT gates AND gates OR gates 12 Shift-Register TMR with the same combinaison of the Shift-register without TMR 5
6 Test Logic: Shift-Register Objective: SEU detection Register arrangment 2 SR with 350 reg. placed «randomly» by the compiler 3 SR with 350 reg. placed manually at the extreme of the FPGA 32 bit shift register (manual placement) Long connection in the fabric 6 32 bit shift register (manual placement)
7 Shift-Register with Logic Gates S SET Q S SET Q S SET Q R CLR Q R CLR Q R CLR Q Shift-Registers with 8 NOT gates between each register Objective SEU detection SET 2 SR with 350 reg. placed «randomly» by the compiler 3 SR with 350 reg. placed manually at the extreme of the FPGA Shift-Registers with 8 AND gates between each register Sensibility of SEU and SET 3 SR with 350 reg. placed manually at the extreme of the FPGA Shift-Registers with 8 Or gate between each register Sensibility of SEU and SET 3 SR with 350 reg. placed manually at the extreme of the FPGA 7
8 Shift-Register With «TMR» Shift-Registers with «TMR» SEU Immune, SET in the voter 3 Simple SR, 3 with 8 NOT gate, 3 with 8 AND gate, 3 with 8 OR gate (all SR with 350 reg TMR) Test is used to compare sensibility of Shift-Register with TMR and without TMR 8
9 Results - TID results Type of SR Manual Placement in the FPGA Placed by the Compiler Shift-Register TMR Gy Gy Gy SR_ SR_ SR_ SR_NOT_ SR_NOT_ SR_NOT_ SR_AND_ SR_AND_ SR_AND_ SR_OR_ SR_OR_1 459 SR_OR_2 485 Manual placement in the FPGA has failed from 485Gy to 538 Gy Placed by the compiler has failed from 467Gy to 492Gy Shift-Register TMR has failed from 461Gy to 511Gy FPGA Stopped working at 752Gy 9
10 Results #errors and Cross-Section σσ = #eeeeeeeeeeee #DDDDDD ffffffffffffff ffffffffffffff = 1.67EE + 12 σσ uuuuuuuuuuuuuuuuuuuuuu = SSSSSS. dddddd #DDDDDD ffffffffffffff Without TMR Type Total Nb of Register Total Nb of Errors Cross- Section Cross Section uncertainty Simple E E-15 Not Gate E E-15 And Gate E E-15 Or Gate E E-15 10
11 Results #errors and Cross-Section σσ = #eeeeeeeeeeee #DDDDDD ffffffffffffff ffffffffffffff = 1.67EE + 12 σσ uuuuuuuuuuuuuuuuuuuuuu = SSSSSS. dddddd #DDDDDD ffffffffffffff With TMR Type Total Nb of Register Mean (λ) std dev (σ) Cross- Section Cross Section uncertainty Simple E E-15 Not Gate And Gate Or Gate E E E E E E-15 11
12 Results Confidence on TMR results The I/O of the Shift-Register with TMR are not TMR too We have 2 register in the input and 1 register in the output port What is the probability to have one error on these i/o port? Type #I/O reg Cross- Section Error I/O reg probability Simple E Not Gate E And Gate E Or Gate E PP EEEEEEEEEE ii 0 rrrrrr = σσ # ii oo rrrrrr ffffffffffffff 12
13 Results Difference between SR not TMR and SR TMR No TMR TMR Type Improvement σ σ Simple 9.14E E Not Gate 8.76E E And Gate 8.33E E Or Gate 8.90E E IIIIIIIIIIIIIIIIIIIIII = σ NNNNNNNNNN σ TTTTTT 13
14 Conclusion All shift register stopped around 500Gy The ProAsic dies around 750Gy We have few errors on TMR-ed chain, so the statistics or not really good We can suppose error in the I/O cell in the Shift-Register TMR Future testing can be programmed to test more in details the propagation delays 14
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