Digitizer products. VME NIM Desktop

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1 Digitizer products Index Introduction... pag. 19 Principles of Operation... pag. 20 Digital Pulse Processing (DPP) for physics and biomedical applications... pag. 20 Trigger and synchronization in multi-board systems... pag. 22 Software... pag. 22 Application... pag. 23 CAEN Waveform Digitizers feature Digital Pulse Processing (DPP) firmware for physics applications. DPP algorithms are implemented in FPGA and can be reprogrammed at any time. In one single module you have the complete information and the capability to extract all the quantities of interest. The CAEN Digitizers are Platform independent instruments housing high speed (up to 5 GS/s) multichannel flash ADC, with local memory and FPGA for real-time data processing. Available in different form factors: VME, NIM, Desktop. Up to 14 bit resolution VME64X, Optical Link, USB 2.0 Interfaces available Memory buffer: up to 58 MS/ch (max events) Multi-board synchronization and trigger distribution FPGA fimware for Digital Pulse Processing - Pulse triggering - Zero suppression - Pulse Height Analysis - Charge Integration - Gamma-Neutron discrimination - Time measurement - Possibility of customization Software Tools for Windows and Linux VME NIM Desktop 18 Short Form Catalog 2012 More Technical Specifications available on

2 Introduction CAEN has developed a complete family of digitizers that consists of several models differing in sampling frequency, resolution, number of channels, form factor, memory size and other parameters. The following table lists all models currently available. In parallel with the hardware development, CAEN has made a big effort in developing algorithms for the Digital Pulse Processing (DPP); you can install a DPP algorithm on the FPGA of the digitizer (firmware upgrade), run it on-line and implement new acquisition methods that go beyond the simple waveform recording. A digitizer with DPP becomes a new instrument that represents a fully digital replacement of most traditional modules such as Multi and Single Channel Analyzers, QDCs, TDCs, Discriminators and many others. The purpose of the following pages is to provide an overview on the digitizers, explain the main characteristics and the different operating modes and present the available options in terms of hardware, firmware and software in order to guide you in your choice. DIGITIZERS Digitizers Selection Table Model (1) Form Factor N. of ch. (4) Max. Sampling Frequency (MS/s) N. of Bits Input Dynamic Range (Vpp) (4) Single Ended / Differential Input Bandwidth (MHz) Memory (MS/ch) (4) DPP firmware (5) x724 VME / 2.25 / 10 Desktop/NIM 4 / 2 SE / 4 PHA x720 VME Desktop/NIM 4 / 2 SE / 10 CI, PSD x721 VME no x731 VME / / 4 no x730 VME Desktop/NIM 4 / 2 SE / 10 PSD x751 VME Desktop/NIM 4-2 SE / / 28.8 PSD x761 VME Desktop/NIM 1 SE TBD 7.2 / 57.6 no x740 VME 64 Desktop/NIM / 10 SE / 1.5 no x742 VME 32+2 Desktop/NIM (2) 12 1 SE / 1 (3) no All models Analog Input Trigger Synchronization Memory FPGA Readout Other features Single Ended: MCX 50 Ω; Differential (where present): MODU-II 110 Ω DC offset adjust in the full range (±FSR/2) Positive, negative and bipolar inputs External TRG-IN, Software or channel self-trigger Common (all models/firmware) or Individual (DPP only) TRG-OUT for trigger propagation Digital timing and trigger filters for pulse triggering (DPP only) 32 bit Time Stamp Daisy Chain (VME only) or one-to-many clock distribution Clock Cable delay compensation Sync start/stop through S-IN or GPI input or Trigger In/Out External Time Stamp reset up to 1024 acquisition buffers (2) Independent read/write access Ability to do on-line Digital Pulse Processing (DPP) for pulse shaping and height analysis, digital charge integration, gamma-neutron discrimination, timing, segmented detectors, etc USB (30MB/s), CONET (80MB/S), VME (60MB/s MBLT, 120MB/s 2eSST) Independent read/write access 16 programmable LVDS GPIOs (VME only) Analog Output for monitors, sum of the inputs, multiplicity, test waveform, etc (VME only) (1) The x in the model name is V1 for VME, VX1 for VME64X, DT5 for Desktop and N6 for NIM (2) Sampling frequency of the analog memory (switched capacitor array); A/D conversion takes place at lower speed (dead-time) (3) The memory size for the x742 is 128/1024 events of 1024 samples each (4) The indication size 1/ size 2 denotes different options (5) DPP-PHA: Pulse Height Analysis (Trapezoidal Filters), DPP-CI: Charge Integration (digital QDC), DPP-PSD: Pulse Shape Discrimination Short Form Catalog

3 DIGITIZERS Principles of Operation The basic operating mode of a digitizer is essentially the same as a digital oscilloscope: the analog signal, after an input stage of signal conditioning mainly used to adapt the dynamic range, is sampled by a flash ADC, whose output, i.e. the stream of digital samples, is continuously read by an FPGA and stored in a circular memory buffer of a programmable size. At the arrival of the trigger, the buffer is frozen and made available for the readout while the acquisition can continue in a new buffer. However, there are few important differences between a digitizer and a commercial digital oscilloscope: 1. The digitizers allow for dead-timeless acquisition. In fact, unlike most oscilloscopes, they have the ability to accept two consecutive triggers very close to each other (1) thanks to the multi buffer memory management: there is no dead time between an acquisition window and the next one. It is even possible to accept two trigger for which the acquisition windows overlap. The dead-timeless acquisition is a very important feature, especially in the case of events randomly distributed in time (in nuclear physics this is typically a Poissonian distribution), so that two of them, even at low rate, can occur at very short distance but you still want to capture both. (1) Except for 742 Series. 2. In the digitizers, all the channels are allowed to generate triggers independently. The individual trigger can be used locally by the channel that generated it (independent triggering) or can participate to the assertion of a global trigger for all the channels in the board, as well as to generate a pulse on the TRG-OUT. 3. The digitizers are designed for scalability. It is possible to synchronize several boards to make an acquisition system with a theoretically unlimited number of channels. Board synchronization consists of distributing a common clock reference on which all the ADC sampling clock are locked, aligning the acquisition time base of each board in order to have events with correlated time stamps, distributing the channel auto-triggers and the global triggers according to a programmable trigger logic in order to implement coincidences, neighbour triggering and other acquisition criteria and topologies. 4. The High bandwidth data readout links. Usually oscilloscopes do not have any communication channel (data is only displayed) or, if they have, most probably it has a fairly low bandwidth (GPIB, Ethernet, etc ); conversely, the digitizers are designed to provide high rate data transfer to a computer or an external data processing unit. CAEN digitizers have a minimum bandwidth of ~30MB/s in the case of the USB, about 80MB/s with CONET port up to more than 120MB/s for the VME with 2eSST. 5. On Line data processing. The acquisition in the digitizers is based on FPGAs. These are programmable devices with the ability to manage the ADC sample stream and implement on-line digital algorithms for signal processing. This feature is of fundamental importance for the implementation of systems that are not simply based on the acquisition, storage and readout of waveforms (raw data) but rather on the calculation of certain quantities of interest (e.g. the charge associated with a pulse, the pulse height, the leading edge, the baseline, the arrival time and other parameters) and the storage and transfer of just the final results, with clear advantages in terms of readout bandwidth. Dead-timeless acquisition Individual pulse self-trigger Multi-board synchronization for system scalability High bandwidth data readout links On-line data processing (FPGA or DSP) DPP CAEN Digitizer block diagram: The mother board defines the form-factor; it contains one FPGA for the readout interfaces and the services The daughter board defines the type of digitizer; it contains the input amplifiers, the ADCs, the FPGA for the data processing and the memories Digital Pulse Processing (DPP) for physics and biomedical applications In recent years, thanks to the availability on the market of faster and more precise ADC chips, applications in the field of nuclear physics (or related fields) have made large use of data acquisition systems based on digitizers. Compared to the traditional analog acquisition systems, in which the A/D conversion is performed at the end of the chain, the new systems have reversed that approach: the conversion to digital is performed as close as possible to the source of the signal (output of the detector or preamplifier). However, systems based on digitizers have a basic fundamental problem: the extremely huge amount of data to manage. As stated above, high trigger rate, multitude of channels and high readout bandwidth are the features that characterize the One single board can do the job of several analog modules digitizers when compared to the digital oscilloscope; at Full information preserved the same time, these features lead to large data streams. For this reason it is important to have an FPGA with the Reduction in size, cabling, power consumption and cost per channel ability to do on-line data processing and to extract from High reliability and reproducibility the raw samples sequence only the specific parameters necessary to the acquisition. Flexibility (different digital algorithms can be designed and loaded at any time into the same hardware) 20 Short Form Catalog 2012 More Technical Specifications available on

4 For this purpose, special algorithms can be applied to the digital samples coming from the ADC for the extraction of the quantities of interest and the reduction of the data; the relevant digital filters are, in most cases, very similar (at least from a functional point of view) to the old and familiar analog circuits, such as timing filters, shapers, CFDs, baseline restorers, etc.. DIGITIZERS The benefits of the digital approach are great stability and reproducibility, ability to reprogram and tailor the algorithms to the application, ability to preserve the information of the signal along the entire acquisition chain, better correction of unwanted effect such as baseline fluctuation, pile-up, ballistic deficit, etc All this in one board. To better understand the principles of operation of the DPP, let s take a practical example: suppose you have a detector for spectroscopy (scintillator and phototube) which generates pulses with a duration of about 100 ns. We can utilize an algorithm that permits you to extract the pulse charge on-line in the FPGA of the digitizer (i.e. continuously and in real time); to do this, we need to calculate the baseline by means of a moving average filter, detect the pulses when the signal exceeds a certain threshold respect to the baseline (trigger), 60 Co gamma spectrum acquired with a HPGe and DPP-PHA at University of Palermo. In the box, a least squares fit of the 1.33 MeV photopeak; a FWHM < 2 kev was obtained. implement a digital delay line in order to compensate the trigger latency and finally sum a certain number of samples within the integration gate after having subtracted the baseline from them. The charge thus obtained, together with a time stamp that identifies the position of the pulse, is the only information stored in memory for that event, resulting in a significant reduction of the data, such as 8 bytes per event, instead of saving the portion of the waveform that contains the pulse and a piece of baseline, which could consist of tens or hundreds of samples. 2D plot of Energy versus PSD using an AmBe source at 2 kcounts/s; the two lobes of the neutrons and gammas are well separated. The data were acquired at DukeUniversity (TUNL). CAEN is willing to collaborate with customers to create other types of firmware and algorithms for specific applications. In this example the algorithm replaces in digital form the same acquisition chain which traditionally consisted of a discriminator, a QDC and an analog delay line to fit the pulse within the gate coming from the discriminator. Other examples of algorithms implemented on CAEN s digitizer (generically called DPP, or Digital Pulse Processing) are those for (1) Pulse Height Analysis using trapezoidal filters, algorithms for the gamma-neutron discrimination realized by means of Pulse Shape Analysis, Zero suppression (removal of parts of signal that do not contain pertinent information), (2) Implementation of digital timing filter or digital constant fraction discriminator to determine precise timing information, (3) Mixed acquisition modes in which the quantities of interest calculated by the DPP (charge, height, etc...) are saved together with a short but significant chunk of waveform (e.g. the rising edge) to allow for off-line analysis, etc.. The digitizers are available with the standard version of the firmware that implement only the waveform acquisition mode (oscilloscope mode) or, in certain cases, some techniques of zero suppression. The firmware that implements a certain DPP algorithm is provided separately as an ordering option. The user can download any of this DPP from our Web site, install it on the digitizer that supports it and try it for free, with the only limitation that the acquisition may not last more than 30 minutes, after which you must perform a power-cycle (Time Bomb). Only after purchasing each Short Form Catalog

5 DIGITIZERS firmware and its relevant license (that is installed on the card in the form of electronic key) the time bomb will be eliminated. The table below shows all types of DPP and the relevant digitizers that support them. For more detailed information on the DPP algorithms and firmware, please refer to the White Paper WP2081. Name Model Detectors (typ.) Notes DPP-PHA x724 Hi res. SI, Ge Digital Pulse Processing for Pulse Height Analysis DPP-CI x720 PMT, SiPM Digital Pulse Processing for Charge Integration DPP-PSD x720, x751 Organic liquid Digital Pulse Processing for Pulse Shape Discrimination NEW Trigger and synchronization in multi-board systems In most cases, the applications that require the use of several channels, need to synchronize the acquisition across different digitizers, this is performed according to the following points: 1. Distribution of a common clock reference in order to have the same sampling clock on all the ADC channels. CAEN s digitizers feature a programmable PLL able to generate the sampling clocks locked to an external clock input (usually at lower frequency) whose distribution can be done in parallel from a common source, using a fan-out, as well as through an in-out daisy chain with the ability to use the first board as a clock master and to compensate for delays in the cables by means of a programmable phase shift. The daisy-chain mode is available only in the VME models. 2. Alignment of the time stamp associated with the triggers to allow off-line reconstruction of the events read from different boards. This can be done by using a dedicated SYNC input as well as through the TRG-IN, TRG-OUT daisy chain by issuing a first pulse acting as a start of acquisition; this pulse doesn t trigger the channels. After that, the TRG-IN and TRG-OUT start their normal operating mode that is to receive and send triggers. 3. Distribution of the triggers from channel to channel and from board to board, according to a certain trigger logic. Each card has different sources of trigger: external TRG-IN from the front panel, software trigger and channel self-triggers. All these triggers can be combined in order to make coincidences, majorities, global triggers and other functions. It is worth noticing that the DPP firmware, compared to the standard version, gives important advantages also in terms of trigger managing: first of all, the digital filters are able to detect the input pulses and generate triggers even in the presence of noise, baseline fluctuation and pile-up that make inefficient the simple trigger mechanism based on a fixed threshold. Furthermore, with the DPP, the channels operate independently and it is possible to implement the trigger propagation on a channel to channel basis, also including channels on different boards. This option is particularly useful in the segmented detectors where the detection of one pulse in a certain segment requires the acquisition of the signals also in the neighbour segments in order to calculate the exact position in which the particle hit. Software CAEN provides drivers for all the different types of physical communication channels (USB 2.0 or the proprietary CONET Optical Link, managed by the A2818 PCI card or A3818 PCIe cards or the VME bus accessed by the V1718 and V2718 bridges), a set of C and LabView libraries, demo applications and utilities. Windows and Linux are both supported. More specifically, the available software is the following: CAENComm library Contains the basic functions for access to hardware; the aim of this library is to provide a unique interface to the higher layers regardless the type of physical communication channel. Note: for VME access, CAENcomm is based on CAEN s VME bridges V1718 (USB to VME) and V2718 (PCI to VME). In the case of third-part bridges or SBCs, the user must provide the functions contained in the CAENcomm library for to the relevant platform. CAENDigitizer library Contains the functions to program the digitizers, manage the acquisition, execute the readout, unpack the data, send triggers, etc... WaveDump It s a Console application that lets you program the digitizer (according to a text configuration file that contains a list of parameters and instructions), to start the acquisition, read the data, display the readout and trigger rate, apply some post processing (such as FFT and amplitude histogram), save data to a file and also plot the waveforms using the external plotting tool gnuplot that is available on internet for free. This program is quite basic and has no graphics but it is an excellent example of C code that demonstrates the use of libraries and methods for an efficient readout and data analysis. It is strongly recommended, to any user willing to write the SW on their own to start with this demo and modify it according to his or her needs. For more details please see the WaveDump User Manual (UM2091) and Quick Start Guide (GD2084 ). 22 Short Form Catalog 2012 More Technical Specifications available on

6 CAENScope It s a fully graphical program that implements a simple oscilloscope: you can see the waveforms, set the trigger thresholds, change the scales of time and amplitude, perform simple mathematical operations between the channels, save data to file and other operations. CAENscope is provided as an executable file; the source codes are not distributed. DIGITIZERS NOTE: CAENScope does not work with digitizers running DPP firmware. For more details please see the CAENScope Quick Start Guide GD2484. CAENUpgrader It s a tool that allows the user to update the firmware of the digitizers, change the PLL settings (i.e. set the ADC sampling frequency, enable the clock output, etc...), load, when requested, the license for the pay firmware (for example, the DPP-CI, DPP-PHA and DPP-PSD) and other utilities. For more details please see the CAENUpgrader Quick Start Guide GD2512. DPP Control Software It s an application that manages the acquisition in the digitizers which have DPP firmware installed on it. The program consist of different parts: there is a GUI whose purpose is to set all the parameters for the DPP and for the acquisition; the GUI generates a textual configuration file that contains all the parameters. This file is read by the Acquisition Engine, which is a C console application that programs the digitizer according to the parameters, starts the acquisition and manage the data readout. The data, that can be waveforms, time stamps, energies or other quantities of interest, can be saved to output files or plotted using gnuplot as an external plotting tool, exactly like in WaveDump. Name Software Notes DPP-PHA DPP-PHA Control Software works only with x724 models and DPP-PHA DPP-CI DPP-CI Control Software works only with x720 models and DPP-CI DPP-PSD DPP-PSD Control Software works only with x720 OR X751 models and DPP-PSD Application The great versatility of the DPP algorithms allowed CAEN to develop a new product dedicated to the gamma spectrometry, the DT5780 Digital MCA. This module is a compact, stand-alone digital solution for Pulse Height Analysis based on DPP-PHA firmware. It houses a two-channel, 14-bit, 100 MS / s digitizer (see Model DT5724A), two HV channels able to supply a bias voltage up to + -5 kv, 300 µa and two connectors for the power supply of preamplifiers and detector temperature readout. For more information about DT5780, please refer to page 29. Short Form Catalog

7 DIGITIZERS Model Ordering Code Description Single Ended / Differential Input SRAM Memory Sample/ch AMC FPGA (*) X724 WDT5724XAAAA DT Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C4, SE SE 512 k EP1C4 Desktop WDT5724AXAAA DT5724A - 2 Ch. 14 bit 100 MS/s Digitizer: 512kS/c h, C4, SE SE 512 k EP1C4 Desktop WN6724XAAAAA N Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C4, SE SE 512 k EP1C4 NIM WN6724AXAAAA N6724A - 2 Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C4, SE SE 512 k EP1C4 NIM WV1724XAAAAA V Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C4, SE SE 512 k EP1C4 6U-VME64 WV1724BXAAAA V1724B - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C4, SE SE 4 M EP1C4 6U-VME64 WV1724CXAAAA V1724C - 8 Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C4, DIFF DIFF 512 k EP1C4 6U-VME64 WV1724DXAAAA V1724D - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C4, DIFF DIFF 4 M EP1C4 6U-VME64 WV1724EXAAAA V1724E - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C20, SE SE 4 M EP1C20 6U-VME64 WV1724FXAAAA V1724F - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C20, DIFF DIFF 4 M EP1C20 6U-VME64 WV1724GXAAAA V1724G - 8 Ch. 14 bit 100 MS/s Digitizer: 512KS/ch, C20, SE SE 512 k EP1C20 6U-VME64 WVX1724XAAAA VX Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C4, SE SE 512 k EP1C4 6U-VME64X WVX1724BXAAA VX1724B - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C4, SE SE 4 M EP1C4 6U-VME64X WVX1724CXAAA VX1724C - 8 Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C4, DIFF DIFF 512 k EP1C4 6U-VME64X WVX1724DXAAA VX1724D - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C4, DIFF DIFF 4 M EP1C4 6U-VME64X WVX1724EXAAA VX1724E - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C20, SE SE 4 M EP1C20 6U-VME64X WVX1724FXAAA VX1724F - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C20, DIFF DIFF 4 M EP1C20 6U-VME64X X720 WDT5720XAAAA DT Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C4, SE SE 1.25 M EP1C4 Desktop WDT5720AXAAA DT5720A - 2 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ ch, C4, SE SE 1.25M EP1C4 Desktop WDT5720BXAAA DT5720B - 4 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C20, SE SE 1.25 M EP1C20 Desktop WDT5720CXAAA DT5720C - 2 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C20, SE SE 1.25 M EP1C20 Desktop WN6720XAAAAA N Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C4, SE SE 1.25 M EP1C4 NIM WN6720AXAAAA N6720A - 2 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/c h, C4, SE SE 1.25M EP1C4 NIM WN6720BXAAAA N6720B - 4 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C20, SE SE 1.25 M EP1C20 NIM WN6720CXAAAA N6720C - 2 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C20, SE SE 1.25 M EP1C20 NIM WV1720XAAAAA V Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C4, SE SE 1.25 M EP1C4 6U-VME64 WV1720BXAAAA V1720B - 8 Ch. 12 bit 250 MS/s Digitizer: 10MS/ch, C4, SE SE 10 M EP1C4 6U-VME64 WV1720CXAAAA V1720C - 8 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C4, DIFF DIFF 1.25 M EP1C4 6U-VME64 WV1720DXAAAA V1720D - 8 Ch. 12 bit 250 MS/s Digitizer: 10MS/ch, C4, DIFF DIFF 10 M EP1C4 6U-VME64 WV1720EXAAAA V1720E - 8 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C20, SE SE 1.25 M EP1C20 6U-VME64 WV1720FXAAAA V1720F - 8 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C20, DIFF DIFF 1.25 M EP1C20 6U-VME64 WVX1720XAAAA VX Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C4, SE SE 1.25 M EP1C4 6U-VME64X WVX1720BXAAA VX1720B - 8 Ch. 12 bit 250 MS/s Digitizer: 10MS/ch, C4, SE SE 10 M EP1C4 6U-VME64X WVX1720CXAAA VX1720C - 8 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C4, DIFF DIFF 1.25 M EP1C4 6U-VME64X WVX1720DXAAA VX1720D - 8 Ch. 12 bit 250 MS/s Digitizer: 10MS/ch, C4, DIFF DIFF 10 M EP1C4 6U-VME64X WVX1720EXAAA VX1720E - 8 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C20, SE SE 1.25 M EP1C20 6U-VME64X WVX1720FXAAA VX1720F - 8 Ch. 12 bit 250 MS/s Digitizer: 1.25MS /ch, C20, DIFF DIFF 1.25 M EP1C20 6U-VME64X X721 WV1721BXAAAA WV1721XAAAAA V Ch. 8 bit 500 MS/s Digitizer: 2MS/ch, C4, SE SE 2 M EP1C4 6U-VME64 WV1721XAAAAA WV1721BXAAAA V1721B - 8 Ch. 8 bit 500 MS/s Digitizer: 2MS/ch, C4, DIFF DIFF 2 M EP1C4 6U-VME64 WVX1721XAAAA WVX1721XAAAA VX Ch. 8 bit 500 MS/s Digitizer: 2MS/ch, C4, SE SE 2 M EP1C4 6U-VME64X WVX1721BXAAA WVX1721BXAAA VX1721B - 8 Ch. 8 bit 500 MS/s Digitizer: 2MS/ch, C4, DIFF DIFF 2 M EP1C4 6U-VME64X X730 WDT5730AXAAA WDT5730XAAAA DT Ch. 12 bit 500 MS/s Digitizer: 1.25MS/ch, EP3C16, SE COMING SOON SE 1.25 M EP3C16 Desktop WDT5730XAAAA WDT5730AXAAA DT5730A - 2 Ch. 12 bit 500 MS/s Digitizer: 1.25MS/ch, EP3C16, SE COMING SOON SE 1.25 M EP3C16 Desktop WN6730AXAAAA WN6730XAAAAA N Ch. 12 bit 500 MS/s Digitizer: 1.25MS/ch, EP3C16, SE COMING SOON SE 1.25 M EP3C16 NIM WN6730XAAAAA WN6730AXAAAA N6730A - 2 Ch. 12 bit 500 MS/s Digitizer: 1.25MS/ch, EP3C16, SE COMING SOON SE 1.25 M EP3C16 NIM WV1730BXAAAA WV1730XAAAAA V Ch. 12 bit 500 MS/s Digitizer: 1.25MS/ch, EP3C16, SE COMING SOON SE 1.25 M EP3C16 6U-VME64 WV1730XAAAAA WV1730BXAAAA V1730B - 8 Ch. 12 bit 500 MS/s Digitizer: 10MS/ch, EP3C16, SE COMING SOON SE 10 M EP3C16 6U-VME64 WVX1730BXAAA WVX1730XAAAA VX Ch. 12 bit 500 MS/s Digitizer: 1.25MS/ch, EP3C16, SE COMING SOON SE 1.25 M EP3C16 6U-VME64X WVX1730XAAAA WVX1730BXAAA VX1730B - 8 Ch. 12 bit 500 MS/s Digitizer: 10MS/ch, EP3C16, SE COMING SOON SE 10 M EP3C16 6U-VME64X X731 WV1731XAAAAA V1731-4/8 Ch. 8 bit 1000/500 MS/s Digitizer: 4/2MS/ch, C4, SE SE 2/4 M EP1C4 6U-VME64 WV1731BXAAAA V1731B - 4/8 Ch. 8 bit 1000/500 MS/s Digitizer: 4/2MS/ch, C4, DIFF DIFF 2/4 M EP1C4 6U-VME64 WVX1731XAAAA VX1731-4/8 Ch. 8 bit 1000/500 MS/s Digitizer: 4/2MS/ch, C4, SE SE 2/4 M EP1C4 6U-VME64X WVX1731BXAAA VX1731B - 4/8 Ch. 8 bit 1000/500 MS/s Digitizer: 4/2MS/ch, C4, DIFF DIFF 2/4 M EP1C4 6U-VME64X X740 WDT5740XAAAA DT Ch. 12 bit 62.5 MS/s Digitizer: 192kS/ch, EP3C16, SE SE 192 k EP3C16 Desktop WDT5740CXAAA DT5740C - 10Vpp 32 Ch. 12 bit 62.5 MS/s Digitizer: 192kS/ch, EP3C16, SE SE 192 k EP3C16 Desktop WN6740XAAAAA N Ch. 12 bit 62.5 MS/s Digitizer: 192kS/ch, EP3C16, SE SE 192 k EP3C16 NIM WN6740CXAAAA N6740C - 10Vpp 32 Ch. 12 bit 62.5 MS/s Digitizer: 192kS/ch, EP3C16, SE SE 192 k EP3C16 NIM WV1740XAAAAA V Ch. 12 bit 62.5 MS/s Digitizer: 192kS/ch, EP3C16, SE SE 192 k EP3C16 6U-VME64 WV1740AXAAAA V1740A - 10Vpp input 64ch 12bit 62.5MS/s Digitizer: 1.5 MS/ch, EP3C16, SE SE 1.5 M EP3C16 6U-VME64 WV1740BXAAAA V1740B - 64 Ch. 12 bit 62.5 MS/s Digitizer: 1.5 MS/ch, EP3C16, SE SE 1.5 M EP3C16 6U-VME64 WV1740CXAAAA V1740C - 10Vpp input 64ch 12bit 62.5MS/s Digitizer: 192kS/ch, EP3C16, SE SE 192 k EP3C16 6U-VME64 WVX1740XAAAA VX Ch. 12 bit 62.5 MS/s Digitizer: 192kS/ch, EP3C16, SE SE 192 k EP3C16 6U-VME64X WVX1740AXAAA VX1740A - 10Vppm 64 Ch. 12 bit 62.5 MS/s Digitizer: 1.5 MS/ch, EP3C16, SE SE 1.5 M EP3C16 6U-VME64X WVX1740BXAAA VX1740B - 64 Ch. 12 bit 62.5 MS/s Digitizer: 1.5 MS/ch, EP3C16, SE SE 1.5 M EP3C16 6U-VME64X WVX1740CXAAA VX1740C - 10Vppm 64 Ch. 12 bit 62.5 MS/s Digitizer: 192 KS/ch, EP3C16, SE SE 192 k EP3C16 6U-VME64X (*) AMC: ADC & Memory controller FPGA. ALTERA models available: EP1C4: Cyclone (4.000 LEs), EP1C20: Cyclone ( LEs), EP3C16: Cyclone III ( LEs). Form factor 24 Short Form Catalog 2012 More Technical Specifications available on

8 Model Ordering Code Description Single Ended / Differential Input SRAM Memory Sample/ch AMC FPGA (*) X761 WDT5761XAAAA DT5761-1Ch.10 bit 4 GS/s Digitizer: 7.2MS/ch, EP3C16, SE NEW SE 7.2 M EP3C16 Desktop WN6761XAAAAA N Ch. 10 bit 4 GS/s Digitizer: 7.2Ms/ch, EP3C16, SE NEW SE 7.2 M EP3C16 NIM WV1761XAAAAA V1761-2Ch.10 bit 4 GS/s Digitizer: 7.2MS/ch, EP3C16, SE NEW SE 7.2 M EP3C16 6U-VME64 WV1761BXAAAA V1761B - 2Ch.10 bit 4 GS/s Digitizer: 7.2MS/ch, EP3C16, DIFF NEW DIFF 7.2 M EP3C16 6U-VME64 WV1761CXAAAA V1761C - 2 Ch. 10 bit 4 GS/s Digitizer: 57.6MS/ch, EP3C16, SE NEW SE 57.6 M EP3C16 6U-VME64 WVX1761CXAAA VX1761-2Ch.10 bit 4 GS/s Digitizer: 7.2MS/ch, EP3C16, SE NEW SE 7.2 M EP3C16 6U-VME64X WVX1761BXAAA VX1761B - 2Ch.10 bit 4 GS/s Digitizer: 7.2MS/ch, EP3C16, DIFF NEW DIFF 7.2 M EP3C16 6U-VME64X WVX1761CXAAA VX1761C - 2 Ch. 10 bit 4 GS/s Digitizer: 57.6MS/ch, EP3C16, SE NEW SE 57.6 M EP3C16 6U-VME64X X751 WDT5751XAAAA DT5751-2/4 Ch. 10 bit 2/1 GS/s Digitizer: 1.8/3.6MS/ch, EP3C16, SE SE 1.8/3.6 M EP3C16 Desktop WN6751XAAAAA N6751-2/4 Ch. 10 bit 2/1 GS/s Digitizer: 1.8/3.6MS/ch, EP3C16, SE SE 1.8/3.6 M EP3C16 NIM WV1751XAAAAA V1751-4/8 Ch. 10 bit 2/1 GS/s Digitizer: 1.8/3.6MS/ch, EP3C16, SE SE 1.8/3.6 M EP3C16 6U-VME64 WV1751BXAAAA V1751B - 4/8 Ch. 10 bit 2/1 GS/s Digitizer: 1.8/3.6MS/ch, EP3C16, DIFF DIFF 1.8/3.6 M EP3C16 6U-VME64 WV1751CXAAAA V1751C - 4/8 Ch. 10 bit 2/1 GS/s Digitizer: 14.4/2 8.8MS/ch, EP3C16, SE SE 14.4/28.8M EP3C16 6U-VME64 WVX1751XAAAA VX1751-4/8 Ch. 10 bit 2/1 GS/s Digitizer: 1.8/3.6MS/ch, EP3C16, SE SE 1.8/3.6 M EP3C16 6U-VME64X WVX1751BXAAA VX1751B - 4/8 Ch. 10 bit 2/1 GS/s Digitizer: 1.8/3.6MS/ch, EP3C16, DIFF DIFF 1.8/3.6 M EP3C16 6U-VME64X WVX1751CXAAA VX1751C - 4/8 Ch. 10 bit 2/1 GS/s Digitizer: 14.4/ 28.8MS/ch, EP3C16, SE SE 14.4/28.8M EP3C16 6U-VME64X X742 WDT5742XAAAA DT Ch. 12 bit 5 GS/s Switched-Capacitor Digitizer: 128kS/ch, EP3C16, SE SE 128 k EP3C16 Desktop WDT5742BXAAA DT5742B Ch. 12 bit 5 GS/s Switched-Capacito r Digitizer: 1024 events/ch (1kS/event), EP3C16, SE SE 1 M EP3C16 Desktop WN6742XAAAAA N Ch. 12 bit 5 GS/s Switched-Capacitor Digitizer: 128kS/ch, EP3C16, SE SE 128 k EP3C16 NIM WN6742BXAAAA N6742B Ch. 12 bit 5 GS/s Switched-Capacitor Digitizer: 1024 events/ch (1kS/event), EP3C16, SE SE 1 M EP3C16 NIM WV1742XAAAAA V Ch. 12 bit 5 GS/s Switched-Capacitor Digitizer: 128kS/ch, EP3C16, SE SE 128 k EP3C16 6U-VME64 WV1742BXAAAA V1742B Ch. 12 bit 5 GS/s Switched-Capacitor Digitizer: 1024 events/ch (1kS/events), EP3C16, SE SE 1 M EP3C16 6U-VME64 WVX1742XAAAA VX Ch. 12 bit 5 GS/s Switched-Capacitor Digitizer: 128kS/ch, EP3C16, SE SE 128 k EP3C16 6U-VME64X (*) AMC: ADC & Memory controller FPGA. ALTERA models available: EP1C4: Cyclone (4.000 LEs), EP1C20: Cyclone ( LEs), EP3C16: Cyclone III ( LEs). WVX1742BXAAA VX1742B Ch. 12 bit 5GS/s Switched-Capacitor Digitizer: 1024 events/ch (1kS/event), EP3C16, SE SE 1 M EP3C16 6U-VME64X (*) AMC: ADC & Memory controller FPGA. ALTERA models available: EP1C4: Cyclone (4.000 LEs), EP1C20: Cyclone ( LEs), EP3C16: Cyclone III ( LEs). Form factor DIGITIZERS Accessories Ordering Information Code Description WA2818XAAAAA A PCI Optical Link Controller WA3818AXAAAA A PCIe 1 Optical Link WA3818BXAAAA A PCIe 2 Optical Link WA3818CXAAAA A PCIe 4 Optical Link WAI2703XAAAA AI Optical Fibre 30cm. simplex WAI2705XAAAA AI Optical Fibre 5 m. simplex WAI2720XAAAA AI Optical Fibre 20 m. simplex WAI2730XAAAA AI Optical Fibre 30 m. simplex WAI2740XAAAA AI Optical Fibre 40 m. simplex WAY2705XAAAA AY Optical Fibre 5 m. duplex WAY2720XAAAA AY Optical Fibre 20 m. duplex WAY2730XAAAA AY Optical Fibre 30 m. duplex WA654XAAAAAA A654 - Single Channel MCX to LEMO Cable Adapter WA654K4AAAAA A654 KIT4-4 MCX TO LEMO Cable Adapter WA654K8AAAAA A654 KIT8-8 MCX TO LEMO Cable Adapter WA659XAAAAAA A659 - Single Channel MCX to BNC Cable Adapter WA659K4AAAAA A659 KIT4-4 MCX TO BNC Cable Adapter WA659K8AAAAA A659 KIT8-8 MCX TO BNC Cable Adapter WA746BXAAAAA A746B - 64Ch.Adapter for LEMO connector WA746DXAAAAA A746D - 32 Ch.Adapter for Lemo connector WA746EXAAAAA A746E - 32 Ch. Adapter for Lemo connector Customizations Code WPERS WPERS WPERS Description V1724 Customization - 10Vpp Input Range, SE V1724 Customization - 500mVpp Input Range, SE V1751 Customization - 10Vpp Input Range Short Form Catalog