Accelerator Spectrum

Transcription

1 Active/HardBD Panel Mohammad Sadoghi, Purdue University Sebastian Breß, German Research Center for Artificial Intelligence Vassilis J. Tsotras, University of California Riverside

2 Accelerator Spectrum Commodity Hardware Multi- Threading Intel Hyper-threading Single-Instruction Multiple Data (SIMD) Oracle SPARC DAX, AltiVec,SSE,AVX Graphics Processing Unit (GPU) Discrete & Integrated GPUs (Nvidia,AMD,Intel) Field Programmable Gate Array (FPGA) Xilinx and Altera FPGAs Application Specific Integrated Chip (ASIC) SPARC M7 Microprocessor Specialization

3 Hardware Acceleration Landscape System Model Host FPGA/ASIC FPGA/ASIC Host CPU FPGA/ASIC/GPU Standalone Co-placement Co-processor Procedural Languages Declarative Languages General Purpose Languages XML Filtering (C, C++, Java) (SQL-based) Hardware Description Languages Parallel Programming Static Compiler (VHDL, Verilog, SystemC, TLM) Languages & Parallel APIs (Glacier) Dynamic Compiler Programming Model (CUDA, OpenCL, OpenMP) FlexTrack (FQP) Host CPU Bump-in-the-wire Active Path Parametrized Circuits (Skeleton Automata, fpga- ToPSS, OPB, FQP, Ibex, IBM Netezza) Representational Model Temporal/Spatial Instructions (Q100) Parametrized Data Segments (FQP) Parametrized Topology (FQP) Static Circuits Bi-directional Flow Uni-directional Flow Boolean Formula (Handshake Join) (SplitJoin) Precomputation Indexing (Ibex) (Propagation) Multi-query Optimization Pipeline Parallelism (Rete-like Network) Algorithmic Model Data Parallelism Task Parallelism Hardware Acceleration Landscape for Distributed Real-time Analytics: Virtues and Limitations, ICDCS 17

4 Heterogeneous Hardware Virtualization Standalone Co-processor Co-placement Hardware Acceleration Landscape for Distributed Real-time Analytics: Virtues and Limitations, ICDCS 17

5 Software-Hardware Life-cycle for Modern Accelerators Moore s Law Limit Heterogeneous Architecture? Homogeneity? (abstraction)

6 Software-Hardware Life-cycle for Modern Accelerators Moore s Law Limit FPGA Software ASIC Heterogeneous Architecture? GPU Homogeneity? (abstraction)

7 Software-Hardware Life-cycle for Modern Accelerators Software FPGA ASIC Abstraction? Programming Models? Programming Executions? Logical/Physical Independence? Virtualization? GPU

8 Software-Hardware Life-cycle for Modern Accelerators Software FPGA GPU ASIC Abstraction? Programming Models? Programming Executions? Logical/Physical Independence? Virtualization? Compiler? Optimizer? Co-processor Optimization? Code Generation? Spatial vs. Temporal Sharing/Scheduling?

9 References Andrew Putnam, "The Configurable Cloud -- Accelerating Hyperscale Datacenter Services with FPGAs Xiaodong Zhang, "Enabling Effective Utilization of GPUs for Data Mamagement Systems" Stratis D. Viglas, "Processing declarative queries through generating imperative code in managed runtimes Bingsheng He, "Data Management Systems on Future Hardware: Challenges and Opportunities Jianting Zhang and Le Gruenwald, "Parallel Selectivity Estimation for Optimizing Multidimensional Spatial Join Processing on GPUs Marcus Pinnecke, David Broneske, Gabriel Campero Durand and Gunter Saake, "Are Databases Fit for Hybrid Workloads on GPUs? A Storage Engine s Perspective Roger Moussalli, "Tradeoffs and Considerations in the Design of Accelerators for Database Applications" Eva Sitaridi, "Hardware Acceleration of Database Analytics"