Distributed systems: paradigms and models Motivations

Transcription

1 Distributed systems: paradigms and models Motivations Prof. Marco Danelutto Dept. Computer Science University of Pisa Master Degree (Laurea Magistrale) in Computer Science and Networking Academic Year

2 Contents Hardware motivations CPU evolution HPC Clouds Software motivations innovative paradigms can be moved to different frameworks 2

3 Moore s law Moore's original statement can be found in his publication "Cramming more components onto integrated circuits", Electronics Magazine 19 April 1965: The complexity for minimum component costs has increased at a rate of roughly a factor of two per year... Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer. 3

4 Moore s law evolution Transistors/gates doubling every 2 years more and more powerful single processor systems Cores doubling every two years simpler cores more complex (?) memory hierarchy more complex interconnection structure 4

5 Why? doubling core exploits existing technology (and trends) keeping reasonable power consumption doubling the frequency of a single core chip costs much more than putting two simpler cores on the same chip Perf = Freq x IPC Power = DynamicCapacitance x Volt x Volt x Freq ( 5

6 Commodity processors 6

7 Intel perspective 7

8 Intel perspective (2) 8

9 Commodity processors: non Intel 9

10 Commodity processors: niche products 10

11 Research processors: Intel 80 cores 11

12 More in detail... 4Ghz chip with mesh (logical and physical) 10x8 core FP, 1,28 TFlops Tile: router: addesses each core on chip, implements the mesh VLIW processor (96 bit x instruction, up to 8 ops per cycle), in-order-execution, 32 registers (6Read/4Write), 2K Data, 3K Instruction cache, 2 FPU (9 stages, 2FLOPs/cycle sustained), Cicli: FPU:9, Ld/St:2, Snd/ Rcv:2, Jmp/Br:1 12

13 IBM WireSpeed 13

14 WireSpeed (PowerEn) Multicore 16 Power PC cores Etherogeneous I/O XML, RegExp, Compress, Crypto coprocessors share logical address space (through MMU) integrated I/O 14

15 WireSpeed: accelerators! 15

16 WireSpeed: suggested uses 16

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22 GPUs / FPGAs 21

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27 Intel Larrabee 26

28 Not only processors: FPGAs q1_embedded_xilinx.htm&usg= PXXvIQmng-24QwOWFUFfFuf1lS4=&h=380&w=650&sz=71&hl=en&start=6&um=1&tbnid=LaX1pZKYodDqSM:&tbnh=80&tbnw=137&prev=/images%3Fq%3Dprocessor %2Bevolution%26hl%3Den%26client%3Dsafari%26rls%3Den%26sa%3DN%26um%3D1 27

29 Not only processors: FPGAs q1_embedded_xilinx.htm&usg= PXXvIQmng-24QwOWFUFfFuf1lS4=&h=380&w=650&sz=71&hl=en&start=6&um=1&tbnid=LaX1pZKYodDqSM:&tbnh=80&tbnw=137&prev=/images%3Fq%3Dprocessor %2Bevolution%26hl%3Den%26client%3Dsafari%26rls%3Den%26sa%3DN%26um%3D1 27

30 Consequence: programming model Heterogeneous computing coming to the scene more and more adaptivity required in the code more and more special purpose solutions needed (transparent to the user) 28

31 Energy concerns/tradeoffs

32 Energy concerns/tradeoff 30

33 Consequence: programming model Faster single core systems faster dusty deck code Multi-many core require parallel / distributed code UMA! NUMA 31

34 But... Amdhal law is still there serial fraction = f (% of code not parallelizable) p processors available to parallelize the non serial fraction (1-f) Speedup(p) = Ts / (f Ts + (1-f) (Ts / p)) = 1 / (f + (1-f)/p) asymptotically (when p increases): Speedup(p) = 1 / f 32

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