Asynchronous Elastic Dataflows by Leveraging Clocked EDA
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1 Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA Mahdi Jelodari Mamaghani, Jim Garside, Will Toms, & Doug Edwards Verona, Italy 29 th August 2014
2 Motivation: Automatic GALSification of Control-driven Systems Partitioning a control-driven system at behavioural level is complicated Detecting signal correspondence between data and control path is error prone Presence of global control impedes the detection process [1,2] Balsa, Petrify, VeriSyn& AVS : Popular Control-driven synthesis tools GCD a data-dependent loop example: [GCD Control Path] [GCD Data Path]
3 Motivation: Automatic GALSification of Data-driven Systems Concurrent dataflow Specification of a System Fine-grained Dataflow Synthesis Automatically Partitioning the System into multiple clocked islands 3
4 Teak: Asynchronous Dataflow Backend for Balsa Language Released in 2010 as a Dataflow Syntax-directed Synthesis backend for Balsa language [ACSD 09]. Some of the properties of Teak Dataflow Networks (TDNs): Communication: Point-to-point communication between computation blocks. Slack elastic channels are capable of storing any number of tokens. Computational : Macro-modulestyle with separate Goand Done activation signals. These modules are chained in sequence or parallel according to the source level directives. Dataflow which realises data-dependent computation. 4
5 Teak: Behavioural Synthesis Flow Syntax Directed 5
6 Teak Model of Computation: Macro-modules Single-Input, Single-Output Macro-modules Connected by buffers Control and Data move along through Macro-modules Teak uses three hierarchical primitives to form a dataflow Network Sequential SteerMerge Iterative 6
7 Protocol: Conventional Synchronous vs. Elastic Timing alignment by inserting buffers in postsynthesis stage [Synchronous] In Conventional Sync. Systems Latency = 0 System tolerates variations in latencies through handshaking [Asynchronous] In Elastic Systems Latency can vary A common timing discipline is introduced to the handshake system [Synchronous Elastic] In Sync. Elastic Systems Latency is discretised by clock 7
8 A Common Timing Discipline for Asynchronous Dataflow Networks of Teak Synchronous Elastic* protocol is incorporated in Teak flow as a common timing discipline: Deterministic behaviour (bounded delays) Simplified deadlock issue in the network Smaller circuit area (~4 times) Still Preserves slack elasticity (any storage on links) Improved power utility (clock gating + simple handshake) SDF *Synchronous Elastic Flow (SELF) [3] Kahn Process Networks [Deterministic] CSP Networks [non-deterministic] 8
9 Correctness in Asynchronous dataflow networks of Teak Variables in dataflow networks: single write/multiple read Variable provides a place for data tokens, so >2 latches to ensure deadlock freedom 9
10 Correctness in SELF Adapted Networks Variables in eteak: Elastic Controllers with a pair of latches operating at opposite clock phases Operations : write takes 1 cycle and read take 0 cycles Each variable provides twoplaces for data tokens Loops with write/read operations do not need extra latches 10
11 Synchronous Crystallisation and Re-synthesis Synchronous Crystallisation: Regional transformation of a dataflow into a synchronous control-driven circuit through re-synthesis The candidates for Crystallisation are selected based on their physical characteristics (e.g. critical path) Synthesis at system level enables us to rapidly explore different trade-offs between power, performance and area 11
12 Crystallisation: Through RTL Transformation By extracting the occurrence graph and detecting concurrent dataflowswithin the Teak Network What we achieve by this transformation: Locally synchronous deterministic behaviour reduced fine-grained communication overhead Easier modelling and partitioning towards GALSification Use the power of Clocked EDA to re-synthesise Pipelined structures better Throughput 12
13 Elastic to RTL Transformation: The Algorithm A Root B Case A When Root is a Fork and MM1 / MM2 are independent: φ1 MM1 MM2 φ2 (posedge CLK) : FSM_A1 Out _1 <= φ1 (A,B) (posedge CLK) : FSM_A2 Out_2 <= φ2 (A,B) assign Out = Join (Out_1, Out_2) Sink Out 13
14 Elastic to RTL Transformation: The Algorithm A Root B Case B When Root is a Fork and MM1 / MM2 are dependent: MM1 MM2 (posedgeclk) : FSM_B State1: Out_temp <= φ1 (A, B) State2: Out_2 <= φ2 (A, B, Out_temp) φ1 φ2 assign Out = Out_2 Sink Out 14
15 Elastic to RTL Transformation: The Algorithm A Root B Case C When Root is a Splitter/Steer: MM1 φ1 MM2 φ2 FSM_C State_Root: Case (A,B) 1: State1 2: State2 State1: Out_1 <= φ1 (A, B) State2: Out_2 <= φ2 (A, B) Sink Out assign Out = Merge (Out_1, Out_2) 15
16 RTL Transformation for the Shifter Example In this example within Macro-modules Root is a Splitter (Case C) whilst Macro-modules are dependent (Case B), therefore the whole structure is transformed to a single FSM 16
17 eteaksnapshot: Visual Crystallised Partitions 17
18 Async. vs. Sync. Elastic: Area Cost Case Study: SSEM, A three stage iterative Processor implemented in Balsa Deadlock-free design: Async. (65 Buffers) vs. Sync. Elastic (6 Buffers) The slack elastic property is preserved Asynchronous Synchronous Elastic Area Cost F-J-M-S Variables Subtracter Latch
19 Asynchronous vs. Synchronous Elastic SSEM Application: GCD (67, 2) : 250 Instructions Slack Matching can potentially improve the performance by a factor of Asynchronous vs. Synchronous Elastic SSEM Area /Throughput 20 0 Asynchronous* Synchronous Elastic* (f = GHz ) Asynchronous *Fully buffered to approve the slack elastic property Synchronous Elastic (f = 435 MHz) Solid Synchronous (f = 1.1GHz) Total Cell Area (k*mm^2) Exec. Time (10*ms)
20 Summary & Future work Summary: A framework for exploring GALSification: an extension to the Teak EDA flow which provides a framework for exploring GALSification techniques and Behavioural partitioning A re-synthesis mechanism to exploit synchronous EDA: exploiting the synchronous elastic protocol to move from the asynchronous domain to the synchronous domain where it is possible to leverage synchronous EDAs to improve the circuits Future Work: Automatic partitioning the system into multiple clock domains: Running the re-synthesised structures with different clock frequency based on their behaviour is what we pursue as future work 20
21 References [1]. Wei Song,Jim D. Garside,Doug Edwards: Automatic data path extraction in large-scale register-transfer level designs.iscas 2014: [2]. Wei Song,Jim D. Garside: Automatic Controller Detection for Large Scale RTL Designs. DSD 2013: [3]. Cortadella, Jordi, Mike Kishinevsky, and Bill Grundmann. "SELF: Specification and design of a synchronous elastic architecture for DSM systems."tau 2006: Handouts of the International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems
22 Youtube: eteak- A Synchronous Elastic Dataflow Synthesiser Thanks for Listening! We acknowledge EPSRC for supporting this research under GAELS project Globally Asynchronous Elastic Logic Synthesis (EP/I038306/1) 22
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