On Efficient Concurrent Fault Simulation For Synchronous Sequential Circuits

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1 ~ On Efficient Concurrent Fault Simulation For Synchronous Sequential Circuits Dong Ho Lee Sudhakar M. Reddy Department of Computer Science Department of Electrical and Computer Engineering University of Iowa Iowa City, IA Abstract In this paper, we report on an efficient fault simulation method for synchronous sequential circuits. The method is based on concurrent fault simulation, and it has the simplicity of deductive fault simulation. Several new ideas to reduce computation time and memory requirement are proposed. New fault simulators wcrc developed to simulate transition faults as well as stuck-at faults. The experimental results demonstrate that the proposed method is an effective method to simulate faults in large synchronous sequential circuits in the workstation environment. 1. Introduction Efficient fault simulators for synchronous scquential circuits are important for the design of large digital circuitshystems. Recently, there has bccn a surge of publications in this area[2-71. Most of them utilize the fact that zero delay simulation is adequate for fault simulation in synchronous sequential circuits. [4] and 171 extended critical path tracing to sequential circuits, but they didn t give adequate experimental results to assess the effcctiveness of their methods. [5] proposes a fault simulator based on parallel simulation method. Concurrent fault simulation method has been successfully used in industry for a long time. Thc success of concurrent fault simulation is due to its flexibility to allow arbitrary delay fault simulation(i.e., the circuit gates may have arbitrary but known propagation delays) and mixed or hierarchical designs. But the concurrent fault simulation method has been criticized to be inefficient as compared to other methods which are specialized to synchronous scquential circuits[5]. In this paper, we introduce efficient fault simulators for synchronous sequential circuits which are based on concurrent fault simulation. The proposed method ha3 the simplicity of dcductivc fault simulation and flexibility and efficiency of concurrent fault simulation. Several improvements to reducc the computa- Lion time and memory requirement arc also proposed. The cxpcrimenral results show that the concurrent fault simulators with the proposed improvements arc competitive with This research has been supported by the SDIOflST Contract No. N J-1793 managed by US office of Naval Research other methods both in computation time and memory requirements. Although test generators and fault simulators for delay faults[ 101 have been reported for combinational circuits, stuck-at fault model has been the only practical fault model for sequential circuit test generation so far. A simpler delay fault model callcd transition fault model has been proposed and fault simulators for stuck-at faults have been augmented to accommodate this fault model[ 113. But no study of transition faults has been reported for sequential circuits in the literature. In this paper, transition fault model for synchronous sequential circuits is introduced and the concurrent fault simulator developed for stuck-at faults is extended to include transition faults. The paper is organized as follows. In Section2, a concurrent fault simulation method is discussed together with several improvements. In Section 3, transition fault model for synchronous sequential circuits is discussed. In Section 4, experimental results are presented followed by a summary in Section Concurrent fault simulation 29th ACM/IEEE Design Automation Conference@ Concurrent simulation is a simulation paradigm rather than an algorithm. Many algorithmic details should be carefully planned to make this paradigm into an effective fault simulator. In concurrent fault simulation, the circuit statc is defined in terms of the collection of gate states. The state of each gate is composed of all input line values and an output line value. The basic idea of concurrent fault simulation is to simulate one good machine and multiple faulty machines at the same time. In Figure l, good machine elements are shown with the white box and faulty machine elements for a fault fare shown with the gray box. Faulty machines are simulated specifically only where they assume different logic values than the good machine value. Each input line of a gate in a faulty machine gets its value either from the good machine or the corresponding faulty machine gate depending on whether the fault is explicit in its fanin gate. For example, the fault element at gate G4 gets its input from the fault element at gate GI in Figure 1.1, but it gets its input value from the good machine element in Figure 1.2 because fault f is not explicit at gate G 1. In concurrent fault simulation, an event generated on a machine propagates only within the machine. In other words, when an event is generated for a faulty machine, x192 $3.00 Q 1992 IEEE

2 only that faulty machine need be processed to propagate the changed value at ils fanout gates. A new fault element is introduced, i.e., diverged, when the propagated event makes the faulty machine assume a logic state which is different from the good state at a gate. n state variable. For example, the fault descriptor holds information about how to evaluate the faulty machine, or whether the fault has already been detected or not. Finally, the fault identifier is a pointer to its fault descriptor and each fault list is terminated with a terminal fault element which has a fault identifier which lies in high end memory location to avoid checking end of list during fault list processing. Fig 1.1 fault f explicit in G1 Fig 1.2 fault f implicit in G1 Figurel. Concurrent Fault Simulation On the other hand, when an existing fault element assumes the same logic state as the good machine state at a gate, the fault element should be removed, i.e., converged. In Figure 1, when the faulty machine assumed the same output value as the good machine value at gate G1, this event is propagated to gate G3 and G4. The fault element at gate G3 is removed, but the fault element at gate G4 should remain since the fault effect has also propagated through G2. The convergence and divergence can be determined by simply comparing logic state after gate evaluation, In some case, an event is generated when a faulty machine is converged at the gate. In this case, at the next level of simulation, the fault element of the fanout gate will copy its input value from the good machine element. In addition, a redundant copy of gate output value is kept at the input pin of its fanouts so that it is only necessary to compare the input fault lists of the gate which have events with its fault list. Furthermore, the state of a gate is packed into a word so that the output can be efficiently evaluated by table look up. Fast evaluation is extremely important in concurrent fault simulation because each faulty gate is explicitly evaluated one by one. Normally this is achieved through table look up. 2.1 Simplification Unlike in the originally proposed concurrent simulation method[9], the data structure of the proposed fault simulators adopts the simplicity of deductive fault simulation. As shown in Figure 2, each gate has a fault list and each element of the fault list is composed of a fault identifier, a state variable, and a pointer to the next element. The fault idenwier is a unique identifier which differentiates a fault from all other faults. Furthermore, a fault descriptor is associated with the fault identifier and the information central to the fault is stored in the fault descriptor and each fault element keeps only the local information, which is specific to the faulty machine state at the location, in the Fault Elements Fault Descriptors Fault E : input 2 of gate e stuck at 0 Fault G : output of gate g stuck at 0. dropped Figure 2. Data Structure In the following, we will briefly discuss arbitrary delay fault simulation using the given data structure. For convenience, we assume two phase fault simulation scheme. Assuming that delays are associated with gates, events are posted for all changing elements after gate evaluation. When delays vary widely among different faulty machines, it is advantageous to queue each faulty machine element independently into the timing queue, but for unit delay simulation, one can use a list event to queue a collection of faulty machine elements whose output values change at the same time. In the first phase of fault simulation, the matured events are fetched to assign logic values to gate outputs. When list events are used, the actual output values of fault elements are set via list traversal. The fanout gate identifiers are entered into a local queue, not the timing queue, for the second phase. When the event, i.e., the gate identifier, is fetched in second phase, the multi-list traversal technique[3] is employed to copy the logic values from the source fault lists to the destination fault list. Then the fault elements are evaluated and when the evaluated output values are different from previous values, events are posted. Fault simulation procedure for synchronous circuits is much simpler than described above because one can use zero delay simulation. For zero delay fault simulation, only the second phase is necessary since the evaluated value can be assigned directly on the output as long as the gate evaluation is done orderly according to its level, where the level of a gate is assigned so that all its fanins are at the lower levels. Furthermore, the timing queue is no longer necessary and only gate identifiers are "scheduled" into the event queue when there is an event on at least one machine element. Note that, in the general simulation 328 T

3 described before, a fault element is treated the same as the good machine gate so that it should be scheduled to be evaluated after a given delay. 2.2 Further improvements Among the three improvements discussed in this subsection, both fault dropping scheme and invisible fault handling scheme are good for arbitrary delay fault simulation as well as zero delay fault simulation. Fault dropping is very important in concurrent fault simulation because dropped fault effects should be eliminated as soon as possible for efficient fault simulation. Nevertheless, the fault elements for a detected fault are scattered around the circuit and there is no effective scheme to search them without scanning the whole circuit. We adopted an event driven fault dropping scheme. In this scheme fault elements for detected faults are removed while the fault list to which it belongs is traversed. This scheme can be implemented efficiently in the fault simulation procedure discussed before. The fault identifier of terminal element points to an imaginary fault descriptor which is never dropped. With this provision together with the proposed data structure, only several machine instructions are enough to check if a fault has been detected already. Most concurrent fault simulators keep invisible faults. Invisible faults are the fault elements which have the same output value as the good machine value. Invisible faults can be avoided if one copies the logic values of all input values when a new fault element is introduced. We use the method which keeps two fault lists, one for visible faults and the other for invisible faults, to avoid examining invisible faults. We found that splitting fault lists help reduce computation time. For further details, we refer to D31. Concurrent fault simulation uses table look up method to speed up gate evaluation. As a result, for example, evaluating an inverter takes the same amount of time as evaluating a multinput gate. In order to take advantage of table look up mechanism, it is advantageous to partition the circuit into macro modules. memory requirement because many fault elements are collapsed into one fault element. The number of fault elements is also reduced from 3 elements to 1 element in Figure 3. If the look up table overhead is not too high, macro extraction reduces the total memory requirement. We found that the speed improvement and decrease in memory are both significant for large circuits when macros are used. Although macros are limited to be fanout free in this paper, they can be any combinational circuits with limited number of inputs. When reconvergent macros are used, stuck at faults may be translated into functional faults which can be represented by look up table entries. The functional faults can be evaluated efficiently because each fault descriptor holds an adequate look up table entry corresponding the fault. Further details can be found in Wl. 3. Simulating transition faults Some physical faults do not show up when test clock cycle is much larger than the operational cycle. The transition fault is a gross delay fault where a gate is experiencing a modestly large delay. In general, any gate delay fault which delays a gate transition slightly longer than its slack time can be considered to be a transition fault. If the delay is extremely large, it acts as if it is a stuck-at fault[ 121. Two transition faults are associated with each gate input, i.e., 0 to 1 transition fault and 1 to 0 transition. If a gate input is experiencing a 0(1) to l(0) transition fault, the 0(1) to l(0) transition is delayed. This affects both the primary output values and the values sampled into flip-flops. Since the delay is not too large, after the primary outputs and flip-flops are sampled, the combinational part of the circuit is assumed to settle down correctly. Strictly speaking, this implies that the delay defect does not increase the delay at the fault site by more than one clock cycle, which we believe is reasonable. Table 1 shows the complete logic value relationship of this fault model. In Table 1, PV denotes the value when transition does not occur due to the transition fault and CV denotes the value when the transition is complete. I 0 -> 1 0 -> 0 0 -> x Table 1. Transition Table I 1 -> 0 Fault I PV ICV IFV ICV I X X X Transition I 0 -> 1 Fault Figure 3. Macro Extraction In Figure 3, a possible macro is enclosed by a dashed box. Macro extraction collapses many events into an event to save computation time. In Figure3, the number of gates to evaluate can be reduced from 3 evaluations to 1 evaluation. More importantly, macro extraction reduces the x ->o x->x 0 0 Ix 0 x X Ix X 329

4 Figure 4. Transition Fault We illustrate our model through an example given next. In Figure 4, consider a 0 to 1 transition Cault at the input 1 of gate G 1. Assumc that all signal line values are set to X s initially. To detect this fault the 01 input sequence is cnough. When the first input 0 is applied, logic value 1 will appear at the output. When the second input 1 is applicd, the value of input 2 of gate G1 is changed from X to 1. Since there is no Cault there, second input will be immediately set to 1. So there exists a sensitized path from the input I to the output 0. The good machine will output 0 at the sampling time, but the faulty machine value remains at logic value 1. Transition fault 1 to 0 at thc same gate input is more interesting. When this fault exists at input 1, it is necessary to use the scqucnce 00 to set the flip-flop. When a logic value 1 is applied as a third input, input 2 will assume logic value 1. Thc flip-flop input will have a logic value 1. If logic 0 is applied at the input 1, there is a transition, but the fault would not be detected because the latched value 1 will cause input 2 to assume logic value 0 to block the sensitizing path. It is necessary to apply logic 1 at the input again to make input 2 to assume logic value 0. Finally when a logic 0 is applied to input 1, input 2 will be changed to logic 1 before the transition fault affects the gate. The concurrent fault simulation method as proposed is ideal to simulate the transition faults because all previous input values of all the gates are available. To simulate the transition faults, the combinational part of the synchronous sequential circuit is simulated twice. In the first simulation, it is assumed that all faulty transitions do not fire to dctennine the propagated faults and, in addition, to latch (master part of) the flip-flops. Thcn the network is simulated again after firing all the transitions. Note that the Cault effects are latched into (master part of) the flip-flops at the first simulation, but (slave part of) the flip-flops should not be used in evaluation to avoid the ncw flipflop values affccting the second phase simulation. In actual implcmentation, it is possible to simulate transition faults in one pass since the second phase simulation can bc overlapped with the first phase simulation of the next time step, Further details can be found in [13]. 4. Experimental results To determine thc effectiveness of the proposed method, a stuck-at fault simulator based on the procedures discussed in Section 2 was impicmented and run on SUN Sparc 2. The final version is called csim-vm, where V means that visible and invisible faults are kept separately at each gate, and M means that macro modules are extracted. csim- M is a version which does not keep separate lists for visible and invisible faults and csim-v is the version that does not use macro extraction. In Table 2, the statistics of some benchmark circuits and the tests applied are given. These tests were used to evaluate the performance of PROOFS[5] and were provided to us by Professor J.H patel of University of Illinois. In Table 3, we report the CPU times and memory requirements for stuck-at fault simulation using the proposed simulator and PROOFS, all run on the same Sun Sparc 2 workstation. As one can see from the Table 3, both macro extraction and separation of visible/invisible faults consistently reduce the simulation time. Table 3. Deterministic Patterns (I) ckts csim V I csim I csim MV I PROOFS 1 I I-M I I I ~CPU lmem ]CPU lcpu I mem ICPU lmem Macro extraction increases the memory requirement a little bit for small circuits. But for large circuits, it actually reduces the memory requirement considerably. For example, the memory requirement is reduced from 16.2 M to 9.24 M in ~ Upto circuit s1494, csim-mv and PROOFS show comparable performance. For circuit ~5378, csim-mv is about two times faster than PROOFS. Paper

5 For ~35932, csim-mv performs slightly bctter than PROOFS. For somc of the ISCASS9 benchmark circuits, we were able to obtain higher coverage tests using a sequential test generator dcvelopcd by us[14]. In Table 4, we repon the results of fault simulation using thcse tests. Table 4. Deterministic Patterns(l1) 1 I I csim-mv I PROOFS ckts I#ptns lcvg ]CPU IMEM ICPU I MEM synchronous sequential circuits. More efficient fault simulation is possible when hierarchical design information is utilized because the concurrent fault simulation method is inherently suited to hierarchical designs[3]. Furthermore, the method can be extended to simulate faults for large circuits which contain both synchronous and asynchronous designs. Acknowledgment: We would like to thank Professor Janak Patel and his graduate students Vivek Chikermane and Elizabeth Rudnick for answering many questions regarding PROOFS and making PROOFS available to us. Reference In Tablc 5, wc rcport thc random pattcrn simulation results. Wc chosc thc larger onc of ISCAS-89 bcnchmark circuits, ~35932, for which random patterns gave reasonably high fault coverage. The memory requircmcnt of csim-mv in this experimcnt is lower than that shown in Table 3 becausc faults are rather I slowly 1 activated. I 1 Table 5. Random Pattern Simulation I I csim-mv I PROOFS #ptns 1 fltcvg ICPU IMEM ICPU MEM meg sec meg sec In Table 6 we report the transition fault coveragcs of the ISCAS89 benchmark circuits. The stuck at tests are not good tests for transition faults. Fault coverages are in general much less than 50%. Table 6.Transition Fault Simulation I ckts I# flts IMEMICPU I flt I 5. Conclusion In this paper we showed that concurrent fault simulation is a simple and effective method for simulating faults in [ 11 D. B. Armstrong, "A Deductive Method of Simulating Faults in Logic Circuits," IEEE Trans. on Computers, Vol. C-21, No. 5, pp , May, 1972 [2] W. T. Cheng and M. L. Yu, "Differential Fault Simulation - A Fast Method Using Minimal Memory," Proc. 26th Design Automation Conf., pp , June, S. Gai, F. Somenzi and E. Ulrich, "Advanced Techniques for Concurrent Multilevel Simulation," Proc. Intn'l Conf. on Computer-Aided Design, pp , November, P. R. Menon, Y.H. Levendel, and M. Abramovici, "Critical Path Tracing in Sequential Circuits," Proc. Intn'l Conf. on Computer-Aided Design, pp November, 1988 [S] T. M. Niermann, W. T. Cheng, and J. H. Patel, "Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator," 27th ACM/IEEE Design Automation Conference. pp [6] K. Son, "Fault Simulation with the Parallel Value List Algorithm," VLSl SYSTEMS DESIGN, pp , December X. Wang, "A Sequential Circuit Fault Simulation by Surrogate Fault Propagation," 1989 International Test Conference, pp [8] S. Seshu, "On an Improved Diagnostic Program," IEEE Trans. on Electronic Computers, Vol. EC-12, no. 12, pp , 1965 [9] E. G. Ulrich and T. Baker, "The Concurrent Simulation of Nearly Identical Digital Networks", 10th Design Automation Workshop, pp , 1973 [lo] V. S. Iyengar, B. K. Rosen. and J. A. Waicukauski, "On Computing the Sixs of Detected Delay Faults, " IEEE Transaction on Computer-Aided Design, March 90, pp [ 111 G. L. Smith, "Model for Delay Faults Based Upon Paths," Proc IEEE International Test Conference, November 1985, pp [ 121 J. A. Waicukauski and E. Lindbloom, "Transition Fault Simulation by Parallel Pattern Single Fault Propagation, 1986 International Conference, pp [ 131 D.H. Lee and S.M. Reddy, "On Efficient Concurrent Fault Simulation for Synchronous Sequential Circuits," Technical Memo in preparation, Department of Electrical and Computer Engineering. University of Iowa [I41 D.H. Lee and S.M. Reddy, "A New Test Generation Method for Sequential Circuits,'' Proc. Intn'l Conf. on Computer-Aided Design, pp , November,