TM52F2260. DATA SHEET Rev 0.90

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1 TM5F60 DATA SHEET Rev 0.90 tenx reserves the right to change or discontinue the manual and online documentation to this product herein to improve reliability, function or design without further notice. tenx does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. tenx products are not designed, intended, or authorized for use in life support appliances, devices, or systems. If Buyer purchases or uses tenx products for any such unintended or unauthorized application, Buyer shall indemnify and hold tenx and its officers, employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that tenx was negligent regarding the design or manufacture of the part.

2 TM5F60 Data Sheet AMENDMENT HISTORY Version Date Description V0.90 Jan, 05 New release DS-TM5F60_E Rev 0.90, 05/0/07

3 TM5F60 Data Sheet CONTENTS AMENDMENT HISTORY... TM5 Fxx FAMILY... 5 GENERAL DESCRIPTION... 6 BLOCK DIAGRAM... 6 FEATURES... 7 PIN ASSIGNMENT... 0 PIN DESCRIPTION... PIN SUMMERY... FUNCTIONAL DESCRIPTION.... CPU Core.... Accumulator (ACC).... B Register (B)....3 Stack Pointer (SP).... Dual Data Pointer (DPTRs) Program Status Word (PSW) Memory Program Memory Data Memory Power.... Reset.... Power on Reset.... External Pin Reset....3 Software Reset.... Watch Dog Timer Reset....5 Low Voltage Reset Clock Circuitry & Operation Mode System Clock Operation Modes Interrupt & Wake-up Interrupt Enable and Priority Control Pin Interrupt Idle mode Wake up and Interrupt Stop mode Wake up and Interrupt I/O Ports Port & Port P DS-TM5F60_E 3 Rev 0.90, 05/0/07

4 TM5F60 Data Sheet 7.3 Port Timers Timer0 / Timer Timer Timer TO, TB and TO output Control UART Resistance to Frequency Converter (RFC) LCD Driver In Circuit Emulation (ICE) Mode... 5 SFR & CFGW MAP SFR & CFGW DESCRIPTION INSTRUCTION SET... 6 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings DC Characteristics BandGap Reference Voltage Clock Timing V DD Voltage Level LVR Level PACKAGE INFORMATION DS-TM5F60_E Rev 0.90, 05/0/07

5 TM5F60 Data Sheet TM5 Fxx FAMILY Common Feature CPU Fast 805 (T) Flash Program memory 8K~3K with IAP, ISP, ICP RAM bytes 5 ~ 30 Dual Clock SXT SRC FXT FRC Operation Mode Fast Slow Idle Stop Timer0 Timer Timer UART 805 Standard Real-time Timer3 0.5~6ppm Adjustable LBD.V ~ 3.V LVR.6V Family Members Features P/N Flash RAM bytes IO Pin RFC ADC SAR ADC Touch Key LCD LED SPI others Status TM5-F6 -ch 3 x 0 30x6 6K ch.0~.5V 0mA hi- Yes Product TM5-F6 adj.-bias Sink 36 x TM5-F60 6K ch Product.0V Bias TM5-F80 6bit 5-ch 3 x 8 0x 8K ch.0~.5V 0mA hi- Yes Product TM5-F8 7-ch adj.-bias Sink 6bit TM5-F30 3K ch 5-ch Yes PWM Sample 7-ch P/N Operation Voltage Idle Mode Current (V BAT =3V) with 3KHz wake-up & LVR On TK Off TK On LCD On LCD Off TK Off LCD Off TK On LCD On TM5-F6.3uA.9uA.0~.V 0.8uA.uA TM5-F6 Max. System Clock (Hz) SXT SRC FXT FRC 3K M TM5-F60.0~.V 0.7uA.0uA 3K M TM5-F80.5uA 3.0uA.0~5.5V.0uA.5uA TM5-F8 3K 80K 8M 7.M TM5-F30.0~5.5V.0uA.5uA 3K 80K 8M 7.M DS-TM5F60_E 5 Rev 0.90, 05/0/07

6 TM5F60 Data Sheet GENERAL DESCRIPTION TM5 series F60 is a version of a new, fast 805 architecture for an 8-bit microcontroller single chip with an instruction set fully compatible with industry standard 805, C language development platform, and retains most 805 peripheral functional block. Typically, the TM5-F60 executes instructions six times faster than the traditional 805 architecture. The TM5-F60 provides improved performance, lower cost and fast time-to-market by integrating features on the chip, including 6K Bytes Flash program memory, 80 Bytes SRAM, Low Voltage Reset (LVR), Low Battery Detector (LBD), dual clock power saving operation mode, 805 standard UART and Timer0//, adjustable real time Timer3, LCD driver, Watch Dog Timer and Resistance to Frequency Converter (RFC). Its high reliability and low power consumption feature can be widely applied in consumer and battery appliance products. BLOCK DIAGRAM FRC 3.8 MHz SXT KHz Dual System Clock Flash 6K Bytes IAP ICP ISP IRAM 56 Bytes XRAM 0 Bytes Port0 [7..0] Port [7..0] Port [7] Port3 [7..0] External INT 0// Clock Divider Port Wake-up RTC Timer3 805 Timer 0// WDT POR / LVR BandGap V-Ref LBD Fast 805 CPU Core Power Management Fast / Slow / Idle / Stop Operation Mode RFC ADC UART TX/RX LCD Driver COM 8~36 SEG TM5F60 DS-TM5F60_E 6 Rev 0.90, 05/0/07

7 TM5F60 Data Sheet FEATURES. Standard 805 Instruction set, fast machine cycle Executes instructions six times faster than the traditional K Bytes Flash Program Memory Support In Circuit Programming (ICP) or In System Programming (ISP) for the Flash code Byte Write In Application Programming (IAP) mode is convenient as Data EEPROM access Code Protection Capability 3. Total 80 Bytes SRAM (IRAM + XRAM) 56 Bytes IRAM in the 805 internal data memory area 0 Bytes XRAM in the 805 external data memory area (accessed by MOVX Instruction). Three System Clock type Selections Fast clock from Internal RC (FRC, DD =3V) Slow clock from 3768Hz Crystal (SXT) Slow clock from RFC System Clock can be divided by //6/6 option System Clock output pin (TCO) for EL / IR application Standard Timer Timer0 / / 6-bit Timer0, also supports RFC clock input counting 6-bit Timer, also supports TO / TB clock output for Buzzer / IR application 6-bit Timer, also supports TO clock output for Buzzer / IR application 6. 3-bit Timer3 used for Real Time 3768Hz Crystal counting ± 0.5 ppm ~ 6 ppm interrupt rate adjustable MSB 8-bit overflow auto-reload 0.5 sec, 0.5 sec,.0 sec or overflow Interrupt 7. 9-Sources, -level priority Interrupt Timer0 / Timer / Timer / Timer3 Interrupt INT0 / INT Falling-Edge / Low-Level Interrupt Port Pin Change Interrupt UART TX/RX Interrupt P.7 (INT) Interrupt 8. Pin Interrupt can Wake up CPU from Power-Down (Stop) mode P3. / P3.3 (INT0 / INT) Interrupt & Wake-up P.7 (INT) Interrupt & Wake-up Each Port pin can be defined as Interrupt & Wake-up pin (by pin change) DS-TM5F60_E 7 Rev 0.90, 05/0/07

8 TM5F60 Data Sheet Standard UART One Wire UART option can be used for ISP or other application 0. Max. 5 Programmable I/O pins CMOS Output Pseudo-Open-Drain, or Open-Drain Output Schmitt Trigger Input Pin Pull-up can be Enabled or Disabled. Resistance to Frequency Converter (RFC) RFC clock divided by //6/6 signal can be assigned as Timer0 event count input RFC clock can be used as System clock source. LCD Controller / Driver /3 or / Duty COM, 8 ~ 36 SEG /3 Bias, VL = V BAT / 3 Frame Rate = 0Hz ~ 90Hz 3. BandGap Voltage Reference for Low Battery Detection (LBD) Detect V BAT voltage level from.5v to 3.V. Built-in tiny current LDO Regulator for chip internal power supply (V DD ) V DD voltage level can be set from.v to.9v 5. Watch Dog Timer based on System Clock Running in Fast / Slow Mode, Stop counting in Idle / Stop Mode 3K or 6K counts overflow Reset 6. 5-types Reset Power on Reset Selectable External Pin Reset Selectable Watch Dog Reset Software Command Reset Selectable Battery Low Voltage Reset (when V BAT <.6V) 7. -types Power Operation Modes Fast / Slow / Idle / Stop Mode 8. On-chip Debug / ICE interface Use P. / P.3 pin Share with ICP programming pin DS-TM5F60_E 8 Rev 0.90, 05/0/07

9 TM5F60 Data Sheet 9. Operating Voltage and Current V BAT =.0V ~.V 0.3uA LCD BAT = 3V 0.uA LVR BAT = 3V 0.6uA 3K Crystal and System Clock DD =.5V Total.0uA Idle mode Current with LCD on and LVR BAT = 3V, V DD =.5V 0. Operating Temperature Range 0 C ~ +85 C. 6-pin LQFP Package DS-TM5F60_E 9 Rev 0.90, 05/0/07

10 TM5F60 Data Sheet DS-TM5F60_E 0 Rev 0.90, 05/0/07 PIN ASSIGNMENT TM5-F60 LQFP-6 SEG3 SEG SEG SEG0 SEG9 SEG8 SEG7 SEG6 SEG5 SEG SEG5 SEG6 SEG7 SEG8/P0.7 SEG30/P0.5 SEG3/P0. SEG3/P0.3 SEG33/P0. SEG3/P0. SEG9/P0.6 SEG SEG SEG3 SEG SEG5 SEG6 SEG7 RFCR/P.6 RFCR/P.5 RFC0R/P. P.3 P. TEX/P. TO/T/P.0 RXD/P3.0 TXD/P3. INT0/P3. INT/P3.3 SEG35/P0.0 TB/P3.6 TO/T/P3.5 T0/P3. TCO/P3.7 VDD VSS X X RFCX/P.7 COM3 VBAT P.7/RSTn/INT/VPP VL VL COM0 COM COM SEG0 SEG SEG3 SEG SEG SEG0 SEG9 SEG

11 TM5F60 Data Sheet PIN DESCRIPTION Name In/Out Pin Description P.0~P.7 I/O Bit-programmable I/O port for Schmitt-trigger input, CMOS push-pull output or open-drain output. Pull-up resistors are assignable by software. These pin s level change can interrupt/wake up CPU from Idle/Stop mode. P3.0~P3. I/O Bit-programmable I/O port for Schmitt-trigger input, CMOS push-pull output or pseudo open drain output. Pull-up resistors are assignable by software. P3.3~P3.7 I/O Bit-programmable I/O port for Schmitt-trigger input, CMOS push-pull output or open-drain output. Pull-up resistors are assignable by software. P0.0~P0.7 I/O Bit-programmable I/O port for Schmitt-trigger input or CMOS push-pull output. Pull-up resistors are assignable by software. P.7 I/O Bit-programmable I/O port for Schmitt-trigger input or open-drain output. Pull-up resistor is fix enable. INT0, INT I External low level or falling edge Interrupt input, Idle/Stop mode wake up input INT I External falling edge Interrupt input, Idle / Stop mode wake up input RXD I/O UART Mode0 transmit & receive data, Mode//3 receive data TXD I/O UART Mode0 transmit clock, Mode//3 transmit data. In One Wire UART mode, this pin transmits and receives serial data. T0, T, T I Timer0, Timer, Timer event count pin input TEX I Timer external trigger input TO, TB O Positive and Negative signal pair of Timer overflow divided by /3/ output TO O Timer overflow divided by /3/ output TCO O System Clock divided by //3/ output RFC0R~RFCR O RFC resistor connection pin RFCX I RFC clock input pin SEG0~SEG35 O LCD segment output COM0~COM3 O LCD common output VL, VL LCD Bias Voltage Regulator output, add 0.uF capacitor for each pin to VSS RSTn I External active low reset input, Pull-up resistor is fixed enable X, X 3768 Crystal / Resonator oscillator connection for System Clock VPP I Flash memory programming high voltage input VDD LDO Regulator output and internal power supply, add uf capacitor to VSS VBAT, VSS P Power input pin and ground, VBAT is the I/O pin power supply Note: Digital I/O pins voltage swing from V SS to V BAT. DS-TM5F60_E Rev 0.90, 05/0/07

12 LQFP-6 Type Function State Wake up Ext. Interrupt CMOS P.P. P.O.D. O.D. LCD RFC UART Clock Output Timer Input TM5F60 Data Sheet PIN SUMMERY After Reset Input Output Alternative Function Pin Name Others SEG O LCD DL SEG5 O LCD DL 3 SEG6 O LCD DL SEG7 O LCD DL 5 SEG8/P0.7 I/O LCD DL 6 SEG9/P0.6 I/O LCD DL 7 SEG30/P0.5 I/O LCD DL 8 SEG3/P0. I/O LCD DL 9 SEG3/P0.3 I/O LCD DL 0 SEG33/P0. I/O LCD DL SEG3/P0. I/O LCD DL SEG35/P0.0 I/O LCD DL 3 TCO/P3.7 I/O I/O Input PU TB/P3.6 I/O I/O Input PU 5 TO/T/P3.5 I/O I/O Input PU 6 T0/P3. I/O I/O Input PU 7 INT/P3.3 I/O I/O Input PU 8 INT0/P3. I/O I/O Input PU 9 TXD/P3. I/O I/O Input PU 0 RXD/P3.0 I/O I/O Input PU TO/T/ P.0 I/O I/O Input PU TEX/P. I/O I/O Input PU 3 P. I/O I/O Input PU P.3 I/O I/O Input PU 5 RFC0R/P. I/O I/O Input PU 6 RFCR/P.5 I/O I/O Input PU 7 RFCR/P.6 I/O I/O Input PU 8 RFCX/P.7 I/O I/O Input PU 9 X Crystal Crystal 30 X Crystal Crystal 3 VSS P V SS 3 VDD V DD 33 VBAT P V BAT 3 VPP/RSTn/INT/P.7 I/O I/O Input PU Reset/VPP DS-TM5F60_E Rev 0.90, 05/0/07

13 LQFP-6 Type Function State Wake up Ext. Interrupt CMOS P.P. P.O.D. O.D. LCD RFC UART Clock Output Timer Input TM5F60 Data Sheet After Reset Input Output Alternative Function Pin Name Others Misc. 35 VL LCD 36 VL LCD 37 COM0 O LCD DL 38 COM O LCD DL 39 COM O LCD DL 0 COM3 O LCD DL SEG0 O LCD DL SEG O LCD DL 3 SEG O LCD DL SEG3 O LCD DL 5 SEG O LCD DL 6 SEG5 O LCD DL 7 SEG6 O LCD DL 8 SEG7 O LCD DL 9 SEG8 O LCD DL 50 SEG9 O LCD DL 5 SEG0 O LCD DL 5 SEG O LCD DL 53 SEG O LCD DL 5 SEG3 O LCD DL 55 SEG O LCD DL 56 SEG5 O LCD DL 57 SEG6 O LCD DL 58 SEG7 O LCD DL 59 SEG8 O LCD DL 60 SEG9 O LCD DL 6 SEG0 O LCD DL 6 SEG O LCD DL 63 SEG O LCD DL 6 SEG3 O LCD DL Symbol: P.P. O.D. P.O.D. PU DL = CMOS Push-Pull Output = Open Drain = Pseudo Open Drain = Pull up = Drive Low DS-TM5F60_E 3 Rev 0.90, 05/0/07

14 TM5F60 Data Sheet FUNCTIONAL DESCRIPTION. CPU Core In the 805 architecture, the C programming language is used as a development platform. The F60 features a fast 805 core in a highly integrated microcontroller, allowing designers to be able to achieve improved performance compared to a classic 805 device. TM5 series microcontrollers provide a complete binary code with standard 805 instruction set compatibility, ensuring an easy migration path to accelerate the development speed of system products. The CPU core includes an ALU, a program status word (PSW), an accumulator (ACC), a B register, a stack point (SP), DPTRs, a programming counter, an instruction decoder, and core special function registers (SFRs).. Accumulator (ACC) This register provides one of the operands for most ALU operations. Accumulators are generally referred to as A or Acc and sometimes referred to as Register A. In this document, the accumulator is represented as A or ACC, including the instruction table. The accumulator, as its name suggests, is used as a general register to accumulate the intermediate results of a large number of instructions. The accumulator is the most important and frequently used register to complete arithmetic and logical operations. It holds the intermediate results of most arithmetic and logic operations and assists in data transportation. SFR E0h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 ACC ACC.7 ACC.6 ACC.5 ACC. ACC.3 ACC. ACC. ACC.0 Reset E0h.7~0 ACC: Accumulator. B Register (B) The B register is very similar to the ACC and may hold a Byte value. This register provides the second operand for multiply or divide instructions. Otherwise, it may be used as a scratch pad register. The B register is only used by two 805 instructions, MUL and DIV. When A is to be multiplied or divided by another number, the other number is stored in B. For MUL and DIV instructions, it is necessary that the two operands be in A and B. SFR F0h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 B B.7 B.6 B.5 B. B.3 B. B. B.0 Reset F0h.7~0 B: B register.3 Stack Pointer (SP) The SP register contains the Stack Pointer. The Stack Pointer is used to load the program counter into memory during LCALL and ACALL instructions and is used to retrieve the program counter from memory in RET and RETI instructions. The stack may also be saved or loaded using PUSH and POP instructions, which also increment and decrement the Stack Pointer. The Stack Pointer points to the top location of the stack. DS-TM5F60_E Rev 0.90, 05/0/07

15 TM5F60 Data Sheet SFR 8h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 SP SP Reset h.7~0 SP: Stack Point. Dual Data Pointer (DPTRs) F60 has two DPTRs, which share the same SFR address. Each DPTR is 6 bits in size and consists of two registers: the DPTR high byte (DPH) and the DPTR low byte (DPL). The DPTR is used for 6-bitaddress external memory accesses, for offset code byte fetches, and for offset program jumps. Setting the DPSEL control bit allows the program code to switch between the two physical DPTRs. SFR 8h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 DPL DPL Reset h.7~0 DPL: Data Point low byte SFR 83h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 DPH DPH Reset h.7~0 DPH: Data Point high byte SFR F8h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 AUX CLRWDT CLRTM3 STPRFC DPSEL Reset F8h.0 DPSEL: Active DPTR Select.5 Program Status Word (PSW) This register contains status information resulting from CPU and ALU operations. The PSW affected by instructions is listed below. Instruction Flag Flag Instruction C OV AC C OV AC ADD X X X CLR C 0 ADDC X X X CPL C X SUBB X X X ANL C, bit X MUL 0 X ANL C, /bit X DIV 0 X ORL C, bit X DA X ORL C, /bit X RRC X MOV C, bit X RLC X CJNE X SETB C A 0 means the flag is always cleared, a means the flag is always set and an X means that the state of the flag depends on the result of the operation. DS-TM5F60_E 5 Rev 0.90, 05/0/07

16 TM5F60 Data Sheet SFR D0h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 PSW CY AC F0 RS RS0 OV F P Reset D0h.7 CY: ALU carry flag D0h.6 AC: ALU auxiliary carry flag D0h.5 F0: General purpose user-definable flag D0h.~3 RS, RS0: The contents of (RS, RS0) enable the working register banks as: 00: Bank 0 (00h~07h) 0: Bank (08h~0Fh) 0: Bank (0h~7h) : Bank 3 (8h~Fh) D0h. OV: ALU overflow flag D0h. F: General purpose user-definable flag D0h.0 P: Parity flag. Set/cleared by hardware each instruction cycle to indicate odd/even number of one bits in the accumulator. Bit 7 CY Bit 6 AC Bit 5 FO PSW Bit Bit 3 RS RS0 Bit OV Bit F Bit 0 P RS 0 0 RS0 0 0 Bank 3 0 8h 0h 08h 00h R0 R0 R0 R0 Register Bank 3 R R R3 R R5 R6 Register Bank R R R3 R R5 R6 Register Bank R R R3 R R5 R6 Register Bank 0 R R R3 R R5 R6 R7 R7 R7 R7 Fh 7h 0Fh 07h DS-TM5F60_E 6 Rev 0.90, 05/0/07

17 TM5F60 Data Sheet. Memory. Program Memory The F60 has a 6K Bytes Flash program memory, which can support in-circuit program (ICP), inapplication program (IAP) and in-system program (ISP) function modes. The Flash program memory address continuous space (0000h~3FFFh) is partitioned to several sectors for device operation... Program Memory Functional Partition The last bytes (3FFEh~3FFFh) of program memory is defined as chip Configuration Word (CFGW), which is loaded into the device control registers upon power on reset (POR). The address space 3F00h~3FFDh is the IAP free area, while the 0000h~005Fh is occupied by Reset/Interrupt vectors as standard 805 definition. In the in-circuit emulation (ICE) mode, user also needs to reserve the address space D00h~FFFh for ICE System communication. 0000h 005Fh 0060h CFFh D00h FFFh 000h 3EFFh 3F00h 3FFDh 3FFEh 3FFFh 6K Bytes program memory Reset/Interrupt Vector User Code area ICE mode reserve area User Code area IAP-Free area CFGW.. Flash ICP Mode The Flash memory can be programmed by the tenx proprietary writer (TWR98/TWR99), which needs at least four wires (VBAT, VSS, P., and P.3 pins) to connect to this chip. To shorten the programming time, it is recommended to connect Writer with an additional fifth wire, which is the VPP (P.7) pin. If the user wants to program the Flash memory on the target circuit board (In Circuit Program, ICP), these pins must be reserved sufficient freedom to be connected to the Writer. More pins connected to Writer ensure more writing efficiency and speed. Writer wire number Pin connection -Wire VBAT, VSS, P., P.3 5-Wire 6-Wire VBAT, VSS, P., P.3, VPP VBAT, VSS, P., P.3, VPP, P.0. Note: P. always output Low in this mode DS-TM5F60_E 7 Rev 0.90, 05/0/07

18 TM5F60 Data Sheet..3 Flash IAP Mode The F60 has In Application Program (IAP) capability, which allows software to read/write data from/to the Flash memory during CPU run time as conveniently as data EEPROM access. The IAP function is byte writable, meaning that the F60 does not need to erase one Flash page before write. The available IAP data space is 5 Bytes after chip reset, and can be re-defined by the MVCLOCK and IAPALL control register as shown below. 6K Bytes Flash MOVC MOVX (IAP) Flash memory MVCLOCK IAPALL Program memory Accessible Accessible 0000h X No No MOVC-Lock area 0000h~0FFh 0 0 Yes No 0FFh 0 Yes Yes 000h X 0 Yes No IAP-All area 000h~3EFFh 3EFFh 3F00h X Yes Yes IAP-Free area 3F00h~3FFDh X X Yes Yes 3FFEh X 0 Yes No 3FFEh CFGW area X Yes Yes 3FFFh 3FFFh X X Yes No In IAP mode, the program Flash memory is separated into four sectors: MOVC-Lock area, IAP-All area, IAP-Free area, and CFGW area. These four sectors are regulated differently. In the MOVC-Lock area, IAP read/write is limited by MVCLOCK bit, which can be set to control the accessibility of the MOVC and MOVX instructions to this area. The size of this area is 5 Bytes. The lock function is made to protect the main program code against unconsciously writing Flash memory in IAP mode. Locking or unlocking the function should be performed by the tenx TWR98/99 writing to the CFGW in Flash memory. The IAP-All area is protected by the IAPALL register to prevent IAP mode from writing application data to the program area, resulting in a program code error that cannot be repaired. The size of this area is 5,66 Bytes. Enabling IAPALL requires writing 65h to SFR SWCMD 97h to set the IAPALL control flag. Then, software can use MOVX instructions to write application data to flash memory from 000h to 3EFFh. If user wants to disable IAPALL function, user can write other values to SFR SWCMD 97h to clear the IAPALL control flag. User must be careful not to overwrite program code which is already resided on the same Flash memory area. The IAP-Free area has no control bit to protect. It can be used to reliably store system application data that needs to be programmed once or periodically during system operation. Other areas of Flash memory can be used to store data, but this area is usually the best. The size of this area is 5 Bytes, equivalent to an EEPROM, and Flash memory can provide byte access to read and write commands. In the past, storage of configuration data required an additional EEPROM or the other storage device. However, this functionality can now be provided by on-chip Flash, reducing the chip count of embedded applications. An external EEPROM or SRAM may not be needed. The CFGW area has data bytes (CFGWH and CFGWL), which is located at the last addresses of Flash memory. The CFGWH is not accessible to IAP, while the CFGWL can be read or written by IAP in case the IAPALL flag is set. CFGWL is copied to the SFR F7h after power on reset, software then DS-TM5F60_E 8 Rev 0.90, 05/0/07

19 TM5F60 Data Sheet take over CFGWL s control capability by modifying the SFR F7h. The CFGWL is applied in many other TM5 series MCU. However, it is not defined in F60. Flash 3FFFh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 CFGWH PROT XRSTE MVCLOCK WDTE LVRE 3FFFh.5 MVCLOCK: If, the MOVC & MOVX instruction s accessibility to MOVC-Lock area is limited. SFR 97h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 SWCMD IAPALL / SWRST W Reset 0 97h.7~0 IAPALL (W): Write 65h to set IAPALL control flag; Write other value to clear IAPALL flag. 97h.0 IAPALL (R): Flag indicates Flash memory sectors can be accessed by IAP or not. This bit combines with MVCLOCK to define the accessible IAP area... IAP Mode Access Routines Flash IAP write is simply achieved by a A instruction while the DPTR contains the target Flash address (0~3FFEh), and the ACC contains the data being written. Flash IAP writing requires approximately 500uS. Meanwhile, the CPU stays in a waiting state, but all peripheral modules (Timers, LCD, and others) continue running during the writing time. The software must handle the pending interrupts after an IAP write. Flash IAP writing needs slower SYSCLK frequency as well as higher V DD voltage. User must clear PWRSAV control bit to let V DD =V BAT and V BAT >.8V. Because the Program memory and the IAP data space share the same entity, a Flash IAP read can be performed by the MOVX or MOVC instruction as long as the target address points to the 0~3FFFh area. A Flash IAP read does not require extra CPU wait time. ; IAP example code ; need V DD >.8V and slower System clock MOV DPTR, #3F00h ; DPTR=3F00h=target IAP address MOV A, #5Ah ; A=5Ah=target IAP write data A ; Flash[3F00h]=5Ah, after IAP write ; 00µs~500µs H/W writing time, CPU wait CLR A ; A=0 MOVX ; A=5Ah CLR A ; A=0 MOVC ; A=5Ah..5 Flash ISP Mode The In System Program (ISP) usage is similar to IAP, except the purpose is to refresh the Program code. User can use UART or other method to get new Program code from external host, then writes code as the same way as IAP. ISP operation is complicated; basically it needs to assign a Boot code area to the Flash which does not change during the ISP process. DS-TM5F60_E 9 Rev 0.90, 05/0/07

20 TM5F60 Data Sheet. Data Memory As the standard 805, the F60 has both Internal and External Data Memory space. The Internal Data Memory space consists of 56 Bytes IRAM and 50 SFRs, which are accessible through a rich instruction set. The External Data Memory space consists of 0 Bytes XRAM, LCDRAM and IAP Flash, which can be only accessed by MOVX instruction. FFh IRAM Internal Data Memory SFR 0000h External Data Memory 80h 7Fh Indirect Addressing IRAM Direct Addressing 3FFFh IAP Flash shared with Program memory 00h Direct/Indirect Addressing F000h LCD RAM FC00h FFFFh XRAM.. IRAM IRAM is located in the 805 internal data memory space. The whole 56 Bytes IRAM are accessible using indirect addressing but only the lower 8 Bytes are accessible using direct addressing. There are four directly addressable register banks (switching by PSW), which occupy IRAM space from 00h to Fh. The address 0h to Fh 6 Bytes IRAM space is bit-addressable. IRAM can be used as scratch pad registers or program stack... XRAM XRAM is located in the 805 external data memory space (address FC00h to FFFFh). The 0 Bytes XRAM can be only accessed by MOVX instruction...3 SFRs All peripheral functional modules such as I/O ports, Timers and UART operations for the chip are accessed via Special Function Registers (SFRs). These registers occupy upper 8 Bytes of direct Data Memory space locations in the range 80h to FFh. There are bit addressable SFRs (which means that eight individual bits inside a single byte are addressable), such as ACC, B register, PSW, TCON, SCON, and others. The remaining SFRs are only byte addressable. SFRs provide control and data exchange with the resources and peripherals of the F60. The TM5 series of microcontrollers provides complete binary code with standard 805 instruction set compatibility. Beside the standard 805 SFRs, the F60 implements additional SFRs used to configure and access subsystems such as the Timer3, RFC and LCD, which are unique to the F60. DS-TM5F60_E 0 Rev 0.90, 05/0/07

21 TM5F60 Data Sheet Internal Data Memory Direct / Indirect Addressing 7Fh FFh General Purpose RAM Indirect Addressing (SRAM) SFR Direct Addressing 30h 0h 8h 0h 08h 00h 7F 77 6F 67 5F 57 F 7 3F 37 F 7 F 7 0F 07 7E 76 6E 66 5E 56 E 6 3E 36 E 6 E 6 0E 06 7D 75 6D 65 5D 55 D 5 3D 35 D 5 D 5 0D 05 7C 7 7B 73 6C 6B C 5B 5 53 C B 3 3C 3B 3 33 C B 3 C B 3 0C 0B A A A A 9 3A A 9 A 9 0A Register Bank 3 Register Bank Register Bank Register Bank Bit addressable Fh 7h 0Fh 07h Fh 80h 7Fh 0h 00h Direct / Indirect Addressing Direct / Indirect Addressing (SRAM) Bit addressable AUX B ACC CLKCON PSW TCON P5 IP IE P SCON P TCON P0 F8h F0h E8h E0h D8h D0h C8h C0h B8h B0h A8h A0h 98h 90h 88h 80h 8/0 9/ A/ B/3 C/ D/5 E/6 F/7 F8h AUX F0h B E8h E0h ACC D8h CLKCON D0h PSW C8h TCON RCPL RCPH TL TH C0h B8h IP IPH IP IPH B0h P3 LCON TM3SEC TM3DL TM3DH TM3RLD TM3ADJ A8h IE INTE RFCON A0h P PMODL PMODH P3MODL P3MODH TOCON VCON 98h SCON SBUF 90h P P0OE OPTION INTFLG PWKUP SWCMD 88h TCON TMOD TL0 TL TH0 TH 80h P0 SP DPL DPH PCON DS-TM5F60_E Rev 0.90, 05/0/07

22 TM5F60 Data Sheet 3. Power VBAT pin is the power supply for this chip. It provides voltage source to the built-in tiny current LDO Regulator for chip internal operation. The VDD is the LDO output pin, which needs an external uf capacitor connection to VSS for voltage level stability. The PWRSAV and VSET/VSET SFR bits control the V DD voltage level. If PWRSAV=0 (chip reset default), V DD voltage level is the same as V BAT. If PWRSAV=, the V DD voltage level can be switched from V BAT *5/300 to V BAT *9/300 range. The VSET/VSET SFR can set the V DD voltage level in different operation mode. The lower V DD voltage level causes lower chip current consumption, but user must also consider the System clock rate. Higher clock rate needs higher V DD voltage level. User must keep.v<v DD <.V for the device s proper operation. In IAP write mode, user also needs to set V DD >.8V, which means PWRSAV bit must be 0. The F60 also has a built-in.v BandGap Voltage Reference for Low Battery Detection (LBD). The Battery voltage is divided by resistor to certain level then compare to the BandGap voltage. User can refer to the V BAT voltage level for setting the V DD level by VSET or VSET SFR. The BandGap and Comparator consume un-neglect current, so user should not use them too often. Since V BAT voltage level changes very slowly, user can detect it once an hour or once a day to reduce current consumption. LDO Regulator & Comparator CMPO CMPVS V < V BAT 3.0 < V BAT < 3.V 0.9 < V BAT < 3.0V < V BAT <.9V < V BAT <.8V < V BAT <.7V < V BAT <.6V V BAT <.5V Comparator Result vs V BAT voltage level DS-TM5F60_E Rev 0.90, 05/0/07

23 TM5F60 Data Sheet SFR 9h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 OPTION CMPO CMPVS UARTW WDTPSC TM3PSC R Reset h.7 CMPO: Compare result of BandGap voltage and V BAT voltage divider. means the V BAT divider voltage is higher. 9h.6~ CMPVS: Select V BAT resistor divider for Comparator input to compare with the.v reference. 000: Comparator Disable 00: the Comparator input is V BAT */5 00: the Comparator input is V BAT */6 0: the Comparator input is V BAT */7 00: the Comparator input is V BAT */8 0: the Comparator input is V BAT */9 0: the Comparator input is V BAT */30 : the Comparator input is V BAT */3 SFR A7h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 VCON PWRSAV VSET VSET Reset A7h.6 PWRSAV: V DD voltage control. 0: V DD = V BAT : V DD = V BAT *5/300 ~ V BAT *9/300 A7h.5~3 VSET: V DD voltage setting in Fast/Slow mode while PWRSAV=. 000: V DD = V BAT *5/300 in Fast/Slow mode 00: V DD = V BAT *6/300 in Fast/Slow mode 00: V DD = V BAT *37/300 in Fast/Slow mode 0: V DD = V BAT *8/300 in Fast/Slow mode 00: V DD = V BAT *59/300 in Fast/Slow mode 0: V DD = V BAT *70/300 in Fast/Slow mode 0: V DD = V BAT *8/300 in Fast/Slow mode : V DD = V BAT *9/300 in Fast/Slow mode A7h.~0 VSET: V DD voltage setting in Idle/Stop mode while PWRSAV=. 000: V DD = V BAT *5/300 in Idle/Stop mode 00: V DD = V BAT *6/300 in Idle/Stop mode 00: V DD = V BAT *37/300 in Idle/Stop mode 0: V DD = V BAT *8/300 in Idle/Stop mode 00: V DD = V BAT *59/300 in Idle/Stop mode 0: V DD = V BAT *70/300 in Idle/Stop mode 0: V DD = V BAT *8/300 in Idle/Stop mode : V DD = V BAT *9/300 in Idle/Stop mode DS-TM5F60_E 3 Rev 0.90, 05/0/07

24 TM5F60 Data Sheet. Reset The F60 has five types of reset methods. The CFGW controls the Reset functionality. The SFRs are returned to their default value after Reset.. Power on Reset After Power on Reset, the device stays on Reset state for 8 ms as chip warm up time, then downloads the CFGW register from Flash s last two bytes (Other Reset will not reload the CFGW). The Power on Reset needs both V BAT and V DD s voltage first discharge to near V SS level, then rise beyond.8v.. External Pin Reset External Pin Reset is active low. The RSTn pin needs to keep at least FRC clock cycle long to be sampled by the chip. Pin Reset can be disabled or enabled by CFGW..3 Software Reset Software Reset is activated by writing the SFR 97h with data 56h.. Watch Dog Timer Reset WDT overflow Reset is disabled or enable by CFGW. The WDT uses SYSCLK as its counting time base. It runs in Fast / Slow mode and stops in Idle / Stop mode. WDT overflow speed can be defined by WDTPSC SFR. WDT is cleared by device Reset or CLRWDT SFR bit..5 Low Voltage Reset LVR is disabled or enable by CFGW. If enable, LVR resets the device when V BAT <.5V. Flash 3FFFh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 CFGWH PROT XRSTE MVCLOCK WDTE LVRE 3FFFh.6 XRSTE: Pin Reset enable, =enable. 3FFFh. WDTE: WDT Reset enable, =enable. 3FFFh. LVRE: Low Voltage Reset enable, =enable. SFR 97h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 SWCMD IAPALL / SWRST W Reset 0 97h.7~0 SWRST (W): Write 56h to generate S/W Reset. SFR F8h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 AUX CLRWDT CLRTM3 STPRFC DPSEL Reset F8h.3 CLRWDT: Set to to clear Watch Dog Timer. SFR 9h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 OPTION CMPO CMPVS UARTW WDTPSC TM3PSC R Reset h. WDTPSC: WDT Prescaler. 0: WDT overflow at System clock count : WDT overflow at 3768 System clock count DS-TM5F60_E Rev 0.90, 05/0/07

25 TM5F60 Data Sheet 5. Clock Circuitry & Operation Mode 5. System Clock The F60 is designed with dual-clock system. During runtime, user can directly switch the System clock from fast to slow or from slow to fast. It also can directly select a clock divider of,, 6 or 6. The Fast clock is fixed to FRC (Fast Internal RC, 3.75MHz at V DD =3V). The Slow clock can be selected as SXT (Slow Crystal, 3KHz) or RFC (oscillation with external R and C). Fast mode and Slow mode are defined as the CPU running at Fast and Slow clock speeds. After Reset, V DD =V BAT and the device is running at Fast mode with 3.75MHz FRC. If user set the PWRSAV bit, V DD drops to.v~.9v, and the FRC clock frequency also reduces with the V DD voltage level. The lower V DD level makes the lower FRC frequency. In typical condition, FRC=.5MHz at V DD =.5V. SXT is the default Slow clock type. Before entering the Slow mode, software must select the Slow clock type in advance. If RFC is used as the Slow clock source, software also has to setup the pin mode and RFC related SFRs in advance. Since Fast clock is useless in Slow mode, software can set the STPFCK bit (after SELFCK=0) to stop Fast clock and reduce chip current consumption. Clock Structure The CLKCON SFR controls the System clock operating. H/W automatically blocks the S/W abnormally setting for this register. S/W can only change the Slow Clock type in Fast mode. Never to write both STPFCK= & SELFCK=. It is recommended to write this SFR bit by bit. DS-TM5F60_E 5 Rev 0.90, 05/0/07

26 TM5F60 Data Sheet SFR D8h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 CLKCON SCKTYPE SXTGAIN STPPCK STPFCK SELFCK CLKPSC Reset D8h.7 SCKTYPE: Slow clock Type. This bit can be changed only in Fast mode (SELFCK=). 0: SXT : RFC, S/W must setup RFC oscillating circuitry before set this bit to D8h.6~5 SXTGAIN: 3768 SXT oscillator gain, 3=Highest gain, 0=Lowest gain. Higher gain can shorten the Crystal oscillation warm-up time. Lower gain can reduce oscillation current. D8h. STPPCK: Set to stop UART/Timer0/Timer/Timer clock in Idle mode for current reducing. D8h.3 STPFCK: Set to stop Fast clock for power saving in Slow/Idle mode. This bit can be changed only in Slow mode. D8h. SELFCK: System clock source selection. This bit can be changed only when STPFCK=0. 0: Slow clock : Fast clock D8h.~0 CLKPSC: System clock prescaler. 00: System clock is Fast/Slow clock divided by 6 0: System clock is Fast/Slow clock divided by 6 0: System clock is Fast/Slow clock divided by : System clock is Fast/Slow clock divided by CLKCON (D8h) SYSCLK bit7 bit3 Bit SCKTYPE STPFCK SELFCK Slow SXT 0 0/ 0 Slow RFC (*) 0/ 0 Fast FRC 0/ 0 Slow type change 0 0 Stop FRC 0/ 0 0 Switch to fast FRC 0/ 0 0 Switch to slow SRC/RFC 0/ 0 0 (*) also need RFC related SFRs proper setting This device can also output the System clock to TCO pin (in CMOS format). TCO s frequency/duty is defined by TCOCON SFR. TCO pin s output enable is defined by P3MOD7 SFR (see section 7). SFR A6h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TOCON TOCON TOCON TCOCON Reset A6h.~0 TCOCON: TCO pin duty and frequency control 000: / duty, / SYSCLK frequency 00: /3 duty, /3 SYSCLK frequency 00: / duty, / SYSCLK frequency 0: / duty, / SYSCLK frequency 00: / duty, / SYSCLK frequency 0: /3 duty, /3 SYSCLK frequency 0: 3/ duty, / SYSCLK frequency : 3/ duty, / SYSCLK frequency DS-TM5F60_E 6 Rev 0.90, 05/0/07

27 TM5F60 Data Sheet TCO waveform with TCOCON 5. Operation Modes There are four operation modes for this device. Fast Mode is defined as the CPU running at Fast clock speed. Slow Mode is defined as the CPU running at Slow clock speed. When the System clock speed is lower, the power consumption is lower. Idle Mode is entered by setting the IDL bit in PCON SFR. Both Fast and Slow clock can be set as the System clock source in Idle Mode, but Slow clock is better for power saving. In Idle mode, the CPU puts itself to sleep while the on-chip peripherals stay active. The STPPCK bit in CLKCON SFR can be set to furthermore reduce Idle mode current. If STPPCK=, Timer0// and UART are stopped in Idle mode. The slower System clock rate also helps current saving. It can be achieved by setup the CLKPSC SFR to divide System clock frequency. Idle mode is terminated by Reset or enabled Interrupts wake up. Stop Mode is entered by setting the PD bit in PCON SFR. This mode is the so-called Power Down mode in standard 805. In Stop mode, all clocks stop. Stop Mode can be terminated by Reset or pin wake up. SFR 87h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 PCON SMOD GF GF0 PD IDL Reset h. PD: Power down control bit, set to enter STOP mode. 87h.0 IDL: Idle mode control bit, set to enter IDLE mode. DS-TM5F60_E 7 Rev 0.90, 05/0/07

28 TM5F60 Data Sheet 6. Interrupt & Wake-up The F60 has an 9-source four-level priority interrupt structure. All enabled Interrupts can wake up CPU from Idle mode, but only the Pin Interrupts can wake up CPU from Stop mode. Each interrupt source has its own enable control bit. An interrupt event will set its individual Interrupt Flag, no matter its interrupt enable control bit is 0 or. The Interrupt vectors and flags are list below. Vector Flag Description 0003 IE0 INT0 external pin Interrupt (can wake up Stop mode) 000B TF0 Timer0 Interrupt 003 IE INT external pin Interrupt (can wake up Stop mode) 00B TF Timer Interrupt 003 RI+TI Serial Port (UART) Interrupt 00B TF+EXF Timer Interrupt 0033 Reserved for ICE mode use 003B TF3 Timer3 Interrupt 003 PIF Port external pin change Interrupt (can wake up Stop mode) 00B IE INT external pin Interrupt (can wake up Stop mode) Interrupt Vector & Flag 6. Interrupt Enable and Priority Control The IE and INTE SFRs decide whether the pending interrupt is serviced by CPU. The PWKUP SFR controls the individual Port pin s wake-up and interrupt capability. The IP, IPH, IP and IPH SFRs decide the interrupt priority. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed. SFR 96h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 PWKUP PWKUP Reset h.7~0 PWKUP: P.7~P.0 pin individual Wake-up / Interrupt enable control 0: Disable : Enable DS-TM5F60_E 8 Rev 0.90, 05/0/07

29 TM5F60 Data Sheet SFR A8h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 IE EA ET ES ET EX ET0 EX0 Reset A8h.7 EA: Global interrupt enable control. 0: Disable all Interrupts. : Each interrupt is enabled or disabled by its individual interrupt control bit A8h.5 ET: Timer interrupt enable 0: Disable Timer interrupt : Enable Timer interrupt A8h. ES: Serial Port (UART) interrupt enable 0: Disable Serial Port (UART) interrupt : Enable Serial Port (UART) interrupt A8h.3 ET: Timer interrupt enable 0: Disable Timer interrupt : Enable Timer interrupt A8h. EX: External INT pin Interrupt enable and Stop mode wake up enable 0: Disable INT pin Interrupt and Stop mode wake up : Enable INT pin Interrupt and Stop mode wake up, it can wake up CPU from Stop mode no matter EA is 0 or. A8h. ET0: Timer0 interrupt enable 0: Disable Timer0 interrupt : Enable Timer0 interrupt A8h.0 EX0: External INT0 pin Interrupt enable and Stop mode wake up enable 0: Disable INT0 pin Interrupt and Stop mode wake up : Enable INT0 pin Interrupt and Stop mode wake up, it can wake up CPU from Stop mode no matter EA is 0 or. SFR A9h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 INTE EX PIE TM3IE Reset A9h. EX: External INT pin Interrupt enable and Stop mode wake up enable 0: Disable INT pin Interrupt and Stop mode wake up : Enable INT pin Interrupt and Stop mode wake up, it can wake up CPU from Stop mode no matter EA is 0 or. A9h. PIE: Port pin change interrupt enable. This bit does not affect the Port pin s Stop mode wake up capability. 0: Disable Port pin change interrupt : Enable Port pin change interrupt A9h.0 TM3IE: Timer3 interrupt enable 0: Disable Timer3 interrupt : Enable Timer3 interrupt DS-TM5F60_E 9 Rev 0.90, 05/0/07

30 TM5F60 Data Sheet SFR B9h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 IPH PTH PSH PTH PXH PT0H PX0H Reset SFR B8h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 IP PT PS PT PX PT0 PX0 Reset B9h.5, B8h.5 B9h., B8h. B9h.3, B8h.3 B9h., B8h. B9h., B8h. B9h.0, B8h.0 PTH, PT : Timer Interrupt Priority control. (PTH, PT)= : Level 3 (highest priority) 0: Level 0: Level 00: Level 0 (lowest priority) PSH, PS : Serial Port (UART) Interrupt Priority control. Definition as above. PTH, PT : Timer Interrupt Priority control. Definition as above. PXH, PX : External INT pin Interrupt Priority control. Definition as above. PT0H, PT0 : Timer0 Interrupt Priority control. Definition as above. PX0H, PX0 : External INT0 pin Interrupt Priority control. Definition as above. SFR BBh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 IPH PXH PPH PT3H Reset SFR BAh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 IP PX PP PT3 Reset BBh., BAh. BBh., BAh. BBh.0, BAh.0 PXH, PX : External INT pin Interrupt Priority control. Definition as above. PPH, PP : Port Pin Change Interrupt Priority control. Definition as above. PT3H, PT3 : Timer3 Interrupt Priority control. Definition as above. DS-TM5F60_E 30 Rev 0.90, 05/0/07

31 TM5F60 Data Sheet 6. Pin Interrupt Pin Interrupts include INT0 (P3.), INT (P3.3), INT (P.7) and Port Change Interrupt. These pins also have the Stop mode wake up capability. INT0 and INT are falling edge or low level triggered as the 805 standard. INT is falling edge triggered, while Port Change Interrupt is triggered by any Port pin state change. P.7 PWKUP[7] PIE P. INERRUPT PWKUP[] EA P.0 PWKUP[0] INT EX INT STOP_WAKE_UP EX INT0 EX0 Pin Interrupt & Wake up SFR 88h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TCON TF TR TF0 TR0 IE IT IE0 IT0 Reset h.3 IE: External Interrupt (INT pin) edge flag. Set by H/W when an INT pin falling edge is detected, no matter the EX is 0 or. It is cleared automatically when the program performs the interrupt service routine. 88h. IT: External Interrupt control bit 0: Low level active (level triggered) for INT pin : Falling edge active (edge triggered) for INT pin 88h. IE0: External Interrupt 0 (INT0 pin) edge flag Set by H/W when an INT0 pin falling edge is detected, no matter the EX0 is 0 or. It is cleared automatically when the program performs the interrupt service routine. 88h.0 IT0: External Interrupt 0 control bit 0: Low level active (level triggered) for INT0 pin : Falling edge active (edge triggered) for INT0 pin DS-TM5F60_E 3 Rev 0.90, 05/0/07

32 TM5F60 Data Sheet SFR 95h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 INTFLG IE PIF TF3 Reset h. IE: External Interrupt (INT pin) edge flag Set by H/W when a falling edge is detected on the INT pin, no matter the EX is 0 or. It is cleared automatically when the program performs the interrupt service routine. S/W can write FBh to INTFLG to clear this bit. 95h. PIF: Port pin change interrupt flag Set by H/W when a Port pin state change is detected and its interrupt enable bit is set (PWKUP). PIE does not affect this flag s setting. It is cleared automatically when the program performs the interrupt service routine. S/W can write FDh to INTFLG to clear this bit. Note: S/W can write 0 to clear a flag in the INTFLG, but writing has no effect. 6.3 Idle mode Wake up and Interrupt Idle mode is waked up by enabled Interrupts, which means individual interrupt enable bit (ex: EX0) and EA bit must be both set to to establish Idle mode wake up capability. All enabled Interrupts (Pins, Timers and UART) can wake up CPU from Idle mode. Upon Idle wake-up, Interrupt service routine is entered immediately. The first instruction behind IDL (PCON.0) setting is executed after interrupt service routine return. INST. CODE MOV PCON, #0h H/W FORCE NOP INTERRUPT SUB-ROUTINE RETI NX INST. SYSCLK IDLE P3. EA=EX0=, Idle mode wake-up and Interrupt by P3. (INT0) SFR 87h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 PCON SMOD GF GF0 PD IDL Reset h. PD: Power down control bit, set to enter STOP mode. 87h.0 IDL: Idle mode control bit, set to enter IDLE mode. 6. Stop mode Wake up and Interrupt Stop mode wake up is simple, as long as the individual pin interrupt enable bit (ex: EX0) is set, the pin wake up capability is asserted. Set EX0/EX/EX can enable INT0/INT/INT pins Stop mode wake up capability. Set PWKUP bit 7~0 can enable P.7~P.0 s Stop mode wake up capability. Upon Stop wake up, the first instruction behind PD setting (PCON.) is executed immediately before Interrupt service. Interrupt entry requires EA= (PWKUP also needs PIE=) and trigger state of the pin staying sufficiently long to be observed by the System clock. This feature allows CPU to enter or not enter Interrupt sub-routine after Stop mode wake up. Note: It is recommended to place the NX/NX with NOP Instruction in figures below. DS-TM5F60_E 3 Rev 0.90, 05/0/07

33 TM5F60 Data Sheet INST. CODE MOV PCON, #0h NX INST. (> Cycles) HOLD RUN INTERRUPT SUB-ROUTINE RETI NX INST. INST. CODE MOV PCON, #0h NX INST. ( Cycles) HOLD RUN NX INST. INTERRUPT SUB-ROUTINE RETI NX3 INST. SYSCLK STOP P3. WARM EA=EX0=, P3. (INT0) is sampled after warm-up, Stop mode wake-up and Interrupt INST. CODE MOV PCON, #0h NX INST. HOLD RUN INTERRUPT SUB-ROUTINE RETI NX INST. SYSCLK STOP P.0 WARM EA=PIE=PWKUP=, P.0 change (not need clock sample), Stop mode wake-up and Interrupt INST. CODE MOV PCON, #0h NX INST. HOLD RUN NX INST. NX3 INST. SYSCLK STOP P3. P.7 P.0 WARM EA=EX0=EX=PWKUP=, PIE=0, Stop mode wake-up but not Interrupt. P3./P.7 pulse too narrow INST. CODE MOV PCON, #0h NX INST. HOLD RUN NX INST. NX3 INST. SYSCLK STOP P3. P.7 P.0 WARM EX0=EX=PWKUP=PIE=, EA=0, Stop mode wake-up but not Interrupt DS-TM5F60_E 33 Rev 0.90, 05/0/07

34 TM5F60 Data Sheet 7. I/O Ports The F60 has total 5 multi-function I/O pins. All I/O pins follow the standard 805 Read-Modify- Write feature. The instructions that read the SFR rather than the Pin State are the ones that read a port or port bit value, possibly change it, and then rewrite it to the SFR. (ex: ANL P, A; INC P0; CPL P3.0) 7. Port & Port3 These pins can operate in four different modes as below. Mode Mode 0 Mode Mode Mode 3 Port, Port3 pin function P3.0~P3. Pseudo Open Drain Pseudo Open Drain CMOS Output Others Open Drain Open Drain Alternative Function, such as RFC and Clock output P.n / P3.n SFR data Pin State Resistor Pull-up Digital Input 0 Drive Low N N Pull-up Y Y 0 Drive Low N N Hi-Z N Y 0 Drive Low N N Drive High N N X (don t care) Port, Port3 I/O Pin Function Table N N If a Port or Port3 pin is used for Schmitt-trigger input, S/W must set the I/O pin to Mode0 or Mode and set the corresponding Port Data SFR to to disable the pin s output driving circuitry. Beside I/O port function, each Port and Port3 pin has one or more alternative functions, such as RFC and Clock output. Most of the functions are activated by setting the individual pin mode control SFR to Mode3. Port/Port3 pins also have standard 805 auxiliary definition such as INT0/, T0//, or RXD/TXD. These pin functions need to set the pin mode SFR to Mode0 or Mode and keep the P.n / P3.n SFR at. Pin Name 805 Wake-up CKO RFC Mode3 P.0 T Y TO TO P. TEX Y P. Y P.3 Y P. Y RFC0R RFC0R P.5 Y RFCR RFCR P.6 Y RFCR RFCR P.7 Y RFCX RFCX P3.0 RXD P3. TXD P3. INT0 Y P3.3 INT Y P3. T0 P3.5 T TO TO P3.6 TB TB P3.7 TCO TCO Port, Port3 multi-function Table DS-TM5F60_E 3 Rev 0.90, 05/0/07

35 TM5F60 Data Sheet The necessary SFR setting for Port/Port3 pin s alternative functions is list below. Alternative Function T0, T, T, TEX, INT0, INT Mode P.n / P3.n SFR data Pin State 0 Input with Pull-up Input 0 Input with Pull-up / Pseudo Open Drain Output RXD, TXD Input / Pseudo Open Drain Output TCO, TO, TB, TO 3 X Clock Output (CMOS Push-Pull) RFCX, RFC0R~RFCR 3 X RFC clock oscillating Mode Setting for Port, Port3 Alternative Function For tables above, a CMOS Output pin means it can sink and drive at least ma current. It is not recommended to use such pin as input function. An Open Drain pin means it can sink at least ma current but only drive a small current (< 0uA). It can be used as input or output function and typically needs an external pull up resistor. An 805 standard pin is a "Pseudo Open Drain pin. It can sink at least ma current when output is at low level, and drives at least ma current for ~ clock cycle when output transits from low to high, then keeps driving a small current (< 0uA) to maintain the pin at high level. It can be used as input or output function. P.0 Pin Structure DS-TM5F60_E 35 Rev 0.90, 05/0/07

36 TM5F60 Data Sheet P. Pin Structure P3.0 Pin Structure SFR 90h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 P P.7 P.6 P.5 P. P.3 P. P. P.0 Reset 90h.7~0 P: Port data DS-TM5F60_E 36 Rev 0.90, 05/0/07

37 TM5F60 Data Sheet SFR B0h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 P3 P3.7 P3.6 P3.5 P3. P3.3 P3. P3. P3.0 Reset B0h.7~0 P3: Port3 data SFR Ah Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 PMODL PMOD3 PMOD PMOD PMOD0 Reset Ah.7~6 PMOD3: P.3 pin control. 00: Mode0 0: Mode 0: Mode : not used Ah.5~ PMOD: P. pin control. 00: Mode0 0: Mode 0: Mode : not used Ah.3~ PMOD: P. pin control. 00: Mode0 0: Mode 0: Mode : not used Ah.~0 PMOD0: P.0 pin control. 00: Mode0 0: Mode 0: Mode : Mode3, P.0 is Timer overflow divided by /3/ (TO) CMOS push pull output. SFR A3h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 PMODH PMOD7 PMOD6 PMOD5 PMOD Reset A3h.7~6 PMOD7: P.7 pin control. 00: Mode0 0: Mode 0: Mode : Mode3, P.7 is RFC clock input pin (RFCX) A3h.5~ PMOD6: P.6 pin control. 00: Mode0 0: Mode 0: Mode : Mode3, P.6 is RFC resistor connection pin (RFCR) A3h.3~ PMOD5: P.5 pin control. 00: Mode0 0: Mode 0: Mode : Mode3, P.5 is RFC resistor connection pin (RFCR) A3h.~0 PMOD: P. pin control. 00: Mode0 0: Mode 0: Mode : Mode3, P. is RFC resistor connection pin (RFC0R) DS-TM5F60_E 37 Rev 0.90, 05/0/07

38 TM5F60 Data Sheet SFR Ah Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 P3MODL P3MOD3 P3MOD P3MOD P3MOD0 Reset Ah.7~6 P3MOD3: P3.3 pin control. 00: Mode0 0: Mode 0: Mode : not used Ah.5~ P3MOD: P3. pin control. 00: Mode0 0: Mode 0: Mode : not used Ah.3~ P3MOD: P3. pin control. 00: Mode0 0: Mode 0: Mode : not used Ah.~0 P3MOD0: P3.0 pin control. 00: Mode0 0: Mode 0: Mode : not used SFR A5h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 P3MODH P3MOD7 P3MOD6 P3MOD5 P3MOD Reset A5h.7~6 P3MOD7: P3.7 pin control. 00: Mode0 0: Mode 0: Mode : Mode3, P3.7 is SYSCLK divided by //3/ (TCO) CMOS push pull output. A5h.5~ P3MOD6: P3.6 pin control. 00: Mode0 0: Mode 0: Mode : Mode3, P3.6 is Negative Timer overflow divided by /3/ (TB) CMOS push pull output. A5h.3~ P3MOD5: P3.5 pin control. 00: Mode0 0: Mode 0: Mode : Mode3, P3.5 is Positive Timer overflow divided by /3/ (TO) CMOS push pull output. A5h.~0 P3MOD: P3. pin control. 00: Mode0 0: Mode 0: Mode : not used DS-TM5F60_E 38 Rev 0.90, 05/0/07

39 TM5F60 Data Sheet 7. P.7 P.7 can be only used as Schmitt-trigger input or open-drain output, with pull-up resistor always enable. P.7 pin is shared with RSTn, INT and Flash VPP function. 7.3 Port0 Port0 pins are shared with LCD segment pins. The pin s LCD mode is controlled by P0SEG SFR. If a Port0 pin is defined as I/O pin, it can be used as CMOS push-pull output or Schmitt-trigger input. The pin s pull up function is enable while SFR bit P0OE.n=0 and P0.n=. Port0 pin function P0OE.n P0.n SFR data Pin State Resistor Pull-up Digital Input Input CMOS Output 0 0 Hi-Z N Y 0 Pull-up Y Y 0 Drive Low N N Drive High N N Port0 I/O Pin Function Table P0.0 Pin Structure DS-TM5F60_E 39 Rev 0.90, 05/0/07

40 TM5F60 Data Sheet SFR 80h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 P0 P0.7 P0.6 P0.5 P0. P0.3 P0. P0. P0.0 Reset 80h.7~0 P0: Port0 data, also controls the P0.n pin s pull-up function. If the P0.n SFR data is and the corresponding P0OE.n=0 (input mode), the pull-up is enabled. SFR A0h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 P P.7 P.6 P.5 P. P.3 P. P. P.0 Reset A0h.7 P.7: P.7 data, 0=Open Drain output low, =Schmitt-trigger input with pull up A0h.6~0 P.6~P.0: General purpose register. SFR 9h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 P0OE P0OE Reset h.7~0 P0OE: Port0 CMOS Push-Pull output enable control, =Enable. SFR Bh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 LCON DSPON LCDCLK LCDFMR LCDUTY P0SEG Reset Bh.~0 P0SEG: Port0 LCD mode control. 000: P0.0~P0.7 are I/O pins 00: P0.0~P0.5 are I/O pins, P0.6~P0.7 are LCD Segment pins 00: P0.0~P0. are I/O pins, P0.5~P0.7 are LCD Segment pins 0: P0.0~P0.3 are I/O pins, P0.~P0.7 are LCD Segment pins 00: P0.0~P0. are I/O pins, P0.3~P0.7 are LCD Segment pins 0: P0.0~P0. are I/O pins, P0.~P0.7 are LCD Segment pins 0: P0.0 is I/O pin, P0.~P0.7 are LCD Segment pins : P0.0~P0.7 are LCD Segment pins DS-TM5F60_E 0 Rev 0.90, 05/0/07

41 TM5F60 Data Sheet 8. Timers Timer0, Timer and Timer are provided as standard 805 compatible timer/counter. Timer3 is provided for a real-time clock count. Compare to the traditional T 805, the chip's Timer0// use System clock cycle as the time base unit. That is, in timer mode, these timers increase at every System clock rate; in counter mode, T0/T/T pin input pulse must be wider than System clock to be seen by this device. In addition to the standard 805 timers function, the TO and TB pin can output the positive and negative Timer overflow divided by /3/ signal, and the TO pin can output the Timer overflow divided by /3/ signal. These outputs can be used for Buzzer application. Timer0 s extra utility is to supports RFC. The RFC clock divided by //6/6 signal can replace T0 pin as the Timer0 s event count input. 8. Timer0 / Timer TCON and TMOD are used to set the mode of operation and to control the running and interrupt generation of the Timer0/, with the timer/counter values stored in two pairs of 8-bit registers (TL0, TH0, and TL, TH). SFR 88h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TCON TF TR TF0 TR0 IE IT IE0 IT0 Reset h.7 TF: Timer overflow flag Set by H/W when Timer/Counter overflows Cleared by H/W when CPU vectors into the interrupt service routine. 88h.6 TR: Timer run control 0: Timer stops : Timer runs 88h.5 TF0: Timer0 overflow flag Set by H/W when Timer/Counter 0 overflows Cleared by H/W when CPU vectors into the interrupt service routine. 88h. TR0: Timer0 run control 0: Timer0 stops : Timer0 runs SFR 89h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TMOD GATE CTN TMOD GATE0 CT0N TMOD0 Reset h.7 GATE: Timer gating control bit 0: Timer enable when TR bit is set : Timer enable only while the INT pin is high and TR bit is set 89h.6 CTN: Timer Counter/Timer select bit 0: Timer mode, Timer data increases at System clock cycle rate : Counter mode, Timer data increases at T pin s negative edge 89h.5~ TMOD: Timer mode select 00: 8-bit timer/counter (TH) and 5-bit prescaler (TL) 0: 6-bit timer/counter 0: 8-bit auto-reload timer/counter (TL). Reloaded from TH at overflow. : Timer stops DS-TM5F60_E Rev 0.90, 05/0/07

42 TM5F60 Data Sheet 89h.3 GATE0: Timer0 gating control bit 0: Timer0 enable when TR0 bit is set : Timer0 enable only while the INT0 pin is high and TR0 bit is set 89h. CT0N: Timer0 Counter/Timer select bit 0: Timer mode, Timer0 data increases at System clock cycle rate : Counter mode, Timer0 data increases at T0 pin s negative edge 89h.~0 TMOD0: Timer0 mode select 00: 8-bit timer/counter (TH0) and 5-bit prescaler (TL0) 0: 6-bit timer/counter 0: 8-bit auto-reload timer/counter (TL0). Reloaded from TH0 at overflow. : TL0 is an 8-bit timer/counter. TH0 is an 8-bit timer/counter using Timer s TR and TF bits. SFR 8Ah Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TL0 TL0 Reset Ah.7~0 TL0: Timer0 data low byte SFR 8Bh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TL TL Reset Bh.7~0 TL: Timer data low byte SFR 8Ch Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TH0 TH0 Reset Ch.7~0 TH0: Timer0 data high byte SFR 8Dh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TH TH Reset Dh.7~0 TH: Timer data high byte SFR AFh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 RFCON T0RFC RFCPSC RFCS Reset AFh. T0RFC: Timer0 Counter mode (CT0N=) input select 0: T0 (P3.) pin : RFC Clock divided by //6/6 AFh.3~ RFCPSC: RFC clock divider to Timer0 00: divided by 6 0: divided by 6 0: divided by : divided by DS-TM5F60_E Rev 0.90, 05/0/07

43 TM5F60 Data Sheet 8. Timer Timer is controlled through the TCON register with the low and high bytes of Timer/Counter stored in TL and TH and the low and high bytes of the Timer reload/capture registers stored in RCAPL and RCAPH. SFR C8h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TCON TF EXF RCLK TCLK EXEN TR CTN CPRLN Reset C8h.7 TF: Timer overflow flag Set by H/W when Timer/Counter overflows unless RCLK= or TCLK=. This bit must be cleared by S/W. C8h.6 EXF: TEX interrupt pin falling edge flag Set when a capture or a reload is caused by a negative transition on TEX pin if EXEN=. This bit must be cleared by S/W. C8h.5 RCLK: UART receive clock control bit 0: Use Timer overflow as receive clock for serial port in mode or 3 : Use Timer overflow as receive clock for serial port in mode or 3 C8h. TCLK: UART transmit clock control bit 0: Use Timer overflow as transmit clock for serial port in mode or 3 : Use Timer overflow as transmit clock for serial port in mode or 3 C8h.3 EXEN: TEX pin enable 0: TEX pin disable : TEX pin enable, it cause a capture or reload when a negative transition on TEX pin is detected if RCLK=TCLK=0 C8h. TR: Timer run control 0: Timer stops : Timer runs C8h. CTN: Timer Counter/Timer select bit 0: Timer mode, Timer data increases at System clock cycle rate : Counter mode, Timer data increases at T pin s negative edge C8h.0 CPRLN: Timer Capture/Reload control bit 0: Reload mode, auto-reload on Timer overflows or negative transitions on TEX pin if EXEN=. : Capture mode, capture on negative transitions on TEX pin if EXEN=. If RCLK= or TCLK=, CPRLN is ignored and timer is forced to auto-reload on Timer overflow. SFR CAh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 RCPL RCPL Reset CAh.7~0 RCPL: Timer reload/capture data low byte SFR CBh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 RCPH RCPH Reset CBh.7~0 RCPH: Timer reload/capture data high byte DS-TM5F60_E 3 Rev 0.90, 05/0/07

44 TM5F60 Data Sheet SFR CCh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TL TL Reset CCh.7~0 TL: Timer data low byte SFR CDh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TH TH Reset CDh.7~0 TH: Timer data high byte 8.3 Timer3 The 3-bit wide Timer3 is reloadable for its 8-bit MSB when overflow. Its time base is 3768Hz SXT clock. Timer3 can generate interrupt periodically at different rate, and its counting data can be read out by CPU. However, while CPU clock is switched to FRC or RFC, the clock source of CPU and Timer3 are different, CPU may read a under changing Timer3 data. User F/W must have some filter mechanism to avoid such kind un-stability. On the contrast, Timer3 interrupt has no ambiguous behavior no matter what the CPU clock source is. Timer3 can control its counting rate by the TM3ADJ SFR. This feature compensates the 3768 SXT crystal s in-accuracy. While TM3ADJ=0, Timer3 increase its data count normally at each SXT clock cycle. If TM3ADJ is set to positive adjustment, Timer3 increase its data count by in particular SXT cycles, resulting a faster counting rate. If TM3ADJ is set to negative adjustment, Timer3 stop increase in particular SXT cycles, resulting a slower counting rate. The adjustment is 0.77ppm per step, and the total adjustable range is ± 6ppm. Timer3 Structure SFR F8h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 AUX CLRWDT CLRTM3 STPRFC DPSEL Reset F8h. CLRTM3: Set to Clear Timer3 DS-TM5F60_E Rev 0.90, 05/0/07

45 TM5F60 Data Sheet SFR 9h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 OPTION CMPO CMPVS UARTW WDTPSC TM3PSC R Reset h.~0 TM3PSC: Timer3 Interrupt rate 00: Timer3 interrupt occurs when 3 bit count data overflow 0: Timer3 interrupt is.0 second rate (3768 SXT cycles) 0: Timer3 interrupt is 0.5 second rate (638 SXT cycles) : Timer3 interrupt is 0.5 second rate (89 SXT cycles) SFR 95h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 INTFLG IE PIF TF3 Reset h.0 TF3: Timer3 Interrupt Flag Set by H/W when Timer3 reaches TM3PSC setting cycles. Cleared automatically when the program performs the interrupt service routine. S/W can write FEh to INTFLG to clear this bit. (Note) SFR B3h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TM3SEC TM3SEC R Reset B3h.7~0 TM3SEC: Timer3 count data bit ~5 SFR Bh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TM3DL TM3DL R Reset Bh.7~0 TM3DL: Timer3 count data bit 7~0 SFR B5h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TM3DH TM3DH R Reset B5h.6~0 TM3DH: Timer3 count data bit ~8 SFR B6h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TM3RLD TM3RLD Reset B6h.7~0 TM3RLD: Timer3 overflow reload data for Timer3 bit ~5 (TM3SEC) SFR B7h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TM3ADJ TM3ADJS TM3ADJ Reset B7h.7 TM3ADJS: Timer3 adjustment sign 0: Timer3 positive adjust, to increase Timer3 counting rate : Timer3 negative adjust, to decrease Timer3 counting rate B7h.6~0 TM3ADJ: Timer3 adjust magnitude, 0.77 ppm per LSB. The adjustment is calculated as ±TM3ADJ*0.77ppm. The total adjustable range is ± 6ppm. DS-TM5F60_E 5 Rev 0.90, 05/0/07

46 TM5F60 Data Sheet 8. TO, TB and TO output Control This device can generate various frequency or duty cycle waveform output (in CMOS push pull format) for Buzzer or Remote IR control application. The TO, TB and TO waveform is derived by Timer / Timer overflow signal. User can control their frequency by Timers auto reload value, as well as set their duty cycle by TOCON SFR. The pin output function is enabled by setting the P3MODH SFR to Mode3 for each pin (see Section 7). TO, TB waveform with TOCON TO waveform with TOCON SFR A6h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 TOCON TOCON TOCON TCOCON Reset A6h.7~6 TOCON: TO pin duty and frequency control 00: / duty, / Timer overflow frequency 0: /3 duty, /3 Timer overflow frequency 0: / duty, / Timer overflow frequency A6h.5~3 TOCON: TO pin duty and frequency control 000: / duty, / Timer overflow frequency 00: /3 duty, /3 Timer overflow frequency 00: / duty, / Timer overflow frequency 0: /3 duty, /3 Timer overflow frequency 0: 3/ duty, / Timer overflow frequency Note6: also refer to Section 6 for more information about Timer0///3 Interrupt enable and priority. DS-TM5F60_E 6 Rev 0.90, 05/0/07

47 TM5F60 Data Sheet 9. UART The UART uses SCON and SBUF SFRs. SCON is the control register, SBUF is the data register. Data is written to SBUF for transmission and SBUF is read to obtain received data. The received data and transmitted data registers are completely independent. In addition to standard 805 s full duplex mode, this chip also provides one wire mode. If the UARTW bit is set, both transmit and receive data use P3. pin. SFR 87h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 PCON SMOD GF GF0 PD IDL Reset h.7 SMOD: UART double baud rate control bit 0: Disable UART double baud rate : Enable UART double baud rate SFR 9h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 OPTION CMPO CMPVS UARTW WDTPSC TM3PSC R Reset h.3 UARTW: One wire UART mode enable, both TXD/RXD use P3. pin 0: Disable one wire UART mode : Enable one wire UART mode SFR 98h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 SCON SM0 SM SM REN TB8 RB8 TI RI Reset h.7~6 SM0,SM: Serial port mode select bit 0, 00: Mode0: 8 bit shift register, Baud Rate = F SYSCLK / 0: Mode: 8 bit UART, Baud Rate is variable 0: Mode: 9 bit UART, Baud Rate = F SYSCLK / 3 or / 6 : Mode3: 9 bit UART, Baud Rate is variable 98h.5 SM: Serial port mode select bit SM enables multiprocessor communication over a single serial line and modifies the above as follows. In Modes & 3, if SM is set then the received interrupt will not be generated if the received ninth data bit is 0. In Mode, the received interrupt will not be generated unless a valid stop bit is received. In Mode 0, SM should be 0. 98h. REN: UART reception enable 0: Disable reception : Enable reception 98h.3 TB8: Transmit Bit 8, the ninth bit to be transmitted in Mode and 3 98h. RB8: Receive Bit 8, contains the ninth bit that was received in Mode and 3 or the stop bit in Mode if SM=0 98h. TI: Transmit interrupt flag Set by H/W at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in other modes. Must be cleared by S/W. 98h.0 RI: Receive interrupt flag Set by H/W at the end of the eighth bit in Mode 0, or at the sampling point of the stop bit in other modes. Must be cleared by S/W. DS-TM5F60_E 7 Rev 0.90, 05/0/07

48 TM5F60 Data Sheet SFR 99h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 SBUF SBUF Reset 99h.7~0 SBUF: UART transmit and receive data. Transmit data is written to this location and receive data is read from this location, but the paths are independent. F SYSCLK denotes System clock frequency, the UART baud rate is calculated as below. Mode 0: Baud Rate = F SYSCLK / Mode, 3: if using Timer auto reload mode Baud Rate = (SMOD + ) x F SYSCLK / (3 x x (56 TH)) Mode, 3: if using Timer Baud Rate = Timer overflow rate / 6 = F SYSCLK / (3 x (65536 RCPH, RCPL)) Mode : Baud Rate = (SMOD + ) x F SYSCLK / 6 Note6: also refer to Section 6 for more information about UART Interrupt enable and priority. Note8: also refer to Section 8 for more information about how Timer controls UART clock. DS-TM5F60_E 8 Rev 0.90, 05/0/07

49 TM5F60 Data Sheet 0. Resistance to Frequency Converter (RFC) The RFC module can build the RC oscillation circuitry with RFCX pin and RFC0R, RFCR or RFCR pins. Only one RC oscillation circuitry is active at a time. There are methods to measure the RFC clock frequency. One is to set the RFC as the Timer0 Counter mode input, the other one is to set RFC as the SYSCLK and assign Timer0, or running with timer mode. Since Timer3 s clock source is the precise 3768 SXT, compare the Timer which running by RFC with Timer3 s data/interrupt, user can derive the RFC frequency. RFC Structure SFR AFh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 RFCON T0RFC RFCPSC RFCS Reset AFh. T0RFC: Timer0 Counter mode (CT0N=) input select 0: T0 (P3.) pin : RFC Clock divided by //6/6 AFh.3~ RFCPSC: RFC clock divider to Timer0 00: divided by 6 0: divided by 6 0: divided by : divided by AFh.~0 RFCS: Select RFC convert channel. 00: RFC0R (P.) 0: RFCR (P.5) 0: RFCR (P.6) SFR F8h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 AUX CLRWDT CLRTM3 STPRFC DPSEL Reset F8h. STPRFC: Set to stop RFC clock oscillating DS-TM5F60_E 9 Rev 0.90, 05/0/07

50 TM5F60 Data Sheet SFR D8h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 CLKCON SCKTYPE SXTGAIN STPPCK STPFCK SELFCK CLKPSC Reset D8h.7 SCKTYPE: Slow clock Type. This bit can be changed only in Fast mode (SELFCK=). 0: SXT : RFC, Software must setup RFC oscillating circuitry before set this bit to. SFR A3h Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 PMODH PMOD7 PMOD6 PMOD5 PMOD Reset A3h.7~6 PMOD7: P.7 pin control. 00: Mode0 0: Mode 0: Mode : Mode3, P.7 is RFC clock input pin (RFCX) A3h.5~ PMOD6: P.6 pin control. 00: Mode0 0: Mode 0: Mode : Mode3, P.6 is RFC resistor connection pin (RFCR) A3h.3~ PMOD5: P.5 pin control. 00: Mode0 0: Mode 0: Mode : Mode3, P.5 is RFC resistor connection pin (RFCR) A3h.~0 PMOD: P. pin control. 00: Mode0 0: Mode 0: Mode : Mode3, P. is RFC resistor connection pin (RFC0R) DS-TM5F60_E 50 Rev 0.90, 05/0/07

51 TM5F60 Data Sheet. LCD Driver The LCD Driver is capable of driving the LCD panel with maximum dots by Commons and 36 Segments. The VL/VL LCD Bias voltage is divided from V BAT by 3 identical resistors. Therefore, the VL and VL voltage level always equal to V BAT /3 and V BAT */3. The LCD Clock can be driven by SXT or FRC. If SXT is the clock source, the LCD Frame rate ranges from 3Hz to 98Hz depends on LCD Duty and LCDFRM. If FRC is the LCD clock source, the V DD voltage level would affect the FRC frequency and LCD Frame rate. The LCDRAM is located in the 805 s External Data Memory space, addressing from F000h to F0h. VBAT OP VL 0.uF DSPON OP VL 0.uF LCD Driver Structure LCD Frame Rate (Hz) LCDFMR (SFR Bh.5~) /3 Duty / Duty LCD Frame Rate when LCDCLK=SXT DS-TM5F60_E 5 Rev 0.90, 05/0/07

52 TM5F60 Data Sheet SFR Bh Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 LCON DSPON LCDCLK LCDFMR LCDUTY P0SEG Reset Bh.7 DSPON: LCD display enable control 0: LCD disable : LCD enable Bh.6 LCDCLK: LCD clock source 0: SXT : FRC/6 Bh.5~ LCDFMR: LCD Frame rate control. If LCDCLK=0, SXT is the LCD clock source, the accurate LCD frame rate is listed in the table above. If LCDCLK=, FRC provides LCD clock source, user should consider the FRC s frequency variation with V DD voltage. Bh.3 LCDUTY: LCD Duty control 0: /3 Duty : / Duty Bh.~0 P0SEG: Port0 LCD mode control. 000: P0.0~P0.7 are I/O pins 00: P0.0~P0.5 are I/O pins, P0.6~P0.7 are LCD Segment pins 00: P0.0~P0. are I/O pins, P0.5~P0.7 are LCD Segment pins 0: P0.0~P0.3 are I/O pins, P0.~P0.7 are LCD Segment pins 00: P0.0~P0. are I/O pins, P0.3~P0.7 are LCD Segment pins 0: P0.0~P0. are I/O pins, P0.~P0.7 are LCD Segment pins 0: P0.0 is I/O pin, P0.~P0.7 are LCD Segment pins : P0.0~P0.7 are LCD Segment pins COM3 COM COM COM0 COM3 COM COM COM0 Adr bit7 Bit6 Bit5 Bit Bit3 Bit bit bit0 F000 SEG SEG SEG SEG SEG0 SEG0 SEG0 SEG0 F00 SEG3 SEG3 SEG3 SEG3 SEG SEG SEG SEG F00 SEG5 SEG5 SEG5 SEG5 SEG SEG SEG SEG F003 SEG7 SEG7 SEG7 SEG7 SEG6 SEG6 SEG6 SEG6 F00 SEG9 SEG9 SEG9 SEG9 SEG8 SEG8 SEG8 SEG8 F005 SEG SEG SEG SEG SEG0 SEG0 SEG0 SEG0 F006 SEG3 SEG3 SEG3 SEG3 SEG SEG SEG SEG F007 SEG5 SEG5 SEG5 SEG5 SEG SEG SEG SEG F008 SEG7 SEG7 SEG7 SEG7 SEG6 SEG6 SEG6 SEG6 F009 SEG9 SEG9 SEG9 SEG9 SEG8 SEG8 SEG8 SEG8 F00A SEG SEG SEG SEG SEG0 SEG0 SEG0 SEG0 F00B SEG3 SEG3 SEG3 SEG3 SEG SEG SEG SEG F00C SEG5 SEG5 SEG5 SEG5 SEG SEG SEG SEG F00D SEG7 SEG7 SEG7 SEG7 SEG6 SEG6 SEG6 SEG6 F00E SEG9 SEG9 SEG9 SEG9 SEG8 SEG8 SEG8 SEG8 F00F SEG3 SEG3 SEG3 SEG3 SEG30 SEG30 SEG30 SEG30 F00 SEG33 SEG33 SEG33 SEG33 SEG3 SEG3 SEG3 SEG3 F0 SEG35 SEG35 SEG35 SEG35 SEG3 SEG3 SEG3 SEG3 LCD RAM (External Data Memory) DS-TM5F60_E 5 Rev 0.90, 05/0/07

53 TM5F60 Data Sheet Frame V LCD SEG0 SEG SEG SEG3 COM0 /3 V LCD /3 V LCD V SS COM0 COM COM COM3 COM COM V LCD /3 V LCD /3 V LCD V SS V LCD /3 V LCD /3 V LCD V SS COM3 V LCD /3 V LCD /3 V LCD V SS SEG0 V LCD /3 V LCD /3 V LCD V SS SEG V LCD /3 V LCD /3 V LCD V SS COM0-SEG0 (ON) V LCD /3 V LCD /3 V LCD V SS -/3 V LCD -/3 V LCD -V LCD COM0-SEG (OFF) V LCD /3 V LCD /3 V LCD V SS -/3 V LCD -/3 V LCD -V LCD LCD Waveform, /3 Bias, / Duty, (VLCD=3*VL) DS-TM5F60_E 53 Rev 0.90, 05/0/07

54 TM5F60 Data Sheet. In Circuit Emulation (ICE) Mode The F60 can support the In Circuit Emulation Mode. To use the ICE Mode, user just needs to connect P. and P.3 pin to the tenx proprietary EV Module. The benefit is that user can emulate the whole system without changing the on board target device. But there are some limits for the ICE mode as below.. The device must be un-protect.. The device s P. and P.3 pins must work in input Mode (PMOD=0/ and PMOD3=0/). 3. During Program Code download, P.0 sent acknowledge signal to T-Link unit. After download stage, P.0 can be emulated as any other pins.. During Program Code download, P. always output Low. After download stage, P. can be emulated as any other pins. 5. The Program ROM s addressing space D00h~FFFh and 0033h~003Ah are occupied by tenx EV Module. So user Program cannot access these spaces. 6. The P. and P.3 pin s function cannot be emulated. 7. The V DD level and VCON SFR are controlled by EV module. ICE Mode Connection DS-TM5F60_E 5 Rev 0.90, 05/0/07

55 TM5F60 Data Sheet SFR & CFGW MAP Adr RST NAME Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 80h - P0 P0.7 P0.6 P0.5 P0. P0.3 P0. P0. P0.0 8h SP SP 8h DPL DPL 83h DPH DPH 87h 0xxx-0000 PCON SMOD GF GF0 PD IDL 88h TCON TF TR TF0 TR0 IE IT IE0 IT0 89h TMOD GATE CTN TMOD GATE0 CT0N TMOD0 8Ah TL0 TL0 8Bh TL TL 8Ch TH0 TH0 8Dh TH TH 90h - P P.7 P.6 P.5 P. P.3 P. P. P.0 9h P0OE P0OE 9h x OPTION CMPO CMPVS UARTW WDTPSC TM3PSC 95h xxxx-x000 INTFLG IE PIF TF3 96h PWKUP PWKUP 97h xxxx-xxx0 SWCMD IAPALL / SWRST 98h SCON SM0 SM SM REN TB8 RB8 TI RI 99h xxxx-xxxx SBUF SBUF A0h - P P.7 P.6 P.5 P. P.3 P. P. P.0 Ah PMODL PMOD3 PMOD PMOD PMOD0 A3h PMODH PMOD7 PMOD6 PMOD5 PMOD Ah P3MODL P3MOD3 P3MOD P3MOD P3MOD0 A5h P3MODH P3MOD7 P3MOD6 P3MOD5 P3MOD A6h TOCON TOCON TOCON TCOCON A7h x VCON PWRSAV VSET VSET A8h 0x IE EA ET ES ET EX ET0 EX0 A9h xxxx-x000 INTE EX PIE TM3IE AFh xxx0-00 RFCON T0RFC RFCPSC RFCS B0h - P3 P3.7 P3.6 P3.5 P3. P3.3 P3. P3. P3.0 Bh 000- LCON DSPON LCDCLK LCDFMR LCDUTY P0SEG B3h xxxx-xxxx TM3SEC TM3SEC Bh xxxx-xxxx TM3DL TM3DL B5h xxxx-xxxx TM3DH TM3DH B6h TM3RLD TM3RLD B7h TM3ADJ TM3ADJS TM3ADJ B8h xx IP PT PS PT PX PT0 PX0 B9h xx IPH PTH PSH PTH PXH PT0H PX0H BAh xxxx-x000 IP PX PP PT3 BBh xxxx-x000 IPH PXH PPH PT3H C8h TCON TF EXF RCLK TCLK EXEN TR CTN CPRLN CAh RCPL RCPL CBh RCPH RCPH CCh TL TL CDh TH TH D0h PSW CY AC F0 RS RS0 OV F P D8h 00-0 CLKCON SCKTYPE SXTGAIN STPPCK STPFCK SELFCK CLKPSC E0h ACC ACC.7 ACC.6 ACC.5 ACC. ACC.3 ACC. ACC. ACC.0 F0h B B.7 B.6 B.5 B. B.3 B. B. B.0 F8h xxxx-0000 AUX CLRWDT CLRTM3 STPRFC DPSEL Flash Address NAME Bit 7 Bit 6 Bit 5 Bit Bit 3 Bit Bit Bit 0 3FFEh CFGWL 3FFFh CFGWH PROT XRSTE MVCLOCK WDTE LVRE DS-TM5F60_E 55 Rev 0.90, 05/0/07

56 TM5F60 Data Sheet SFR & CFGW DESCRIPTION Adr SFR Bit# Bit Name Rst Description 80h P0 7~0 P0 Port0 data, also controls the P0.n pin s pull-up function. If the P0.n SFR data FFh is and the corresponding P0OE.n=0 (input mode), the pull-up is enabled. 8h SP 7~0 SP 07h Stack Point 8h DPL 7~0 DPL 00h Data Point low byte 83h DPH 7~0 DPH 00h Data Point high byte 7 SMOD 0 Set to enable UART double baud rate 3 GF 0 General purpose flag bit 87h PCON GF0 0 General purpose flag bit PD 0 Power down control bit, set to enter STOP mode 0 IDL 0 Idle control bit, set to enter IDLE mode 7 TF 0 Timer overflow flag Set by H/W when Timer/Counter overflows. Cleared by H/W when CPU vectors into the interrupt service routine. 6 TR 0 Timer run control. : timer runs; 0: timer stops 5 TF0 0 Timer0 overflow flag Set by H/W when Timer/Counter 0 overflows. Cleared by H/W when CPU vectors into the interrupt service routine. TR0 0 Timer0 run control. :timer runs; 0:timer stops External Interrupt (INT pin) edge flag 88h TCON 3 IE 0 Set by H/W when an INT pin falling edge is detected. Cleared by H/W when CPU vectors into the interrupt service routine. External Interrupt control bit IT 0 0: Low level active (level triggered) for INT pin : Falling edge active (edge triggered) for INT pin IE0 0 External Interrupt 0 (INT0 pin) edge flag Set by H/W when an INT0 pin falling edge is detected. Cleared by H/W when CPU vectors into the interrupt service routine. 0 IT0 0 External Interrupt 0 control bit 0: Low level active (level triggered) for INT0 pin : Falling edge active (edge triggered) for INT0 pin 7 GATE 0 Timer gating control bit 0: Timer enable when TR bit is set : Timer enable only while the INT pin is high and TR bit is set 6 CTN 0 Timer Counter/Timer select bit 0: Timer mode, Timer data increases at System clock cycle rate : Counter mode, Timer data increases at T pin s negative edge 5~ TMOD 00 Timer mode select 00: 8-bit timer/counter (TH) and 5-bit prescaler (TL) 0: 6-bit timer/counter 0: 8-bit auto-reload timer/counter (TL). Reloaded from TH at overflow. : Timer stops 89h TMOD Timer0 gating control bit 3 GATE0 0 0: Timer0 enable when TR0 bit is set : Timer0 enable only while the INT0 pin is high and TR0 bit is set CT0N 0 Timer0 Counter/Timer select bit 0: Timer mode, Timer0 data increases at System clock cycle rate : Counter mode, Timer0 data increases at T0 pin s negative edge ~0 TMOD0 00 Timer0 mode select 00: 8-bit timer/counter (TH0) and 5-bit prescaler (TL0) 0: 6-bit timer/counter 0: 8-bit auto-reload timer/counter (TL0). Reloaded from TH0 at overflow. : TL0 is an 8-bit timer/counter. TH0 is an 8-bit timer/counter using Timer s TR and TF bits. 8Ah TL0 7~0 TL0 00h Timer0 data low byte 8Bh TL 7~0 TL 00h Timer data low byte 8Ch TH0 7~0 TH0 00h Timer0 data high byte 8Dh TH 7~0 TH 00h Timer data high byte DS-TM5F60_E 56 Rev 0.90, 05/0/07

57 TM5F60 Data Sheet Adr SFR Bit# Bit Name Rst Description 90h P 7~0 P FFh Port data 9h P0OE 7~0 P0OE 00h Port0 CMOS Push-Pull output enable control, =Enable. 7 CMPO R Compare result of BandGap voltage and V BAT voltage divider. means the V BAT divider voltage is higher. Select V BAT resistor divider to compare with the.v BandGap reference. 000: Comparator Disable 00: the Comparator input is V BAT */5 00: the Comparator input is V BAT */6 6~ CMPVS 000 0: the Comparator input is V BAT */7 00: the Comparator input is V BAT */8 0: the Comparator input is V BAT */9 9h OPTION 0: the Comparator input is V BAT */30 : the Comparator input is V BAT */3 3 UARTW 0 Set to enable one wire UART mode, both TXD/RXD use P3. pin. WDTPSC 0 WDT Prescaler 0: WDT overflow at System clock count : WDT overflow at 3768 System clock count ~0 TM3PSC 0 Timer3 Interrupt rate 00: Timer3 interrupt occurs when 3 bit count data overflow 0: Timer3 interrupt is.0 second rate (3768 SXT cycles) 0: Timer3 interrupt is 0.5 second rate (638 SXT cycles) : Timer3 interrupt is 0.5 second rate (89 SXT cycles) External Interrupt (INT pin) edge flag IE 0 Set by H/W when a falling edge is detected on the INT pin, no matter the EX is 0 or. It is cleared automatically when the program performs the interrupt service routine. S/W can write FBh to INTFLG to clear this bit. 95h INTFLG PIF 0 Port pin change Interrupt flag Set by H/W when a Port pin state change is detected and its interrupt enable bit is set (PWKUP). PIE does not affect this flag s setting. It is cleared automatically when the program performs the interrupt service routine. S/W can write FDh to INTFLG to clear this bit. 0 TF3 0 Timer3 Interrupt Flag Set by H/W when Timer3 reaches TM3PSC setting cycles. It is cleared automatically when the program performs the interrupt service routine. S/W can write FEh to INTFLG to clear this bit. P.7~P.0 pin individual Wake-up / Interrupt enable control 96h PWKUP 7~0 PWKUP 00h 0: Disable : Enable 7~0 SWRST W Write 56h to generate S/W Reset 97h SWCMD 7~0 IAPALL W Write 65h to set IAPALL flag; Write other value to clear IAPALL flag. 0 IAPALL R 0 Flag indicates whole Flash can be access by IAP or not 7 SM0 0 Serial port mode select bit 0, (SM0, SM)= 00: Mode0: 8 bit shift register, Baud Rate = F SYSCLK / 0: Mode: 8 bit UART, Baud Rate is variable 6 SM 0 0: Mode: 9 bit UART, Baud Rate = F SYSCLK / 3 or / 6 : Mode3: 9 bit UART, Baud Rate is variable Serial port mode select bit 5 SM 0 In Modes /3, if SM is set then the received interrupt will not be generated if the received ninth bit is 0. In Mode, the received interrupt will not be generated unless a valid stop bit is received. In Mode 0, SM should be 0. 98h SCON REN 0 Set to enable UART Reception 3 TB8 0 Transmitter bit 8, ninth bit to transmit in Modes and 3 RB8 0 Receive Bit 8, contains the ninth bit that was received in Mode and 3 or the stop bit in Mode if SM=0 TI 0 Transmit Interrupt flag Set by H/W at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in other modes. Must be cleared by S/W 0 RI 0 Receive Interrupt flag Set by H/W at the end of the eighth bit in Mode 0, or at the sampling point of the stop bit in other modes. Must be cleared by S/W. DS-TM5F60_E 57 Rev 0.90, 05/0/07

58 TM5F60 Data Sheet Adr SFR Bit# Bit Name Rst Description 99h SBUF 7~0 SBUF UART transmit and receive data. Transmit data is written to this location and receive data is read from this location, but the paths are independent. P.7 data A0h P 6~0 P.6~P.0 7Fh General purpose register 7 P.7 0: Open Drain output low : Schmitt-trigger input with pull up 7~6 PMOD3 00 P.3 Pin Control 00: Mode0; 0: Mode; 0: Mode; : not used Ah PMODL 5~ PMOD 00 P. Pin Control 00: Mode0; 0: Mode; 0: Mode; : not used 3~ PMOD 00 P. Pin Control 00: Mode0; 0: Mode; 0: Mode; : not used ~0 PMOD0 00 P.0 Pin Control 00: Mode0; 0: Mode; 0: Mode; : Mode3, P.0 is TO output 7~6 PMOD7 00 P.7 Pin Control 00: Mode0; 0: Mode; 0: Mode : Mode3, P.7 is RFC clock input pin (RFCX) 5~ PMOD6 00 P.6 Pin Control 00: Mode0; 0: Mode; 0: Mode A3h PMODH : Mode3, P.6 is RFC resistor connection pin (RFCR) P.5 Pin Control 3~ PMOD : Mode0; 0: Mode; 0: Mode : Mode3, P.5 is RFC resistor connection pin (RFCR) ~0 PMOD 00 P. Pin Control 00: Mode0; 0: Mode; 0: Mode : Mode3, P. is RFC resistor connection pin (RFC0R) 7~6 P3MOD3 00 P3.3 Pin Control 00: Mode0; 0: Mode; 0: Mode; : not used Ah P3MODL 5~ P3MOD 00 P3. Pin Control 00: Mode0; 0: Mode; 0: Mode; : not used 3~ P3MOD 00 P3. Pin Control 00: Mode0; 0: Mode; 0: Mode; : not used ~0 P3MOD0 00 P3.0 Pin Control 00: Mode0; 0: Mode; 0: Mode; : not used 7~6 P3MOD7 00 P3.7 Pin Control 00: Mode0; 0: Mode; 0: Mode; : Mode3, P3.7 is TCO output A5h P3MODH 5~ P3MOD6 00 P3.6 Pin Control 00: Mode0; 0: Mode; 0: Mode; : Mode3, P3.6 is TB output 3~ P3MOD5 00 P3.5 Pin Control 00: Mode0; 0: Mode; 0: Mode; : Mode3, P3.5 is TO output ~0 P3MOD 00 P3. Pin Control 00: Mode0; 0: Mode; 0: Mode; : not used 7~6 TOCON 00 TO pin duty and frequency control 00: / duty, / Timer overflow frequency 0: /3 duty, /3 Timer overflow frequency 0: / duty, / Timer overflow frequency TO pin duty and frequency control 000: / duty, / Timer overflow frequency 5~3 TOCON : /3 duty, /3 Timer overflow frequency 00: / duty, / Timer overflow frequency 0: /3 duty, /3 Timer overflow frequency A6h TOCON 0: 3/ duty, / Timer overflow frequency TCO pin duty and frequency control 000: / duty, / SYSCLK frequency 00: /3 duty, /3 SYSCLK frequency 00: / duty, / SYSCLK frequency ~0 TCOCON 000 0: / duty, / SYSCLK frequency 00: / duty, / SYSCLK frequency 0: /3 duty, /3 SYSCLK frequency 0: 3/ duty, / SYSCLK frequency : 3/ duty, / SYSCLK frequency DS-TM5F60_E 58 Rev 0.90, 05/0/07

59 TM5F60 Data Sheet Adr SFR Bit# Bit Name Rst Description 6 PWRSAV 0 V DD voltage control. 0: V DD =V BAT : V DD =V BAT *5/300~V BAT *9/300 V DD voltage setting in Fast/Slow mode while PWRSAV=. 000: V DD =V BAT *5/300 in Fast/Slow mode 00: V DD =V BAT *6/300 in Fast/Slow mode A7h VCON 00: V DD =V BAT *59/300 in Fast/Slow mode 0: V DD =V BAT *70/300 in Fast/Slow mode 0: V DD =V BAT *8/300 in Fast/Slow mode : V DD =V BAT *9/300 in Fast/Slow mode ~0 VSET 00 V DD voltage setting in Idle/Stop mode while PWRSAV=. Definition is the same as VSET. 00: V DD =V BAT *37/300 in Fast/Slow mode 5~3 VSET 00 0: V DD =V BAT *8/300 in Fast/Slow mode Global interrupt enable control. 7 EA 0 0: Disable all Interrupts. : Each interrupt is enabled or disabled by its own interrupt control bit. 5 ET 0 Set to enable Timer interrupt A8h IE ES 0 Set to enable Serial Port (UART) Interrupt 3 ET 0 Set to enable Timer Interrupt EX 0 Set to enable external INT pin Interrupt & Stop mode wake up capability ET0 0 Set to enable Timer0 Interrupt 0 EX0 0 Set to enable external INT0 pin Interrupt & Stop mode wake up capability EX 0 Set to enable external INT pin Interrupt & Stop mode wake up capability A9h INTE PIE 0 Set to enable Port Pin Change Interrupt 0 TM3IE 0 Set to enable Timer3 Interrupt T0RFC 0 Timer0 Counter mode (CT0N=) input select 0: T0 (P3.) pin : RFC Clock divided by //6/6 RFC clock divider to Timer0 00: divided by 6 AFh RFCON : divided by 3~ RFCPSC 0: divided by 6 0: divided by Select RFC convert channel. ~0 RFCS 00 00: RFC0R (P.) 0: RFCR (P.5) 0: RFCR (P.6) B0h P3 7~0 P3 FFh Port 3 data 7 DSPON 0 Set to enable LCD Display LCD clock source 6 LCDCLK 0 0: SXT; : FRC/6 5~ LCDFMR 0 LCD Frame Rate, 3=Highest; 0=Lowest 3 LCDUTY LCD Duty control 0: /3 Duty : / Duty Bh LCON Port0 LCD mode control. 000: P0.0~P0.7 are I/O pins 00: P0.0~P0.5 are I/O pins, P0.6~P0.7 are LCD Segment pins 00: P0.0~P0. are I/O pins, P0.5~P0.7 are LCD Segment pins ~0 P0SEG 0: P0.0~P0.3 are I/O pins, P0.~P0.7 are LCD Segment pins 00: P0.0~P0. are I/O pins, P0.3~P0.7 are LCD Segment pins 0: P0.0~P0. are I/O pins, P0.~P0.7 are LCD Segment pins 0: P0.0 is I/O pin, P0.~P0.7 are LCD Segment pins : P0.0~P0.7 are LCD Segment pins DS-TM5F60_E 59 Rev 0.90, 05/0/07

60 TM5F60 Data Sheet Adr SFR Bit# Bit Name Rst Description B3h TM3SEC 7~0 TM3SEC R Timer3 count data bit ~5 Bh TM3DL 7~0 TM3DL R Timer3 count data bit 7~0 B5h TM3DH 6~0 TM3DH R Timer3 count data bit ~8 B6h TM3RLD 7~0 TM3RLD 00h Timer3 overflow reload data for Timer3 bit ~5 (TM3SEC) Timer3 adjustment sign 7 TM3ADJS 0 0: Timer3 positive adjust, to increase Timer3 counting rate B7h TM3ADJ : Timer3 negative adjust, to decrease Timer3 counting rate Timer3 adjust magnitude, 0.77 ppm per LSB. 6~0 TM3ADJ 00h The adjustment is calculated as ±TM3ADJ*0.77ppm. The total adjustable range is ± 6ppm. 5 PT 0 Timer Interrupt Priority Low bit PS 0 Serial Port (UART) Interrupt Priority Low bit B8h IP 3 PT 0 Timer Interrupt Priority Low bit PX 0 External INT Pin Interrupt Priority Low bit PT0 0 Timer0 Interrupt Priority Low bit 0 PX0 0 External INT0 Pin Interrupt Priority Low bit 5 PTH 0 Timer Interrupt Priority High bit PSH 0 Serial Port (UART) Interrupt Priority High bit B9h IPH 3 PTH 0 Timer Interrupt Priority High bit PXH 0 External INT Pin Interrupt Priority High bit PT0H 0 Timer0 Interrupt Priority High bit 0 PX0H 0 External INT0 Pin Interrupt Priority High bit PX 0 External INT Pin Interrupt Priority Low bit BAh IP PP 0 Port pin change Interrupt Priority Low bit 0 PT3 0 Timer3 Interrupt Priority Low bit PXH 0 External INT Pin Interrupt Priority High bit BBh IPH PPH 0 Port Interrupt Priority High bit 0 PT3H 0 Timer3 Interrupt Priority High bit 7 TF 0 Timer overflow flag Set by H/W when Timer/Counter overflows unless RCLK= or TCLK=. This bit must be cleared by S/W. 6 EXF 0 TEX interrupt pin falling edge flag Set when a capture or a reload is caused by a negative transition on TEX pin if EXEN=. This bit must be cleared by S/W. 5 RCLK 0 UART receive clock control bit 0: Use Timer overflow as receive clock for serial port in mode or 3 : Use Timer overflow as receive clock for serial port in mode or 3 TCLK 0 UART transmit clock control bit 0: Use Timer overflow as transmit clock for serial port in mode or 3 : Use Timer overflow as transmit clock for serial port in mode or 3 TEX pin enable C8h TCON 0: TEX pin disable 3 EXEN 0 : TEX pin enable, it cause a capture or reload when a negative transition on TEX pin is detected if RCLK=TCLK=0 TR 0 Timer run control. :timer runs; 0:timer stops CTN 0 Timer Counter/Timer select bit 0: Timer mode, Timer data increases at System clock cycle rate : Counter mode, Timer data increases at T pin s negative edge Timer Capture/Reload control bit 0: Reload mode, auto-reload on Timer overflows or negative transitions on 0 CPRLN 0 TEX pin if EXEN=. : Capture mode, capture on negative transitions on TEX pin if EXEN=. If RCLK= or TCLK=, CPRLN is ignored and timer is forced to autoreload on Timer overflow. CAh RCPL 7~0 RCPL 00h Timer reload/capture data low byte CBh RCPH 7~0 RCPH 00h Timer reload/capture data high byte CCh TL 7~0 TL 00h Timer data low byte CDh TH 7~0 TH 00h Timer data high byte DS-TM5F60_E 60 Rev 0.90, 05/0/07

61 TM5F60 Data Sheet Adr SFR Bit# Bit Name Rst Description 7 CY 0 ALU carry flag 6 AC 0 ALU auxiliary carry flag 5 F0 0 General purpose user-definable flag D0h PSW RS 0 Register Bank Select bit 3 RS0 0 Register Bank Select bit 0 OV 0 ALU overflow flag F 0 General purpose user-definable flag 0 P 0 Parity flag Slow clock Type. This bit can be changed only in Fast mode (SELFCK=). 7 SCKTYPE 0 0: SXT : RFC, S/W must setup RFC oscillating circuitry before set this bit to 6~5 SXTGAIN 3768 SXT oscillator gain, 3=Highest gain, 0=Lowest gain. STPPCK 0 Set to stop UART/Timer0// clock in Idle mode for current reducing. 3 STPFCK 0 Set to stop Fast clock for power saving in Slow/Idle mode. This bit can be changed only in Slow mode. D8h CLKCON System clock select. This bit can be changed only when STPFCK=0. SELFCK 0: Slow clock; : Fast clock ~0 CLKPSC System clock prescaler. 00: System clock is Fast/Slow clock divided by 6 0: System clock is Fast/Slow clock divided by 6 0: System clock is Fast/Slow clock divided by : System clock is Fast/Slow clock divided by E0h ACC 7~0 ACC 00h Accumulator F0h B 7~0 B 00h B register 3 CLRWDT 0 Set to to clear Watch Dog Timer F8h AUX CLRTM3 0 Set to Clear Timer3 STPRFC 0 Set to stop RFC clock oscillating 0 DPSEL 0 Active DPTR Select Adr Flash Bit# Bit Name Description 3FFEh CFGWL 7~0 7 PROT Flash Code Protect, =Protect 6 XRSTE Pin Reset enable, =enable. 3FFFh CFGWH 5 MVCLOCK If, the MOVC & MOVX instruction s accessibility to MOVC-Lock area is limited. WDTE WDT Reset enable, =enable. LVRE Low Voltage Reset enable, =enable. DS-TM5F60_E 6 Rev 0.90, 05/0/07

62 TM5F60 Data Sheet INSTRUCTION SET Instructions are, or 3 bytes long as listed in the byte column below. Each instruction takes ~8 System clock cycles to execute as listed in the cycle column below. ARITHMETIC Mnemonic Description byte cycle opcode ADD A,Rn ADD A,dir ADD A,@Ri ADD A,#data ADDC A,Rn ADDC A,dir ADDC A,@Ri ADDC A,#data SUBB A,Rn SUBB A,dir SUBB A,@Ri SUBB A,#data INC A INC Rn INC dir DEC A DEC Rn DEC dir INC DPTR MUL AB DIV AB DA A Add register to A Add direct byte to A Add indirect memory to A Add immediate to A Add register to A with carry Add direct byte to A with carry Add indirect memory to A with carry Add immediate to A with carry Subtract register from A with borrow Subtract direct byte from A with borrow Subtract indirect memory from A with borrow Subtract immediate from A with borrow Increment A Increment register Increment direct byte Increment indirect memory Decrement A Decrement register Decrement direct byte Decrement indirect memory Increment data pointer Multiply A by B Divide A by B Decimal Adjust A F F F F F A3 A 8 D LOGICAL Mnemonic Description byte cycle opcode ANL A,Rn ANL A,dir ANL A,@Ri ANL A,#data ANL dir,a ANL dir,#data ORL A,Rn ORL A,dir ORL A,@Ri ORL A,#data ORL dir,a ORL dir,#data XRL A,Rn XRL A,dir XRL XRL A,#data XRL dir,a XRL dir,#data CLR A CPL A AND register to A AND direct byte to A AND indirect memory to A AND immediate to A AND A to direct byte AND immediate to direct byte OR register to A OR direct byte to A OR indirect memory to A OR immediate to A OR A to direct byte OR immediate to direct byte Exclusive-OR register to A Exclusive-OR direct byte to A Exclusive-OR indirect memory to A Exclusive-OR immediate to A Exclusive-OR A to direct byte Exclusive-OR immediate to direct byte Clear A Complement A F F F E F DS-TM5F60_E 6 Rev 0.90, 05/0/07

63 TM5F60 Data Sheet LOGICAL Mnemonic Description byte cycle opcode SWAP A RL A RLC A RR A RRC A Swap Nibbles of A Rotate A left Rotate A left through carry Rotate A right Rotate A right through carry C DATA TRANSFER Mnemonic Description byte cycle opcode MOV A,Rn MOV A,dir MOV A,@Ri MOV A,#data MOV Rn,A MOV Rn,dir MOV Rn,#data MOV dir,a MOV dir,rn MOV dir,dir MOV dir,@ri MOV dir,#data MOV DPTR,#data MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR PUSH dir POP dir XCH A,Rn XCH A,dir XCH A,@Ri XCHD A,@Ri Move register to A Move direct byte to A Move indirect memory to A Move immediate to A Move A to register Move direct byte to register Move immediate to register Move A to direct byte Move register to direct byte Move direct byte to direct byte Move indirect memory to direct byte Move immediate to direct byte Move A to indirect memory Move direct byte to indirect memory Move immediate to indirect memory Move immediate to data pointer Move code byte relative DPTR to A Move code byte relative PC to A Move external data(a8) to A Move external data(a6) to A Move A to external data(a8) Move A to external data(a6) Push direct byte onto stack Pop direct byte from stack Exchange A and register Exchange A and direct byte Exchange A and indirect memory Exchange A and indirect memory nibble E8-EF E5 E6-E7 7 F8-FF A8-AF 78-7F F5 88-8F F6-F7 A6-A E-E3 E0 F-F3 F0 C0 D0 C8-CF C5 C6-C7 D6-D7 BOOLEAN Mnemonic Description byte cycle opcode CLR C CLR bit SETB C SETB bit CPL C CPL bit ANL C,bit ANL C,/bit ORL C,bit ORL C,/bit MOV C,bit MOV bit,c Clear carry Clear direct bit Set carry Set direct bit Complement carry Complement direct bit AND direct bit to carry AND direct bit inverse to carry OR direct bit to carry OR direct bit inverse to carry Move direct bit to carry Move carry to direct bit C3 C D3 D B3 B 8 B0 7 A0 A 9 DS-TM5F60_E 63 Rev 0.90, 05/0/07

64 TM5F60 Data Sheet BRANCHING Mnemonic Description byte cycle opcode ACALL addr LCALL addr 6 RET RETI AJMP addr LJMP addr 6 SJMP rel JC rel JNC rel JB bit,rel JNB bit,rel JBC bit,rel JZ rel JNZ rel CJNE A,dir,rel CJNE A,#data,rel CJNE Rn,#data,rel DJNZ Rn,rel DJNZ dir,rel Absolute jump to subroutine Long jump to subroutine Return from subroutine Return from interrupt Absolute jump unconditional Long jump unconditional Short jump (relative address) Jump on carry= Jump on carry=0 Jump on direct bit= Jump on direct bit=0 Jump on direct bit= and clear Jump indirect relative DPTR Jump on accumulator=0 Jump on accumulator 0 Compare A,direct, jump not equal relative Compare A,immediate, jump not equal relative Compare register,immediate, jump not equal relative Compare indirect,immediate, jump not equal relative Decrement register, jump not zero relative Decrement direct byte, jump not zero relative F 3 0-E B5 B B8-BF B6-B7 D8-DF D5 MISCELLANEOUS Mnemonic Description byte cycle opcode NOP No operation 00 In the above table, an entry such as E8-EF indicates a continuous block of hex opcodes used for 8 different registers, the register numbers of which are defined by the lowest three bits of the corresponding code. Non-continuous blocks of codes, shown as -F (for example), are used for absolute jumps and calls with the top 3 bits of the code being used to store the top three bits of the destination address. DS-TM5F60_E 6 Rev 0.90, 05/0/07

65 TM5F60 Data Sheet ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Rating Unit Supply voltage V SS 0.3 ~ V SS +. Input voltage V SS 0.3 ~ V BAT V Output voltage V SS 0.3 ~ V BAT Output current high per pin 0 Output current high per all pins 50 Output current low per pin +30 ma Output current low per all pins +00 Maximum Operating Voltage. V Operating temperature 0 ~ +85 Storage temperature 65 ~ +50 C DC Characteristics (TA=5 C) Parameter Sym Conditions Min Typ Max Unit Input High Voltage V IH all except P.7 V BAT =3V 0.6V BAT P.7 V BAT =3V 0.8V BAT Input Low Voltage V IL all Input V BAT =3V 0.V BAT V I/O Port Source Current I OH all except P.7 I/O Port Sink Current I OL V BAT =3V V OH =.7V V ma all except P.7 V BAT =3V 6 P.7 V OL =0.3V 5 9 Input Leakage Current (pin high) I ILH all Input V IN =V BAT Input Leakage Current (pin low) I ILL all Input Vin=0V ua Fast, 3.7MHz V BAT =3V V DD =3V 970 Fast,.5MHz 60 Power Supply Current I BAT Slow, 3KHz V BAT =3V. ua V DD =.5V Slow, KHz LCD On. Idle, KHz Stop V BAT =3V V DD =.5V 0.3 ua Pull-Up Resistor R PU all except P.7 V BAT =3V 0 KΩ P.7 V IN =0V 70 KΩ ma BandGap Reference Voltage Parameter Sym Conditions Min Typ Max Unit BandGap Voltage V BG V BAT =3V, 5 C...6 V V BAT =.V~3.3V, 0 C~85 C...9 V DS-TM5F60_E 65 Rev 0.90, 05/0/07

66 FRC Frequency (KHz) FRC Freq. (KHz) TM5F60 Data Sheet Clock Timing (TA=5 C) Parameter Sym Conditions Min Typ Max Unit V DD =3.0V 3.75 FRC Clock Frequency F FRC V DD =.8V V BAT =3V. MHz V DD =.5V VDD Voltage (V) FRC Frequency with V DD, T A =5 C VDD=3V VDD=V Temperature (C) FRC Frequency with Temperature, V DD =3V & V DD =V DS-TM5F60_E 66 Rev 0.90, 05/0/07

67 VDD(V) TM5F60 Data Sheet V DD Voltage Level Parameter Sym Conditions Min Typ Max V BAT =3.V, VSET=3 5 C.53 V BAT =.8V, VSET= 5 C.7 V DD Voltage Level V DD V BAT =3.V, VSET=3 70 C.57 V BAT =.8V, VSET= 70 C.5 V BAT =3.V, VSET=3 0 C.50 V BAT =.8V, VSET= 0 C.3 V DD Voltage with VSET/, V BAT =.5V~3.V VBAT=3.V /3.V avg. 5 /3.V avg. 70 /3.V avg V DD Voltage with VSET/, T A = 0 C~70 C DS-TM5F60_E 67 Rev 0.90, 05/0/07

68 Vlvr (V) TM5F60 Data Sheet LVR Level Parameter Sym Conditions Min Typ Max Unit LVR Voltage Level Vlvr 5 C.58 V LVR Temperature ( C ) LVR with Temperature, T A = 0 C~80 C LVR=.58V DS-TM5F60_E 68 Rev 0.90, 05/0/07

69 TM5F60 Data Sheet PACKAGE INFORMATION Ordering Information Ordering Number Package TM5F60-COD Wafer / Dice with code TM5F60-MTP Wafer / Dice blank chip TM5F60-MTP-76 LQFP6 ( 0*0*.mm ) DS-TM5F60_E 69 Rev 0.90, 05/0/07

70 TM5F60 Data Sheet Package Information LQFP-6 ( 0 0mm ) Package Dimension DS-TM5F60_E 70 Rev 0.90, 05/0/07