Table 1-1 Instruction Operation (continued on following 4 pages)

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1 Kris Bleakley S Commands Table - Instruction Operation (continued on following pages) Address Mode Note Cycle Address Bus Bus RWB a. Absolute!abs s, bytes, and cycles () a + + L H b. Absolute!abs CALL, bytes, cycles New New L New H H L Next c. Absolute!abs JMP, bytes, cycles + + New New L New H Next d. Absolute (R-M-W)!abs s, bytes, cycles + + L H e. Absolute (R-M-W)!abs TCLR, TSET s, bytes, cycles + + L H. Absolute Indexed Indirect (!abs+x) JMP, bytes, cycles New L H New L New H Next. Absolute,!abs+x s, bytes, and cycles () a L H. Absolute, Y!abs+y s, bytes, and cycles () a Y +Y L H

2 Kris Bleakley S Commands Table - (continued) Address Mode Note Cycle Address Bus Bus RWB. Accumulator s, byte, cycles + [+] a. Direct dp s, bytes, and cycles () a + b. Direct (R-M-W) dp, CLR, SET s, bytes, cycles + c. Direct dp CMPW, bytes, cycles + + Low High d. Direct dp ADDW, W, SUBW s, bytes, cycles () + + Low Low High / / e. Direct (R-M-W) dp DECW, INCW s, bytes, cycles Low Low High High a. Direct Direct dp,dp ADC, AND, CMP, EOR, OR, SBC s, bytes, cycles + + / b. Direct Direct dp,dp, bytes, cycles + +. Direct Immediate dp,#imm s, bytes, cycles + + / 9. Direct Indexed Indirect [dp+x] s, bytes, and cycles () a L H

3 Kris Bleakley S Commands Table - (continued) Address Mode Note Cycle Address Bus Bus RWB. Direct Indirect Indexed [dp]+y s, bytes, and cycles () a L H. Direct Relative dp, rel BBC, BBS, CBNE, DBNZ s, bytes, and cycles (9) () () a b / a. Direct, dp+x s, bytes, and cycles () a b. Direct, (R-M-W) dp+x s, bytes, cycles c. Direct, Relative dp+x, rel CBNE, bytes, and cycles () () a b Direct, Y dp+y s, bytes, and cycles () a + + +Y +Y a. Indirect (x) s, byte, and cycles () a + [+] b. Indirect (x)+ s, byte, cycles () () + [+] /. Indirect Indirect (x),(y) ADC, AND, CMP, EOR, OR, SBC s, byte, cycles + Y [+] /

4 Kris Bleakley S Commands Table - (continued) Address Mode Note Cycle Address Bus Bus RWB. Immediate #imm s, bytes, cycles +. Implied i CLRC, CLRP, CLRV, D, DAS, DEC, DI, DIV, EI, INC,, MUL, NOP, NOTC, SETC, SETP, CN s, byte,,,, 9 and cycles + + [+] a. Bit mem.bit AND, EOR,, OR s. bytes, and cycles () a + + L H b. Bit mem.bit, NOT, bytes, and cycles () a + + L H 9a. Relative rel BCC, BCS, BEQ, BMI, BNE, BPL, BRA, BVC, BVS 9 s, bytes, and cycles () () a b b. Relative rel DBNZ, bytes, and cycles () () a b [+] a. Stack s BRK, byte, cycles VA VA+ New [+] H L PSW New L New H Next b. Stack s RETI, byte, cycles New [+] PSW New L New H Next c. Stack s PUSH s, byte, cycles + [+] REG

5 Kris Bleakley S Commands Table - (continued) Address Mode Note Cycle Address Bus Bus RWB d. Stack s POP s, byte, cycles + + [+] REG e. Stack s TCALL s, byte, cycles VA VA+ New [+] H L New L New H Next f. Stack s ALL, bytes, cycles New H L Next g. Stack s RET, byte, cycles New [+] New L New H Next Notes: Memory is accessed every cycle.. Add cycle for write.. Add cycles if branch is taken.. Add cycle for EOR, OR.. Add cycle for.. Internal operation for ()+, A.. Internal operation for A, ()+.. Internal operation for CMP.. Internal operation for ADDW, SUBW and W YA, dp. 9. Internal operation for BBC, BBS and CBNE.

The 6502 Instruction Set

The 6502 Instruction Set Load and Store Group LDA Load Accumulator N,Z LDX Load X Register N,Z LDY Load Y Register N,Z STA Store Accumulator STX Store X Register STY Store Y Register Arithmetic Group ADC