GRAFFY / HYDE - Information

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1 GRAFFY / HYDE - Information Revision This file contains important information! Please read it carefully! Description of the GRAFFY/HYDE Enhancements 1.1 General Information about Revision Information for all users 1.3 Information for System Administrators & Macro Programmers 1.1 General Information about Revision 12.1 (GRAFFY, a product from DURST CAD/CONSULTING GmbH, D Holzgerlingen, Germany) We guarantee further on a 100% binary upward compatibility of all drawings, macros and ARCHIVE/- GENERATE files from HP EGS-UNIX to GRAFFY/HYDE. We also guarantee an ARCHIVE/GENERATE-upward compatibility from all earlier GRAFFY/HYDE revisions. Reading data out of HP EGS-PASCAL 3.1 is ensured only by the ARCHIVE format. We would like to point out, that the Microsoft operating systems WINDOWS 95/98/ME/NT will not be supported in the future anymore although the GRAFFY/HYDE software might run on these operating systems. The following description contains the most important enhancements between Revision 11.0 and Information for all Users LTCC Layout Module revised in essential functions This module has been completely revised not only concerning its layer structure but also in many more functions. It now offers additional functionality with the ROUTE and DRC command, an elegant copying of tape and cavity contours, a flexible toolbox for creating vias, a new toolbox for adding bond pads and bond wires as well as an information window about the used tapes and cavities. For each tape buried hybrid resistors are available. The provided vias are stored in their own part directory (viasltcc) which is not included automatically in the Symbol Explorer and in the search table. The new chapter LTCC in the help makes it easier to start with the new module. In the LTCC module hybrids can also be layouted, just by changing the System technology from LTCC to HYBRID.

2 Time to learn: ca. 6-8 hours Substantially enhanced functionality in DRC as well as in the routing functions as mentioned above. This leads to a faster and error-free result while layouting.

2 2 Time to learn: ca. 6-8 hours Substantially enhanced functionality in DRC as well as in the routing functions as mentioned above. This leads to a faster and error-free result while layouting. Some of the layout technologies with setting vias using the via menu are new and allow to create complex layouts with numerous tapes. 2-Point-Router again considerably improved 1. When routing the currently defined DRC distances are taken into consideration. Individual net- and part-specific distances are also considered. In order to test temporary defined distance values, these can be entered in the toolbox but without saving them (valid for all layout modules). 2. Adding individual distances (associated information with tag value: 1015, 1016, 1017) to single components or parts will be considered also by the DRC and while routing. 3. During the routing, the part of the airline, which is not yet completely routed will be renewed periodically to the shortest connection in the net (minimum spanning tree). If obstacles appear at the destination a dotted line appears (valid for all layout modules). 4. Any kind of parts, which contain a keepout area are also considered while routing. 5. When routing a project specific via menu can be activated with the right mouse button. After selecting a via, it is placed on the last digitized point and at the same time the destination routing layer becomes the actual layer (HLM, LTCC) [see also: LTCC Layout Module with new functions]. 2

3 3 If vias should be placed and at the desired point the DRC distance which is defined is not kept, an error message appears and the via will not be placed. The via menu in the HLM module for example looks like the following picture: depending of the number and of the names of the vias used. Using the menu field # 1T-111 # or # 1B-116 # each of the 5 available trace layers can be selected. 6. The ROUTE command reports an error message, if a port is found, which has no belonging pad (area component). 7. Basically it is not possible to route on bond wire layers and outside a tape or board boundary. Time to learn: ca. 30 Min Substantially faster routing of layouts. Easy support when setting vias. LTCC Layout Module with new route functions 1. During routing with the LTCC module all tape borders and embedded cavities (keepouts) are considered. 2. When routing an airline on a layout with several layers the trace begins automatically in that trace layer, which corresponds to the selected terminal, which has been selected first with the airline. A terminal is e.g. a pad of an SMD part, a pad of a printed thick film resistor, the beginning or the end of a via, but also the open end of an existing trace section. A toggle between automatic layer selection and manual layer selection is possible. 3. During the routing with the route icons any available via can be selected and set using the right mouse button. After terminating the via placement the routing is automatically continued on the new destination layer (other tape or bottom side of the tape). 4. There are available 6 possibilities for selective deletion of nets, partial nets, connections, traces and a connection selected with or without adjacent vias: (see the online help for more information) Time to learn: ca. 2-3 hours Substantially faster routing of layouts. Easy support in setting vias. 3

4 ALIGN PART INFO subtantially accellerated In the modules SCH, PCB, HLM, LTCC the function ALIGN PART INFO (in the pull down menu Special) has been redesigned as a command and so it could be

DRC with distance check for electrical nets enhanced The Design Rule Check for the distance check of electrical nets has obtained new functions. After selecting the icon the following toolbox appears.

4 4 ALIGN PART INFO subtantially accellerated In the modules SCH, PCB, HLM, LTCC the function ALIGN PART INFO (in the pull down menu Special) has been redesigned as a command and so it could be accelerated essentially. All errors still contained have been fixed. Time to learn: ca. 5 Min Substantially faster alignment of rotated and mirrored fonts within schematics as well as layouts. DRC with distance check for electrical nets enhanced The Design Rule Check for the distance check of electrical nets has obtained new functions. After selecting the icon the following toolbox appears. There can be defined a distance of electrical nets to each other, to the board boundary as well as to keepout areas in the layout, which even can be checked individually. In order to exclude the DIE pad distances as well as the bond wires from the check, a layer exclusion function is now available. Paste resistor areas will be defined as so called "non routable areas". When using crossover isolations additionally the isolation overlap can be checked. To better recognize extremely short airlines or missing vias a dashed circle has been implemented for these cases. During the routing the airline is always displayed with the shortest distance to the next terminal. New icons make it easier to work, when the toolbox is up: - loading the net list - executing the DRC - zoom to the next error - terminating the distance check and unload the net list After calling the secondary toolbox: Set individual distance for nets, individual electrical distances can be assigned to any net element or library part. This is important if e.g. a leadframe is placed directly on the board boundary and falls below the standard distance, so that this part does not generates an error. 4

5 5 Time to learn: ca. 1-2 hours More possibilities for checking and reliability through additional distance check, faster handling of the checking procedure DRC with enhanced part placement check The Design Rule Check for the independent part placement check has obtained new functions. After selecting the icon the following toolbox appears, which shows the different tests. Different distances can be set between parts or between a part and the board boundary or between a part and a keepout (holes in the board or cavities in the tape). Then these distances are valid for all parts in the whole layout. The part geometry in layer 2 and 3 (or any other layer, which is entered in the toolbox) is used for the check. In case of printed resistors the paste area between the pads will be used as part geometry for the placement distance check. The overlapping of resistor pads does not generate an error. For the placement check no net list is needed. If a net list has been loaded before, it will be unloaded and after the placement check has been executed the net list is loaded again. If the placement check is activated, a safety zone will be shown as a frame for placement assistance when parts are moved or copied. This dotted frame corresponds to the part distance defined in the toolbox. This is also valid for parts, to which an individual placement distance has been assigned. If the part boundaries in the layers 2 and 3 are created as closed contours, a rough estimation of the routing possibility can be made with this area using the AREA command (area :a -e #i +r2 +p2 +c2; <Return>). Many of the SMD parts from the standard library are created with lines instead of rectangles or polygons, which means that a general estimation (without prior modification) is not able with these parts. New icons makes the work easier, if the toolbox is loaded you find: - execute placement distance check - zoom to the next error - stop the distance check 5

Setting an individual distance for single parts was already able by using the secondary toolbox: Set individual placement distance. 6 It is important e.g. to set an individual distance for single DIE parts to the next part, to get enough free space for the bond wires.

6 Setting an individual distance for single parts was already able by using the secondary toolbox: Set individual placement distance. 6 It is important e.g. to set an individual distance for single DIE parts to the next part, to get enough free space for the bond wires. A Non-check can also be associated to certain parts. This maybe necessary if a leadframe is placed directly at the board boundary and therefore the standard distance is falling below, so that no error is generated. Time to learn: ca. 1 hour More layout security through additional placement check Common error list for Design Rule Check (layout modules) All errors which occur while testing are now managed in one error list of the DRC. The connection lister transfers its errors into the error list of the Design Rule Check, too. Thereby with the icon all errors can be searched one after the other. In the DRC error list the following error groups have been created: short circuits through net list errors, distance errors of electrical nets (traces, signal carrying areas) and placement errors (part distances) as well as bond wire errors. All error messages are output in a standard format. The error messages have been related to the reference designators of any single part, if possible. Time to learn: ca. 10 Min No subsequent loading of the error file any more, no deleting of error messages necessary. If an error is removed, the error message disappears automatically. Better error recognition and therefore a faster routing of the layout. Further Design Rule Check improvements (layout modules) Several new functions have been implemented in the DRC: All layout modules 1. The DRC warns with a BEEP and a warning message, if the net list is loaded and a part is added whose ports are not contained in the net list. 2. The DRC generates an error message, if a port has no belonging pad (area component). 3. Isolation components may touch the board or tape boundary but they are not allowed to overlap. 4. When using DIE packages (chip + bond pads) the airlines basically lead to the bond pad. Only if there are no bond pads in the layout, the airlines lead to the DIE pads. If the bond pads are not placed correctly an error is reported. 6

7 7 LTCC 5. For every single tape the tape boundary can be checked with its possible cavities (predefined in the toolbox). 6. DIE parts can be placed on all tapes. An associated text (tag value 1040) must be added, which contains the tape number. The DRC then checks these DIEs against all other parts on the respective tape. Time to learn: ca. 15 Min Easier working with DIE packages. More DRC checks which means faster and error free routing of layouts. HLM and LTCC module, handling of the isolation layers In order to make the handling of the isolation layers above and below the hybrid substrate easier these layers have been divided into groups. On the top side of the substrate: for the region between substrate and 1. isolation (layers ) the group name Top1 has been introduced. Analogue the group between 1. isolation (layers ) and 2. isolation (layers ) is called Top2. The group between 2. isolation (layers ) and 3. isolation (layers ) is called Top3. The group between 3. isolation (layers ) and 4. isolation (layers ) is called Top4. Above the 4. isolation only the topmost trace layer 151 exists. On the bottom side of the substrate: for the area between substrate and 1. isolation (layers ) the group name Bottom1 has been introduced. Analogue the group between 1. isolation (layers ) and 2. isolation (layers ) is called Bottom2. The group between 2. isolation (layers ) and 3. isolation (layers ) is called Bottom3. The group between 3. isolation (layers ) and 4. isolation (layers ) is called Bottom4. Below the 4. isolation only the lowest trace layer 152 exists. First of all buried parts or parts which are placed on isolations refer to these group names. The DRC checks electrically each of these areas, the 2 point router recognizes and considers these isolation layers. Thereby isolation components are allowed to touch the substrate boundary, but they are not allowed to overlap it. Time to learn: ca. 30 Min A clear separation of the isolation layers and a more easily work with buried resistors 7

8 Buried resistors under the isolation layers have been introduced Thick film resistors can now also be buried under isolations above or beneath a hybrid or LTCC. This is valid for all 4 existing isolation layers. The new variable macro parts are: rect4in_t and 8 rect4in_b. They can also be calculated with the command RDIM. With these new parts there also have been introduced new layers for pads and resistor pastes. The pads for buried resistors above the substrate are placed on the layers , the pads for buried resistors below the substrate are placed on the layers The resistor layers are built in groups to 20 layers each, like the existing top side resistors. For resistors in the group Top1 (placed between substrate and 1. isolation layer) the layers are defined. For the resistors in group Top2 (placed between the 1. isolation layer and the 2. isolation layer) the layers , for the resistors in group Top3 (placed between 2. isolation layer and 3. isolation layer) the layers and for resistors in group Top4 (placed between 3. isolation layer and 4. isolation layer) the layers Above the 4. isolation layer the standard resistors are used. For the bottom side groups: Bottom1 Bottom4 the following layers have been introduced: resistor layers group Bottom1: layers , resistor layers group Bottom2: layers , resistor layers group Bottom3: layers , resistor layers group Bottom4: layers All buried resistors are considered by the DRC during the layout and the use of the 2 point router. These buried resistors do not have a trim cut. Time to learn: ca. 2-3 hours More compact layouts with the use of buried resistors LTCC Layout Module 1. For each LTCC project a different number of tapes can be used. But if individual layer extensions have been made in the process file, these will be lost through the automatic definition of the new process file. In order to reload these individual layer extensions automatically the macro: LTCC_Layer_Customization is called. This macro must contain the individual layer extensions (EQU commands). If necessary this macro must exist in the customize file: LTCC.CUST. It is executed automatically. 2. With regard to future developments in the LTCC module for each tape a group of layers has been defined, which contain tape-specific part information. The electric layer bindings have been made corresponding to the rules of the standard parts. For the tape-related top side parts including the associated information the following layers have been established: layers For the tape-related bottom side parts including the associated information the following layers have been established: layers These layers are available in each tape so that the number of 100 layers has to be added for any additional tape. Time to learn: ca. 45 Min Easier library part creation, allows tape-specific parts, more flexible part handling in the LTCC module 8

9 Toolbar for creating library parts has been enhanced for the layout modules Because of new layers and enhanced part functions this toolbox has also been enhanced: For DIE and SMD parts the glue layer 189 (Top) and 190 (Bottom) has been added. If creating a new part is started with an empty screen window, the field near the button is automatically set to 0. If the value is set to 1, the value of the logical level can be reset to 0 by clicking on the field Level. Time to learn: ca. 5 Min 9 Easier library part creation GDSII-in and GDSII-out enhancement The GDSOUT command has obtained a new option :X. Herewith the number of used GDSII layers can be set up to The standard is 64 layers. The GDSIN command accepts up to layers (but layer numbers higher than 8191 will be transformed into the default layer). Time to learn: ca. 5 Min More flexible handling of the GDSII import and export Information about layer extensions 1. The structure of the group names of layers in the process file has been unified and supplemented with new group names. The names of some layers became more clearly and unambiguous in their designation. 2. The layer name of the layer 12 has been renamed, it is now: Part_Number_Top 3. The layer name of the layer 253 has been renamed, it is now: Associate_Information_Top 4. The following new layers have been introduced (PCB/HLM/LTCC): 159 DIE_Pad_Top DIE pad for top side DIE parts. The bond wire layers 161, 163, 171, 173 are now bound to this layer DIE_Pad_Bottom DIE pad for bottom side DIE parts. The bond wire layers 162, 164, 172, 174 are now bound to the layer Associate_Information_Bottom For general associated information on the bottom side 265 DRC_Info_Top For special associated DRC parameters (Tag 1015, 1016, 1017) of the top side 266 DRC_Info_Bottom For special associated DRC parameters (Tag 1015, 1016, 1017) of the bottom side 267 Laser_Cut_Top For a laser cut from the top side 268 Laser_Cut_Bottom For a laser cut from the bottom side 269 Laser_Scribe_Top For laser scribe information from the top side 270 Laser_Scribe_Bottom For laser scribe information from the bottom side 293 Bond_Extra_Pad_Top Additional bond pad layers top side (bound to the upper trace layers) (PCB, HLM, LTCC) 294 Bond_Extra_Pad_Bottom Additional bond pad layer bottom side (bound to the lower trace layers) (PCB, HLM, LTCC) 5. New layers for pad components of buried resistors: Substrate top side: layers 271, 272, 273, 274 Substrate bottom side: layers 275, 276, 277, Names of layer groups (EQUATE command option :G) are output in the same order like they have been created and read in. 9

10 10 7. Extensions of the layer structure of the LTCC module from 35 layers (Rev. 11) to 90 layers per tape in this Rev The following layers have been added. The specification * stands for every tape (repetition every 100 layers): Layers *34 and *35: trace layer on the bottom side of a tape Layer *38: 3. drill hole layer Layer *39 and *40: 2 bond pad layers for the bottom side ofa tape Layer *43: Solder pads for tape-related bottom side parts Layer *44: Test pads for tape related bottom side parts Layer *45: Glue layer for tape related bottom side parts Layers *49 and *50: Extra resistor pad and main pad for buried resistors on any tape Layers *51 up to *70: 20 Resistor paste layers for buried resistors on a tape (same paste system like on the hybrid side) Layers *71 up to *75: tape related resistor information: Reference designator, Type, Physical port, Sheet resistivity value, Maximum value Layer *76: Part outline for tape-related top side parts Layer *77: Part keepout for tape-related top side parts Layer *78: Part pads for tape-related top side parts Layer *79: DIE pads for tape-related top side parts Layers *80 up to *85: Tape-related part information top side: Reference designator, Type, Physical port, Logical port, SMD info, Part number Layer *86: : Part outline for tape-related bottom side parts Layer *87: Part keepout for tape-related bottom side parts Layer *88: Part pads for tape-related bottom side parts Layer *89: DIE pads for tape-related bottom side parts Layer *90 up to 95: Tape-related part information bottom side: Reference designator, Type, Physical port, Logical port, SMD info, Part number 8. The layers 2, 3, 7-19 are no more in the group "Hybrid" (important for the DRC check) 9. The bindings of the top side trace layers 121, 131, 141, 151 and the bottom side trace layers 126, 136, 146, 152 have been changed in such a manner that they are bound directly to the superimposed parts without isolation (important for the DRC check). 10. All isolation layers (in the groups: Top1, Top2, Top3, Top4, Bottom1, Bottom2, Bottom3, Bottom4) have been provided with the corresponding "unbindings" for electrical separation of the trace layers. Important note Please pay attention furtheron that all layers from as well as remain reserved for extension made by DURST CAD. Customer specific extensions should be made beginning with layer

11 Important information about library parts! 1. SCH module: The parts minus.d and plus.d from the directory Miscellaneous have been changed and got the appropriate net name.

11 11 Important information about library parts! 1. SCH module: The parts minus.d and plus.d from the directory Miscellaneous have been changed and got the appropriate net name. The parts plus5v, minus5v, plus12v and minus12v have been added to the library. 2. PCB/HLM/LTCC module: All chip parts (DIEs) out of the existing standard library have been changed and enhanced. Until now DIE pads and bond wires have been on the same layer 161 (top side) or 162 (bottom side). For the DIE pads the layer 159 (top side) and the layer 161 (bottom side) have been introduced. The bond wires are still placed on the layers 161 (top side) and 162 (bottom side) (or 171 and 172). Therefore in the DRC a clear distinction and check can be made between DIE pad and bond wire. Moreover new layers for additional bond wires (other materials or wire size) have been introduced (layer as well as ). All library parts have been changed to this new structure. To distinguish between the already existing library and the new one, all new parts obtained an additional "x" (for extended) in the name. All previously used DIE parts are now stored in the directory DICE1, all new parts are stored in the part directory DICE. Both directories have been listed in the search table. In the Symbol Explorer only the new parts x are available, but the old directory can be included if necessary. DRC and 2 point router consider the new as well as the old parts. All layouts created up to now with the old parts can be processed problem-free and compatible, but they can not be used in tests, which differentiate between DIE pad and bond wire. In the future, please use for new developments only the DIE parts of the new design. The toolbox Part create/edit referring the new layers for the DIE pads has also been updated. When designing bottom side pads of DIE parts a considerably higher flexibility is possible, which is also considered by the DRC and the 2 point router. DIE parts can also have more then one bottom side pad with port, irrespective of whether a DIE pad is placed directly above the bottom side pad. The default files for the connection lister (pcbphy.df, hlmphy.df, ltccphy.df) have been extended with the new layers. All these modifications allow a considerably more flexible part design and more clearly DRC check possibilities. DIE parts can be connected by the 2 point router with traces only beginning with the bond pad, even though the airline point directly at the DIE pad. The 2 point router detects the DIE pad and outputs a message if routing should be done directly to a DIE pad. But if the routing is made from the other side of the airline, it is sub-divided in a white filled trace and a dotted line. As soon as the DIE part owns bond pads, which are connected from the DIE pad to the bond pad through a bond wire, the airline is automatically connected to the bond pad and not any more directly with the DIE pad. Intersections of bond wires are reported as short circuits. 3. PCB/HLM/LTCC module: The SMD info tags for the pick and place machines have been set to invisible for all SMD layout parts on the top side as well as on the bottom side. Thereby this text can not be modified by mistake in the layout any more. Moreover for all bottom side parts the text part-no has been transferred to the layer

12 4. HLM/LTCC module: The following new variable hybrid resistor parts are available as of Rev. 12: rect4in_t Buried rectangle resistor on the top side, between the isolation layers (group: Top1, Top2, Top3, Top4). This resistor can be used simultaneously with a standard top side resistor, if it is separated with an isolation layer. 12 rect4in_b Buried rectangle resistor on the bottom side, between the isolation layers (group: Bottom1, Bottom2, Bottom3, Bottom4). This resistor can be used simultaneously with a standard bottom side resistor, if it is separated with an isolation layer. rect4tpin_t spiral5_t spiral5_b buried resistor inside the LTCC tapes on the top side of a tape. variable circular spiral resistor for the top side. variable circular spiral resistor for the bottom side. All resistors mentioned above can also be modified with the toolbox (pulldown menu: Special/Resistors/Edit parameters). They are considered by the DRC and the 2 point router in their environments. The new resistor calculation (RDIM command) calculates also the new buried resistors. In the RDIM the rectangle resistor types are marked with a "B" for buried if they are placed on the isolations. Rectangle resistors on the tape inner layers are marked with a "TP". Trim cuts are not available with buried resistors. Time to learn: ca. 2 hours Higher flexibility in DIE part creation. Usage of buried resistors. 12

13 1.3. Information for System Administrators & Macro Programmers Miscellaneous 1. 2 point router with new options: + for line attributes, which can be modified during the routing: :W :L :HS :HA :HW + for the via placement during the routing: :V + for the crossover placement during the routing: :C + for deleting last point or via use: ^ 2. MOVE command with new option :G, which can move an element which is not visible on the screen. 13 New System Constants The following new system constants have been implemented into GRAFFY: SYSTEM_DRC_ERR_DISP_COMPS: The value is 1, if additional component info should be displayed in DRC error messages, otherwise 0 (DRC :S :C) SYSTEM_DRC_ERROR_COUNT: contains the current number of errors in the DRC error list. SYSTEM_DRC_KPOUT_SEP: Current DRC distance in user units between an electrical net and a keepout (DRC :S :DK). SYSTEM_TECHNOLOGY: Important for the correct function of the DRC and the 2 point router as well as the EDIT FILM command in the LTCC module. The constant can be defined in the pulldown menu LTCC/SPECIAL/Additional Functions/System Technology: 0 = HLM (Hybrid) 1 = LTCC 2 = PCB. SYSTEM_DRAWING_IS_EMPTY: Shows whether there are existing any drawing elements in the current editor window. The system constant will be defined through the command IDE :A. Constant value = 1 if the drawing is empty, otherwise 0. SYSTEM_DDESYMBOL_TYPE: After selecting a part from the Symbol Explorer with the extension ".d" or "_d" this variable is 0, otherwise the value is 1, if the extension of the part name is ".i" or "_i" (macro instance). SYSTEM_BONDWIRE_LENGTH: shows the total length of all bond wires in user units. SYSTEM_TB_1_NAME... SYSTEM_TB_20_NAME: contains the name of the loaded toolboxes in capital letters without file extension. SYSTEM_BOUNDARY_X1, SYSTEM_BOUNDARY_Y1, SYSTEM_BOUNDARY_X2, SYSTEM_BOUNDARY_Y2 contains the maximum outline points of the tape or board boundary detected after IDE :B. Time to learn: ca. 30 Min Higher flexibility and additional control and evaluation possibilities for a more efficient macro programming. 13

14 14 Additional Improvements The available revision 12.1 contains even more smaller enhancements which are not shown within that survey. Among other things the net list program verify has been enhanced concerning the error messages as well as supplements to the new DRC features. Please test the new revision to notice how much your daily work with GRAFFY/HYDE can be improved. 14

GRAFFY / HYDE Informationen

GRAFFY / HYDE Informationen Version 11.01 31.10.2005 Top news General Information (GRAFFY, a product from DURST CAD/CONSULTING GmbH, D-71088 Holzgerlingen, Germany) GRAFFY is further on a product which