Interfacing GSI Sync SRAMs to a Freescale MPC5554 microcontroller

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Erick Williamson
5 years ago
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1 N1022 Interfacing SI Sync SRMs to a Freescale MPC5554 microcontroller Introduction This application note will discuss interfacing a Freescale MPC5554 microcontroller with SI Syncronous urst SRMs. Compatibility The Freescale MPC5554 is capable of interfacing with SRMs that operate in either Flow Through or Pipeline mode, which is selectable by the addition of wait states in the MPC5554 read timing. The SRMs must operate in a Late Write mode, where the data and byte writes are supplied one cycle after the write command is loaded. ll of SI s Synchronous urst SRMs are compatible with the Freescale MPC5554. Interface Figure 1 shows the basic connection between an MPC5554 and a SI SRM. The FT pin controls whether the SRM operates in Pipeline mode or Flow Through mode. This pin needs to be tied to V SS if the MPC is operating in a zero wait state Read Mode which is also referred to as Flow Through mode in the SRM datasheet. The FT pin will need to be tied to V DD if the MPC is operating in a one wait state Read Mode, which is also refered to as Pipline mode in the SRM datasheet. The MPC5554 microcontroller uses a Late Write protocol when perfroming L2 cache writes. This requires the design to use the DSP pin to configure the SRM to utilize a Late Write protocol. Freescale MPC5554 DDR[8:31] Figure 1: Connection diagram SI Syncronous SRM V DD for Pipeline mode DV FT DSP CLKOUT V SS for Flow Through mode W DSC V DD E2 WE[0:3] D E3 DT[0:31] [0:31] LO V SS Rev: 1. 6/25 1/5 25, SI Technology

2 N1022 Timing nalysis For all of the following timing diagrams, the SI pin names are displayed on the left next to the MPC pin names. Figure 2 is a timing diagram for L2 cache write. s seen in Figure 2, the addresses and DSP signals are supplied on the first rising edge of clock for the beginnning of the write cycle and the write enable, byte writes, and data signals are supplied on the following rising edge of clock. SRM MPC5554 Figure 2: L2 cache write CLKout DDR[8:31] IZ[0:1] DV DSP T D WE Rev: 1. 6/25 2/5 25, SI Technology

3 N1022 Figure 3 illustrates a flow through read which is also referenced as a zero wait state read. When the SRM operates in Flow Through mode, the read command is clocked in and data is referenced to the same rising edge of clock. Figure 3: Flow Through Mode or Zero Wait State Read SRM MPC5554 DDR[8:31] IZ[0:1] DV DSP T Rev: 1. 6/25 3/5 25, SI Technology

4 N1022 Figure 4 illustrates a flow through read cycle followed by a write cycle. One thing to notice is the required deslect cycle that is added between the read cycle and the write cycle. The deselect cycle is nessecary to allow the SRM to get off the bus and the MPC to begin driving. If this cycle is omitted, there will be bus contention and it is possible that the MPC will not latch in correct data. Figure 4: Flow Through Read Deselect Write Read Deselect Write Deselect SRM MPC5554 DDR[8:31] IZ[0:1] DV DSP T D WE Rev: 1. 6/25 4/5 25, SI Technology

5 N1022 Figure 5 illustrates a pipeline read which is also referneced as a one wait state read. The read address is supplied on the rising edge of clock. On the next rising edge of the clock, data is driven out from the SRM. The data is referenced to the second rising edge of clock. SRM MPC5554 Figure 5: Pipeline Read or One Wait State Read DDR[8:31] IZ[0:1] DV DSP T Summary The Freescale MPC5554 Microcontroller will interface with SI Synchronous urst SRMs that are configured to operate in either Pipeline or Flow Through mode. The timing diagrams in this document bridged the gap between those provided in the Freescale documentation referencing the microcontroller signal names and SI Synchronous urst SRM signal names. designer using this document as a guide should be able to properly configure the interface to work with SI Synchronous urstrm devices. If further questions still exist, please feel free to contact SI pplication Engineers at apps@gsitechnology.com. Rev: 1. 6/25 5/5 25, SI Technology

Interfacing GSI Sync SRAMs to a Freescale Multiplexed MPC567xF or PXR40xx Microcontroller

Interfacing GSI Sync SRAMs to a Freescale Multiplexed MPC567xF or PXR40xx Microcontroller N1020 Interfacing SI Sync SRMs to a Freescale Multiplexed MPC567xF or PXR40xx Introduction This application note will discuss interfacing a Freescale MPC567xF microcontroller or the Freescale e200 Power