IOT is IOMSLPT for Verification Engineers

Transcription

1 IOT is IOMSLPT for Verification Engineers Adam Sherer, Product Management Group Director TVS DVClub Bristol, Cambridge, Grenoble, and worldwide 12 September 2017

2 IOT = Internet of Mixed-Signal Low Power Things (IOMSLPT) for Verification Engineers Automotive Consumer Cadence Design Systems, Inc. All rights reserved. Samsung DJI Mobility Data Center and Storage IoT/Industrial Design and Verification Challenges Design size and complexity Analog-digital integration at every level (IP, IC, SoC/system) Including analog early in design starting from hardware/software co-design Power top constraints for mixed signal AMS IP integration and re-use Distributed design/verification management Resource required for methodology (metricdriven verification, model-based) adoption Cost of design/silicon re-spin Verification teams have to deal with compounding low-power and mixed-signal verification challenges

3 Mixed-Signal Verification Flow Analog Domain Schematic Env. Analog Design Requirements Device Specs vplan Digital Domain MDV Digital Design Analog Verification Mixed Signal MDV with UVM-MS Block-Level Verification SV/UVM Testbench RF Receiver/ Transmitter FM Receiver/ Transmitter Audio Analog Modeling Bluetooth TV Real Number Model Creation PMU Communication Processor Image Processor LCD Driver Model vs Schematic Verification Cadence Design Systems, Inc. All rights reserved. PLL Application Processor DSP SV/UVM Testbench

4 Metric Driven Verification (MDV) Planning with unified verification metrics TB Top Analog Wire UVC env agent Seq driver Real Numbers seq seq seq Measure / Analyze Functional Specification Metric-based Executable Verification Plan Plan Execute Construct Cadence Design Systems, Inc. All rights reserved. Yes, for Analog and MS as well! Code reuse and structure Common, well-understood testbench structure Separation of interface code from DUT specific code Common file names and directory structure Randomization of stimulus Explore combinations of stimulus and device config Common, powerful test writing interface, reducing test-writing and maintenance effort Enable fewer simulations to reach spec-verification complete Automatic checking Verifies correct device behavior for all possible stimulus variations Combination of behavioral code and assertions Verification tracking using functional coverage Useful in risk mitigation and functional verification sign-off DUT-Specific and Customizable Monitor VAMS gasket Waveform Generator To DUT wreal/electrical Bias 0 0 Phase Period BFM Signal Map CTRL CTRL CTRL Sampler Measures and Drives: Amplitude

5 Level of Abstraction Real Number Modeling Benefits Much faster filtering of functional bugs early in verification process Significant increase in verification coverage Higher verification and design productivity Benefit Model development time and effort Accuracy, level of details Languages Analog Performance Simulation Continuous, Time-Based SPICE Electrical: Verilog-A Verilog-AMS VHDL-AMS Functional Verification Real Number Model Simulation Performance Pure Digital Logic Discrete, Event-Based Cadence Design Systems, Inc. All rights reserved. Model what you need, not what you can Clearly define model limitations Top-down approach Generate models during architecture phase Verify specifications early in the design cycle Allow designers to compare their functionality early with expected results Swap more detailed models as they become available Bottom-up approach Requires schematics to be ready Recognize modeling as discipline/job Share information across groups Pin list (type, allowed values, relations) Modeling engineer analog designer Analog SoC handoff Automate as much as possible

6 SystemVerilog (SV) Standardization for Mixed-Signal Designs Purpose Address needs for efficient, mixed-signal verification solution, in collaboration with industry experts by create a solid foundation of SV-AMS semantics in the standard SV-DC (RNM part of IEEE 1800 SystemVerilog standard) First SV-DC (RNM) version released in 2012, next major update targeted for release in 2019 SV-AMS Intended to be a part of IEEE standard To be based on core technology of proposed IEEE 1800 SystemVerilog 2019 standard With proposed extensions for RNM, SV-AMS is expected to be rolled out in 2020/ Cadence Design Systems, Inc. All rights reserved.

7 Uniting AMS IP and MS SoC Verification AMS IP Verification MS SoC Verification Use SoC testbench to validate AMS IP in the same context SV UVM bench Provide IP in a form easy to integrate in SoC verification Cadence Design Systems, Inc. All rights reserved.

8 Low-Power Mixed-Signal Simulation Support in AMS Signal path: Low-power intent is correctly interpreted between digital and analog driver/receiver Pwr VDD2 VDD1 SW D SW A Low-Power-Aware Signal Path Supply path: Low-power connection is correctly established, and both analog and digital power supplier/consumer are connected VSS VDDA2 VDDA1 VSSA SW A SW D Low-Power-Aware Supply Connection Cadence Design Systems, Inc. All rights reserved.

9 Mixed-Signal Low-Power Simulation Typical types of supply-path configuration VDD2 VDD1 SW Connection Power Supply Network Type 1 (Top-level behavioral simulation) Type 2 (Traditional low-power simulation) Type 3 (CPF/1801 on top entire design) Type 4 (Mixedsignal supply connection) Digital Power Digital Design Block Digital Power Supply CPF/1801 CPF/1801 CPF/1801 Electrical Connection CPF/1801 CPF/1801 CPF/1801 CPF/1801 VSS Design Block Logic Logic Logic Logic VDDA2 VDDA1 SW Connection Analog Power Supply Behavior Electrical CPF/1801 Electrical Connection Behavior Electrical CPF/1801 CPF/1801 Analog Power VSSA Analog Design Block Design Block Behavior Electrical Electrical Electrical Cadence Design Systems, Inc. All rights reserved.

10 I n t e g r a t i o n a n d A u t o m a t i o n Cadence Mixed-Signal Verification Solution Bridging the gap, addressing complexity TB Development Sim. Management (Virtuoso Analog Design Environment) Analog Modeling (SMG) Multi-Mode Simulation (MMSim) A/D Co-Simulation (Virtuoso AMS Designer) Transistor Simulation (Spectre ) FastSPICE (Spectre XPS) Metric-Driven Verification Methodology UVM Mixed Signal PSL / SVA Assertion Functional Coverage (Incisive vmanager) RNM Simulation Multi-Language Simulation (Incisive /Xcelium ) Logic Simulation (Incisive/Xcelium) Emulation (Palladium Z1) A b s t r a c t i o n L e v e l Analog High Accuracy Digital High Simulation Throughput Virtuoso Analog Design Environment (ADE) Verifier Integration with Incisive vmanager Solution UVM Mixed-Signal Analog and MS Assertions Extensive RNM Support MS / LP Simulation Continuous Performance Improvement in Spectre and Incisive/Xcelium Planning Metrics Modeling Simulation Cadence Design Systems, Inc. All rights reserved.

11 IOMSLPT for Verification Engineers Summary IOT products are dependent on efficient mixed-signal and low power functionality Transistor level + direct test are necessary but insufficient verification approaches Call to action Learn about SystemVerilog RNM Establish a MDV for mixed-signal and low power Verify deeply and efficiently!! Cadence Design Systems, Inc. All rights reserved.

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