Formal Contribution towards Coverage Closure. Deepak Pant May 2013
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1 Formal Contribution towards Coverage Closure Deepak Pant May 2013
2 Agenda 1. Incisive Metric Driven Verification 2. Coverage Unreachability App 3. Enriched Metrics Formal Contribution to MDV 4. Summary Cadence Design Systems, Inc. All Rights Reserved
3 Incisive Metric-Driven Verification (MDV) Use Enterprise Planner to bind assertions and checks goals to features; generate the vplan Spec Design Specification Plan Write new assertions, or use Assertion Based VIP Measure / Analyze Construct output_ready:assert property Execute Contributions from multiple technologies shown in a unified view IFV/IEV IES-XL IFV IFV IFV HW IFV Run formal or dynamic assertions in parallel Unicov Unicov Unicov Database Database Database UniCov DB Cadence Design Systems, Inc. All Rights Reserved Unicov Unicov Unicov Database Database Database UniCov DB Unicov Unicov Unicov Database Database Database UniCov DB
4 Agenda 1. Incisive Metric Driven Verification 2. Coverage Unreachability App 3. Enriched Metrics Formal Contribution to MDV 4. Summary Cadence Design Systems, Inc. All Rights Reserved
5 System Integrator Verification Engineer Designer Verification Apps Across the Project Life Cycle RTL Design Testbench Development RTL Refinement IP Verification Integration Project Start RTL partially available Testbench Ready Feature/Protocol Finished Verification Closure System Tapeout Super Linting Protocol Compliance Coverage Unreachability Analysis Register Map Validation SoC Connectivity Cadence Design Systems, Inc. All Rights Reserved
6 The Dead Code Challenge module multiplexor4_1 (out, in1, in2, in3, in4, cntrl1, cntrl2); output out; input in1, in2, in3, in4, cntrl1, cntrl2; reg out; or in2 or in3 or in4 or cntrl1 or cntrl2) case ({cntrl1, cntrl2}) 2'b00 : out = in1; 2'b01 : out = in2; 2'b10 : out = in3; 2 lines are uncovered 2'b11 : out = in4; default : $display("please check control bits"); endcase endmodule Question: Is the uncovered code reachable or unreachable? Test suite is insufficient. BAD! Fix RTL or discard hole. OK! Cadence Design Systems, Inc. All Rights Reserved
7 The Coverage Hole Problem Design & Testbench Simulation Coverage Database Run simulation and collect metrics Review metrics in IMC Uncovered items Create more tests! Question: Is the uncovered item reachable or unreachable? Cadence Design Systems, Inc. All Rights Reserved
8 Coverage Unreachability App Overview Fully Automated! Design & Testbench Simulation Regression Incisive Enterprise Verifer Holes N Unreachable? Y Coverage Database no action Merge Unreachable Coverage Database Leverage formal to determine if holes are reachable Block code coverage Expression code coverage But: automated flow no formal/abv knowledge required! And: Independent of testbench methodology! Cadence Design Systems, Inc. All Rights Reserved
9 Results Handling Fully Automated! Design & Testbench Simulation Regression Incisive Enterprise Verifer Holes N Y Unreachable? Coverage Database no action Merge Unreachable Coverage Database Only unreachable holes are reported Merge unreachable database into original simulation database Cadence Design Systems, Inc. All Rights Reserved
10 Result Reviewing Focus your effort Fully here Automated! Exclude Design & Testbench UNR Simulation Regression Incisive Enterprise Verifer Holes 100% N Y Unreachable? Exclude Coverage Database no action Merge Unreachable Coverage Database Read in merged database (simulation + unreachable) User to accept UNR by converting into Exclude RESULT: Enhanced code coverage as elements found to be unreachable are now annotated as Exclude Cadence Design Systems, Inc. All Rights Reserved
11 Customer Feedback Successful adoption at multiple customers Feedback and impressions Easy to use Good performance Saves a lot of review cycles for hole analysis Tech. paper: Freescale Bangalore at CDNLive! India mary.aspx > I. Silicon Realization: Functional Verification > Session 1.6 : Innovative Approach To Coverage Closure Through Unreachability Analysis Flow Cadence Design Systems, Inc. All Rights Reserved
12 Fujitsu Article in EETimes Cadence Design Systems, Inc. All Rights Reserved
13 Agenda 1. Incisive Metric Driven Verification 2. Coverage Unreachability App 3. Enriched Metrics Formal Contribution to MDV 4. Summary Cadence Design Systems, Inc. All Rights Reserved
14 Enriched Metrics Incisive Enterprise Verifier Dynamic Simulation Formal Engines Formal & Dynamic sim results automatically annotated to the vplan Verify formal assumptions Highlight unreachability Take credit for formal work Cadence Design Systems, Inc. All Rights Reserved
15 Report Functional Unreachables Simulation coverage hole But can it be reached!?!? Formal says NO! Cadence Design Systems, Inc. All Rights Reserved
16 UVM + IEV = Multi-Engine UVM Module UVC Scoreboard Coverage UVM Testbench DUT I/F UVC Mon Mon VC3 CPU Mem BFM BFM SEQR Mon DRV A A SV Interface Create Passive Test Replay all formal witnesses in the PASSIVE UVM environment Formal contributes Scoreboard failures Covergroup filling Code coverage Etc Virtual Sequencer A Periph SV Interface Mon Mon Mon A BFM BFM DRV Periph A SV Interface Mon Mon Mon BFM BFM DRV Bring results together using EMGR SEQR SEQR Protocol1 VC3 UVC Protocol2 VC3 UVC Cadence Design Systems, Inc. All Rights Reserved
17 Agenda 1. Incisive Metric Driven Verification 2. Coverage Unreachability App 3. Enriched Metrics Formal Contribution to MDV 4. Summary Cadence Design Systems, Inc. All Rights Reserved
18 Summary The Coverage Unreachability App automates post-simulation coverage hole analysis TB and DUT independent Minimal tool knowledge is required Reduces time to verification closure Unreachables can be analyzed or removed from the master RTL/coverage database Easy to setup, quick to run, increases overall productvity Formal MDV & Coverage Unreachability a key tool for Coverage Closure Bottom Line Formal MDV & Coverage Unreachability a key tool for Coverage Closure Cadence Design Systems, Inc. All Rights Reserved
19 Documentation and Webinars Incisive Enterprise Verifier User Guide Chapter 5: Analyzing Unreachable Coverage <root>/doc/ievuser/ievuser.pdf Archived webinars Formal Apps to Automate Mainstream Verification Challenges What to Do When Code Coverage Closure Seems Impossible Cadence Design Systems, Inc. All Rights Reserved
20 Cadence Design Systems, Inc. All Rights Reserved
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