PRIMENA MIKROKONTROLERA- MS1PMK 2. deo. Nenad Jovičić
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1 PRIMENA MIKROKONTROLERA- MS1PMK 2. deo 2017 Nenad Jovičić
2 Cortex-M3 procesor baziran na ARMv7-M arhitekturi RISC procesor Harward arhitektura
3 Cortex-M3 core periferije NVIC (Nested Vector Interrupt Controller) integrisani prekidni kontroler koji omogućava procesiranje prekida sa malim kašnjenjem WIC (Wakeup Interrupt Controller) opcioni kontroler zahteva za buđenje iz režima smanjene potrošnje. SYSTICK sistemski tajmer tj. 24-bitni brojač na dole namenjen za podršku generisanju sistemskog prekida za operativne sisteme. MPU (Memory Protection Unit) opciona jedinica za kontrolu pristupa pojedinim regionima u memoriji ETM (Embedded Trace Macrocell) modul koji obezbeđuje logovanje izvršavanja instrukcija DWT (Data Watchpoint and Trace Unit) modul koji implementira data watchpoint FPB (Flash Patch and Breakpoint Unit) modul koji omogućava preusmeravanje izvršavanja programa iz CODE memorije u neki drugi deo memorije.
4 Tipična arhitektura Cortex-M3 mikrokontrolera
5 Registri procesora Registri opšte namene: 13 registara opšte namene, r0-r12 Pokazivač steka SP (r13) Link registra LR (r14) Programski brojač PC (r15) Registri r0-r7 (niži registri) su dostupni preko svih instrukcija Registri r8-r12 (viši registri) su dostupni preko svih 32-bitnih instrukcija. Specijalni registri: Programski statusni registar xpsr Registri za kontrolu prekida PRIMASK, FAULTMASK, BASEPRI Kontrlni registra CONTROL
6 Registri procesora Registri Cortex-M3 je Load/Store arhitektura, što opšte značinamene: da se memoriji pristupa samo preko 13 registara opšte namene, r0-r12 Pokazivač Load/Store instrukcija, a sve druge operacije sesteka SP (r13) Link registra LR (r14) obavljaju samo nad registrima. Programski brojač PC (r15) Zato je bitno da postoji što veći broj registara Registri r0-r7 (niži registri) su dostupni direktno povezanih na CPU. preko svih instrukcija Registri r8-r12 (viši registri) su dostupni preko svih 32-bitnih instrukcija. Specijalni registri: Programski statusni registar xpsr Registri za kontrolu prekida PRIMASK, FAULTMASK, BASEPRI Kontrlni registra CONTROL
7 SP Stack pointer Registar koji se fizički realizuje kao dva 32-bitna registra. Main Stack Pointer (MSP) ovaj registar je podrazumevani registar posle reseta i mogu da ga koriste i korisnički program i prekidne rutine. U slučaju korišćenja operativnog sistema, ovaj registar koriste Kernel i prekidi, kao i neki delovi korisničkih Thread-ova sa posebnim privilegijama. Process Stack Pointer (PSP) ovaj registar je namenjen za korišćenje od strane neprivilegovanih delova softvera. Na primer, to su korisnički Thread-ovi u Operativnom sistemu. Može da se koristi samo u Thread modu. U zavisnosti od odgovarajućeg konfiguracionog bita u CONTROL registru pristupa se jednom ili drugom od ova dva registra. Jednostavne aplikacije bez OS-a uglavnom korsite samo MSP. Kod Cortex-M3 familije stek je realizovan kao Full Descending Stack, što znači da stek raste prema nižim adresama i pokazuje na poslednju zauzetu adresu. Sve PUSH i POP operacije su 32-bitne. Najniža dva bita SP-a su uvek jednaka nuli jer se radi samo sa 32-bitni veličinama. Nakon reseta inicijalna vrednost MPS-a se hradverski inicijalizuje na vrednost sa početka momorije, a vrednost PSP-a je nedefinisana.
8 LR Link Register LR se koristi za čuvanje adrese povratka iz potprograma - na primer kada je skok izvršen BL (Branch with Link) instrukcijom: Osim ovoga koristi se i pri povratku iz prekidne rutine.
9 Statusni registri Application Program Status Register, APSR Sadrži flegove koje koristi korisnički neprivilegovani aplikativni softver Interrupt Program Status Register, IPSR Sadrži broj izuzetka/prekida koji se trenutno izvršava Execution Program Status Register, EPSR Sadrži specijalne flegove koji kontrolišu rad procesora. Na primer biti ICI/IT se koriste za kontrolu prekidanja uslovnih blokova instrukcija i instrukcija koje rade višestruke Load/store operacije (LDM/STM)
10 Statusni registri Application Program Status Register, APSR Sadrži flegove koje koristi korisnički neprivilegovani aplikativni softver Interrupt Program Status Register, IPSR Sadrži broj izuzetka/prekida koji se trenutno izvršava Execution Program Status Register, EPSR Sadrži specijalne flegove koji kontrolišu rad procesora. Na primer biti ICI/IT se koriste za kontrolu prekidanja uslovnih blokova instrukcija i instrukcija koje rade višestruke Load/store operacije (LDM/STM)
11 Aritmetika sa saturacijom Q flag je setovan nakon operacije u kojoj se pojavi saturacija. Takve instrukcije uglavnom počinju sa Q, kao na primer QADD, QSUB...
12 Registri za kontrolu prekida Pristup ovim registrima je dozvoljen samo u privilegovanom režimu rada softvera. Setovanje PM bita u PRIMASK registru maskira sve prekide osim NMI i HardFault prekida. Setovanje FM bita u FAULTMASK registru maskira sve prekide osim NMI prekida. BASEPRI registra definiše nivo prioriteta prekida kojima je dozvoljeno generisanje.
13 Pristup registrima kontrole prekida Iz C-a: Iz Asembler-a:
14 CONTROL registar
15 CONTROL registar Control registar poseduje samo dva bita (3 ako postoji FPU). Njime se kontroliše korišćenje steka i nivo privilegije softvera. Control registar može da se menja samo iz privilegovanog softvera. Bit 2 (FPCA) govori da li se FPU koristi ili ne.
16 Stanja i režimi rada procesora Dva stanja thumb (radno stanje) i debug (zaustavljen rad) Dva režima rada procesora thread i handler režim. Dva nivoa privilegija privilegovani nivo (OS, prekidi) i neprivilegovani (korisnički softver).
17 Režimi privilegija softvera Privilegovani režim: U njega se automatski prelazi ulaskom u prekid. Potpuno su dostupni svi sistemski resursi. U ovom režimu je moguće menjati nivo privilegije. Neprivilegovani ili tzv. korisnički režim: Uobičajeni režim običnog korisničkog programa. Nisu dostupni svi sistemski resursi. Promena nivoa privilegija moguća samo nakon prekida. Za razliku od režima rada procesora, nivo privilegija se menja programski.
18 Privilegovani/neprivilegovani rad Promena nivoa privilegije je moguća samo u privilegovanom modu rada. U prekidu je moguće uticati na nivo privilegije prilikom povratka u thread režim procesora. OS aplikacije Jednostavne aplikacije
19 Jednostavne OS aplikacije Softver je praktično uvek privilegovan, ali se deo softvera koji je Kernel OS-a izvršava na MSP steku, a deo softvera koji je korisnički na PSP steku.
20 Floating Point Unit Registri Sx su u osnovi 32-bitni (single precision). Grupisanjem se može efektivno dobiti dvostruka preciznost (Dx).
21 Cortex-M povezivanje sa periferijama
22 Magistrale
23 Magistrale ICode memorijska magistrala bazirana na AHB-Lite standardu koristi se za prenos instrukcija iz Code adresnog prostora (0x do 0x1FFFFFFF). Dcode memorijska magistrala bazirana na AHB-Lite standardu koristi se za prenos podataka iz Code adresnog prostora (0x do 0x1FFFFFFF). System memorijska magistrala bazirana na AHB-Lite standardu koristi se za prenos i instrukcija i podataka iz System adresnog prostora (0x do 0xDFFFFFFF i 0xE do 0xFFFFFFFF). Uglavnom za RAM I periferije. PPB magistrala pristup internim i eksternim privatnim periferijama, komponentama Debug sistema,
24 AMBA advanced microcontroller bus architecture High Performance ARM processor APB UART High Bandwidth External Memory Interface AHB APB Bridge Timer Keypad High-bandwidth on-chip RAM DMA Bus Master PIO AHB advanced high-performance bus Visoke performanse Protočni prenos Burst prenosi Višestruki masteri APB advanced peripheral bus Niska potrošnja Mala brzina Jednostavan interfejs Veza sa Slave periferijama
25 Cortex-M3 Pipeline Trostepeni fetch-decode-execute pipeline U prefetch buffer može da se učita 72 bita, tj. tri 32-bitne ili šest 16-bitnih instrukcija ili njihova kombinacija. Na ovaj način je omogućena jednociklusna realizacija direktnih skokova. Indirektni skokovi su oni koji se izračunavaju u toku run-time-a. Zbo ovoga Cortex-M odskače od tradicionalnih RISC procesora. 1 st Stage - Fetch 2 nd Stage - Decode 3 rd Stage - Execute AGU Address Phase & Write Back Data Phase Load/Store & Branch Fetch (Prefetch) Instruction Decode & Register Read Multiply & Divide Write Branch forwarding & speculation Branch Shift ALU & Branch Execute stage branch (ALU branch & Load Store Branch)
26 Značaj prefetch buffer-a
27 Pipeline Fetch učitavanje instrukcije iz memorije i smeštanje u prefetch buffer Decode dekodiranje instrukcije i pripremanje kontrolnih signala koij regulišu protok podataka Execute Očitavanje registara, pomeranje operanda, generisanje rezultata operacije (ALU) i upisivanje rezultata odredišni registar.
28 Interna struktura CPU-a Registarska banka: 2 porta za čitanje, 1 port za upis 1 dodatni port za čitanje i 1 dodatni port za upis u PC Barrel pomerač Pomera za bilo koji broj bita ALU Adresni registar i inkrementer Data registar koji čuva podatke koji se razmenjuju sa memorijom Dekoder instrukcija i sa njim povezan kontrolni blok celog sistema
29 Optimalni pipeline Sve instrukcije su nad registrima Efektivno dobijamo instrukciju po ciklusu
30 Optimalni pipeline obrada podataka
31 Arhitektura instrukcijskog seta ISA Instruction set architecture Instruction set architecture (ISA) is the structure of a computer that a machine language programmer (or a compiler) must understand to write a correct (timing independent) program for that machine IBM introducing 360 in 1964
32 Glavni elementi arhitekture instrukcijskog seta 32-bits mov r0, #1 ld r1, [r0,#5] mem((r0)+5) bne loop subs r2, #1
33 ARM/Thumb instrukcijski set Tradicionalni ARM set: fiksna dužina od 32 bita Dva ili tri operanda Radi se sa podacima u registrima Memorijske transferi se obavljaju samo kroz Load/Store instrukcije Uslovno izvršavanje instrukcija Originalni Thumb instrukcijski set: Implemenaticija određenih instrukcija iz ARM seta, ali sa 16 bita Većina Thumb instrukcija ima dva operanda, tj. Jedan od izvorišnih je i odredišni operand Nisu dostupni registri r8 do r15 Nema uslovnog izvršavanja ARM coding
34
35 ARM/Thumb instrukcijski set Primer implementacije instrukcije sabiranja na ARM i Thumb formatu: -nema uslovnog izvršavanja -nema rotacije neposrednog operanda -statusni flagovi se uvek postavljaju (nema S)
36 Prelaz sa ARM na Thumb i obrnuto Kod ranijih ARM arhitektura prebacivanje sa jednog na drugi instrukcijski set je posedovalo značajan overhead.
37 Thumb-2 Thumb-2 obuhvata i 16-bitne i 32-bitne instrukcije. Napravljen je sa osnovnom idejom da se izbegne potreba za izmenom režima rada procesora. Thumb-2 je zadržao skoro sve insturkcije starijeg Thumb seta i implementirao većinu instrukcija iz ARM seta. Veći deo instrukcija može da se prevede i u 16-bitni i u 32-bitni format u zavisnosti od parametara konkretne instrukcije. Odluku o implementaciji donosi kompajler osim u slučaju kada se implicitno traži jedna ili druga implementacija.
38 16-bitne Thumb-2 instrukcije
39 32-bitne Thumb-2 instrukcije Ako učitana reč (16 bita) sadrži najviših 5 bitova sledećeg sadržaja: 0b b b11111 instrukcija je 32- bitna, tj. Dekodira se i sledeća reč.
40 Primer instrukcije ADD (sabiranje) kada se radi nad registrima. U zavisnosti od upotrebljenih registara ili opcionih polja u instrukciji moguće su različite vrste kodiranja instrukcije. To se u krajnjoj liniji reflektuje na gustinu koda. 16 ili 32 bita?
41 Poređenje performansi instrukcijskih setova Instrukcijski set promenljive dužine ARM instrukcije su bile isključivo 32-bitne Thumb instrukcije su bile isključivo 16-bitne Thumb-2 instrukcije mogu da budu i 16-bitne i 32-bitne, Thumb-2 daje za oko 26% veću gustinu koda od ARM Thumb-2 daje za oko 25% veće performanse u odnosu na Thumb
42 Instrukcijski set kod Cortex-M processora Sa stanovišta korisnika Cortex-M4 se razlikuje od Cortex-M3 procesora u proširenom instrukcijskom setu
43 Cortex-M instrukcijski set - poređenje M7 ima isti instrukcijsk i set kao M4.
44 Tipovi podataka ARM podržava tri tipa podataka: Byte 8-bitni podatak Halfword 16-bitni podatak Word 32-bitni podatak Pristup memoriji kod Cortex-M3 omogućava takozvani neporavnat (unaligned) pristup. Ali to ne važi kod nekih instrukcija. Na primer PUSH i POP rade samo aligned acces. Takođe i specijalne instrukcije za prenos blokova podataka.
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