Uvod u računarstvo. Preddiplomski studij elektrotehnike 2009/2010. prof.dr.sc. Ivo Ipšić UUR 2009/2010
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1 Uvod u računarstvo Preddiplomski studij elektrotehnike 2009/2010 prof.dr.sc. Ivo Ipšić 1
2 Saržaj kolegija Uvod u Uvod i razvoj računala računarstvo Zapis podataka i kodiranje informacija u računalu Građa računala Programska oprema računala Računalne mreže Uvod u programiranje i programski jezik C 2
3 Sadržaj Model računala von Neumannova arhitektura računala Elementi računala Pojednostavljen model računala Izvršavanje instrukcija 3
4 John von Neumann ( ) ideja: zajedničko pohranjivanje podataka i programa u memoriji računala slijedeći korak programa ovisi o prijašnjem predložena arhitektura za EDVAC (Electronic Discrete Variable Automatic Computer) postaje poznata pod imenom von Neumanova arhitektura računala 4
5 Model von Neumannovog računala UPRAVLJAČKI SKLOP ARITMETIČKO - LOGIČKA JEDINICA CPU ULAZNA JEDINICA MEMORIJA IZLAZNA JEDINICA Tok podataka i instrukcija Upravljački signali 5
6 Mikroprocesor Intel Pentium 6
7 Model računala CPU chip register file ALU system bus memory bus bus interface I/O bridge main memory USB controller graphics adapter I/O bus disk controller Expansion slots for other devices such as network adapters. 7 mouse keyboard monitor disk
8 Komponente računala 8
9 Komponente računala centralna procesna jedinica (CPU) ili mikroprocesor obavlja upravljačke operacije i obradu podataka memorija glavna ili radna memorija pohranjuje instrukcije programa i podatke ulazno/izlazni sklopovi služe za unos podataka u računalo i prikaz rezultata obrade sustav sabirnica omogućava prijenos podataka, instrukcija, adresa i upravljačkih signala između mikroprocesora, memorije i ulazno/izlaznih uređaja 9
10 CPU (Central processing unit) storage input/output control unit ALU memory registers registers flags cache memory 10
11 CPU aritmetičko logička jedinica (ALU): izvršava aritmetiče i logičke operacije na podacima zapisanim u registre prema naredbama upravljačkog sklopa registri mikroprocesora: privremena pohrana podataka i instrukcija provides temporary storage for data and instructions. registri upravljačkog sklopa: instrukcijski registar csadrži instrukciju koja se izvršava programsko brojilo (instruction pointer) sadrži adresu sljedeće instrukcije registri aritmetičko logičkog sklopa akumulator sadrži operande i rezultate aritmetičkih i logičkih operacija 11
12 CPU interne sabirnice mikroprocesora: povezuju upravljački sklop, ALU i registre upravljački sklop: upravlja operacijama mikroprocesora, interpretira, dekodira instrukcije, prenosi podatke među registrima, upravlja ALU,... priručna memorija (cache) : sadrži skup instrukcija i podataka koje mikroprocesor koristi za izvršavanje 12
13 Memorije mikroprocesora 13
14 Sabirnice mikroprocesora Control Bus RAM ROM Microprocessor (CPU) Data Bus Address Bus Input/Output (I/O) 14
15 Sabirnice (BUS) spojni putovi vodovi povezuju dijelove računala adresna sabirnica prijenos adresa instrukcija i podataka potrebnih za operacije čitanja i pisanja podatkovna sabirnica prijenos podataka i instrukcija dvosmjerna komunikacija upravljačka sabirnica prijenos upravljačkih i sinkronizacijskih signala 15
16 16
17 Memorija memorijska hijerarhija CPU veća brzina registri i cache RAM vanjska memorija veći kapacitet 17
18 RAM Random Access Memory 18 svaki podatak u memoriji ima svoju jednoznačnu adresu u memoriji se pohrajuju podaci i programi kapacitet memorije 1 bajt = 8 bita 1 kilobajt [KB]= 1024 bita 1 megabajt [MB] = 1024 kilobajta 1 gigabajt [GB ]= 1024 megabajta
19 ROM Read Only Memory sadrži BIOS (Basic Input/Output System-instrukcije koje pokreću operacijski sustav) sadržaj ROM memorije se zapisuje u postupku proizvodnje, kod pokretanja računala čitaju se podaci o računalnom sustavu (tip mikroprocesora, radna memorija,...) 19
20 Vanjska memorija - disk 20
21 Memorija svaki podatak u memoriji ima svoju jednoznačnu adresu u memoriji se pohrajuju podaci i programi postupci pisanja i čitanja preko dva registra: MAR i MDR 21
22 Memorija kapacitet memorije 1 bajt = 8 bita 1 kilobajt [KB]= 1024 bita 1 megabajt [MB] = 1024 kilobajta 1 gigabajt [GB ]= 1024 megabajta 22
23 Memorija - čitanje zapisuje se adresa podatka koji se čita u registar MAR; generiraju se upravljački signali na liniji za čitanje, koji omogućavaju da se sadržaj memorijske lokacije zapisane u MAR prenese u registar MDR; nakon operacije čitanja podatak se nalazi u MDR; vrši se prijenos podatka iz registra MDR u ciljni registar. 23
24 Memorija - pisanje zapisuje se adresa na koju želimo pohraniti podatak u MAR; podatak se prenosi u registar MDR; generiraju se upravljački signali, koji vrše prijenos podataka iz MDR u memoriju na adresu zapisanu u registru MAR; nakon operacije pisanja podatak se nalazi u memoriji 24
25 Memorijska hijerarhija L0: registri L1: L1 cache (SRAM) L2: L2 cache (SRAM) L3: radna memorija (DRAM) L4 : sekundarna memorija (lokalni diskovi) 25 L5: distribuirana sekundarna memorija ( distribuirani datotečni sustavi, web serveri)
26 Ulazno/izlazne jedinice 26 ulazna jedinica - služi za unos podataka iz vanjskog svijeta memoriju računala: tipkovnica, miš, mikrofon, kamera izlazna jedinica - služi za prikaz obrađenih podataka: monitor, štampač, ploter, zvučnik
27 CPU sastoji se od aritmetičko-logičke jedinice, upravljačke jedinice i registara: akumulator (AR), brojilo instrukcija (PC registar), instrukcijski registar (IR), indeksni registar (IX), statusni registar (SR),... 27
28 Izvršavanje instrukcija 2 faze: pribavi instrukciju (fetch) adresa instrukcije iz PC MAR signal za čitanje sadržaj iz MDR IR izvrši instrukciju (execute) dekodiraj instrukciju izvrši instrukciju PC PC
29 Instrukcijski ciklus pribavi instrukciju pribavi operande pohrani operande izračun adrese instrukcije dekodiraj instrukciju izračunaj adresu operanada izvrši instrukciju izračunaj adresu operanada 29
30 Računalni sustav 30
31 Model pojednostavljenog mikroprocesora MAR MDR PC AR IR dekoder ALU upravljački sklop piši čitaj takt φ 31
32 Izvođenje jednog instrukcijskog ciklusa MAR MDR PC AR IR dekoder ALU upravljački sklop piši čitaj 32 takt φ
33 Faza pribavi instrukciju MAR MDR PC AR IR dekoder ALU upravljački sklop piši čitaj 33 takt φ
34 Faza izvrši instrukciju MAR MDR PC AR IR dekoder ALU upravljački sklop piši čitaj 34 takt φ
35 Faza izvrši instrukciju 2 MAR MDR PC AR IR dekoder ALU upravljački sklop piši čitaj 35 takt φ
36 Primjer faze izvrši za instrukciju MVT MAR MDR PC AR IR ALU dekoder upravljački sklop piši čitaj 36 takt φ
37 Pribavi operand MAR MDR AAAA0000 PC AR IR ALU dekoder upravljački sklop piši čitaj 37 takt φ
38 Izvrši MVT MAR MDR AAAA0000 PC AAAA0000 AR IR dekoder ALU upravljački sklop piši čitaj 38 takt φ
39 Jezik mikroprocesora instrukcije se izvršavaju u dvije faze: pribavi i izvrši instrukciju OP 1 AM ADRESA OP - operacija, instrukcijski kod AM - način adresiranja polje operacijskog koda bit 4 = 1 32 bitna instrukcija 39
40 Elementi procesora SAP memorija 2 24 = riječi (16MB) dužina riječi 32 bita dostup do 4 registra akumulator AR 32 bitni indeksni registar IX 24 bitni registar stoga SP 24 bitni statusni registar SR 8 bitni 2 registra do kojih programer nema pristupa programsko brojilo PC 24 bitni registar instrukcijski registar IR 32 bitni 40
41 Elementi procesora SAP format instrukcija 32 bitne i 16 bitne instrukcije OP 1 AM ADRESA OP - operacija, instrukcijski kod AM - način adresiranja polje operacijskog koda bit 4 = 1 32 bitna instrukcija 41
42 Format instrukcije polje operacijskog koda što treba izvršiti adresno polje nad kojim podaci treba izvršiti jednoadresne ili višeadresne instrukcije 42
43 Primjer operacije zbrajanja zbrojiti operande na memorijskim lokacijama 1000 i 1001, te rezultat pohraniti na memorijskoj lokaciji jednoadresne instrukcije MVT ADD MVF triadresne instrukcije ADD 1000,1001,
44 Načini adresiranja bit način adresiranja 000 direktni ili izravni 001 indirektni ili posredni mnemotehnička oznaka MVT ADDR MVT (ADDR) 010 indeksni MVT ADDR,X posredni indeksni MVT (ADDR),X 100 neposredni MVT #ADDR
45 Direktno adresiranje hex MVT AR A 1C 7 3FFE A 1 C 7 3FFE 45
46 Indirektno adresiranje hex MVT A7B 246A7B F F A E AR A E
47 Indeksno adresiranje hex MVT F641 AR 39F D D IX
48 Posredno indeksno adresiranje hex MVT A7B 446A7B F IX AR F641 3 A 5 9 C A59C240 48
49 Neposredno adresiranje bin MVT BR AR 49
50 Instrukcije mikroprocesora SAP aritmetičke logičke naredbe prijenosa podatak naredbe grananja naredbe posmaka i rotacije 50
51 Aritmetičke instrukcije SUC SUB ADC ADD subtract operands with carry subtract operands add operands with carry add operands 51
52 Logičke instrukcije ORA AND XOR BIT logical OR of operands logical AND of operands exclusive OR of operands logical compare 52
53 Instrukcije prijenosa MVT move to A (load A) MVF move from A (store A) 53
54 Instrukcije grananja JSR JMP jump to subroutine jump to address 54
55 Instrukcije posmaka i rotacije LSR SHL ROR... logical shift right shift left rotate right 55
56 Primjeri aritmetičko logičke naredbe naredbe prijenosa podataka među registrima MVT SP,AR MVT AR #0 ADD IX #1 56
57 Primjeri programa zbrajanje Z=A+B pretpostavka da je cijeli broj A na memorijskoj lokaciji , broj B na memorijskoj lokaciji , te da broj Z treba pohraniti na memorijskoj lokaciji MVT upiši u akumulator broj A ADD zbroji A+B MVF zbroj pohrani na adresi
58 Primjer grananja if (n<0) i=j; else if(n==0) i=k; else i=l; pretpostavka da se varijabla n nalazi na memorijskoj lokaciji 100, a varijable i,j,k,l na memorijskim lokacijama 201,202,203,204 slijed naredbi počinje na adresi 4 58
59 Primjer grananja adresa naredba opis 4 MVT 100 u AR upiši n 5 BEQ 4 grananje ukoliko je n=0 6 BPL 6 grananje ukoliko je n>0 7 MVT 202 i=j n<0 8 MVF201 9 BRA 5 grananje na slijedeći blok instrukcija 10 MVT 203 i=k n=0 11 MVF BRA 2 13 MVT 204 i=l n>0 14 MVF
60 Primjer petlje traži se zbroj komponenti vektora x s=σx i i=1,..,n u višem programskom jeziku: s=0; for (i=0;i<n;i++) s=s+x[i]; 60
61 Primjer petlje pretpostavka da je n na memorijskoj lokaciji 200, a s na 199 vrijednosti komponenti vektora x počinju na simboličkoj adresi AX prevodioc će simboličku adresu pretvoriti u fizičku adresu npr. AX=201 61
62 Primjer petlje MVT AR #0 neposredno adresiranje u AR upisujemo 0 MVT IX #0 neposredno adresiranje u IX upisujemo 0 MVF 199 s=0 START MVT 200 u AR upisujemo dužinu vektora CMP AR,IX uspoređujemo IX i n BEQ END MVT 199 upiši s u AR ADD (AX),X s=s+x[i] neposredno indeksni način adresiranja MVF 199 ADD IX #1 BRA START END HLT 62
63 Pisanje na stog dno stoga R vrh stoga R SP POP R1
64 Čitanje sa stoga dno stoga R vrh stoga R SP
65 Programi Z :=A + B; MVT 1024 ADD 1025 MVF
66 Prevođenje programa 66
67 Programski kod tekst C program (p1.c) prevodioc - compiler (gcc -S) tekst asemblerski program (p1.s) asembler (gcc, as) binarni kod objektni program (p1.o) binarni kod 67 Izvršni program (p)
68 Programski kod int zbroji(int x, int y) { int zbroj; } return zbroj=x+y; 68
69 Programski kod prevođenje izvornog programa u asmblerski kod gcc O2 S zbroji.c gcc - GNU compiler prikaz asembleskog programa objdump -d zbroji.s 69
70 Programski kod zbroji.o: file format pe-i386 Disassembly of section.text: <_zbroji>: 0: 55 push %ebp 1: 89 e5 mov %esp,%ebp 3: 8b 45 0c mov 0xc(%ebp),%eax 6: 8b mov 0x8(%ebp),%edx 9: 5d pop %ebp a: 01 d0 add %edx,%eax c: c3 ret d: 90 nop e: 90 nop f: 90 nop 70 objektni kod asemblerski kod
71 Programski kod instrukcija zbroji zbroj=x+y registri mikroprocesora 01 d0 add %edx,%eax bitna instrukcija 71
72 Pitanja Nariši shemu ispisne memorije ROM. Opiši postupak izvođenja jednog instrukcijskog ciklusa. Opiši djelove 16-bitne naredbe sa dvije adrese. Navedi primjere instrukcija. Skiciraj univerzalno (von Neumannovo) računalo. Opiši postupak čitanja i pisanja u memoriju. Opiši funkciju upravljačkog sklopa računala. Opiši postupak prevođenja programa u strojni jezik. 72
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