Overview. Installation Instructions. Teledyne LeCroy: quantumdata 980 Firmware Release 4.27 April 16, 2018 Release Notes

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1 Teledyne LeCroy: quantumdata 980 Firmware Release 4.27 April 16, 2018 Release Notes Overview This document provides information on Release 4.27 of the firmware and External Manager software release for the quantumdata 980B and 980R Advanced Test Platforms. For further information, please refer to the Quick Start Guide for the Advanced Test Platforms, and the User Guides for the individual modules, all available on our website at Major additions are new DisplayPort 1.4 Link Layer Compliance Tests, HDMI 2.1 earc functional testing and compliance testing for common mode, and HDMI Gbps FRL transmit via playback. See below for details. Installation Instructions Begin by installing the Windows External Manager software: 1. Download the External Manager, file type.msi 2. Download the Release ZIP file and unzip it (resulting file is type.deb) 3. Run the.msi file to install it. Then install the Instrument firmware Release. 4. Launch the newly downloaded External Manager (980 Manager) and connect to the 980 via Ethernet TCP/IP. (For information on the 980 network connections, please refer to the Advanced Test Platform Quick Start Guide and related erratum below.) a. Note: you may see a warning about version mismatch. This is normal, and indicates that you should continue with the version upgrade before using the instrument with the new version of the External Manager. 5. From the External 980 Manager program, pull down the Instrument menu and select Upgrade UI/Firmware/Gateware. Browse to and select the unzipped.deb file, select Open, and continue with the process. The 980 will power down at the end. If the 980 is licensed for HDR Lab Images (License 45): 6. Download the HDR Lab Images.deb file. 7. From the External 980 Manager program, pull down the Instrument menu and select Upgrade System Components. Browse to and select the hdr-lab-images.deb file, select Open and continue with the process. If the 980 is licensed for HDMI HDCP CTS 2.2 Compliance Test for Sinks (License 29): 8. Download the 980-hdcp2-sink-ct.deb file. 9. From the External 980 Manager program, pull down the Instrument menu and select Upgrade CT Scripts. Browse to and select the 980-hdcp2-sink-ct.deb file, select Open and continue with the process. 1

2 If the 980 is licensed for HDMI CTS 1.4b Compliance Test for Sinks (License 6): 10. Download the 980-hdmi-sink-ct.deb file. 11. From the External 980 Manager program, pull down the Instrument menu and select Upgrade CT Scripts. Browse to and select the 980-hdmi-sink-ct.deb file, select Open and continue with the process. To verify the installation: 1. After installing any necessary packages from above, press the front button and Reboot the View the Instrument Information report in one of the following ways: a. From the External 980 Manager, when connected to the 980, pull down the Instrument menu and select Information. b. From the External 980 Manager, when connected to the 980, locate the Instruments section in Navigator, right-click on the instrument, and select Information. c. From the 980 front panel touch screen, select the Other page and then select About the 980 Manager. 3. Verify the following version information from the Instrument Information report, for the specific versions of modules installed: a. Advanced Test platform Version: b. QDBUS: [Version: 2981 Build Number: 1 (07/05/ )] c. For each installed module Firmware: [Version: Build Number: (qd 04/13/ :03:27 CDT) ] d. DP Protocol Analyzer Rev D Gateware: [Version: Build Number: 1 (02/28/ :14:18 CST) PCB: 4/D rev=4, DP Product Code=2980] e. DP Protocol Analyzer Rev E (small fpga) Gateware: [Version: Build Number: 1 (02/28/ :14:18 CST) PCB: 5/E rev=4, DP Product Code=2980] f. DP Protocol Analyzer Rev E Gateware: [Version: Build Number: 1 (03/01/2018) PCB: 5/E rev=5, DP Product Code=2981] g. DP Protocol Analyzer Rev F Gateware: [Version: Build Number: 1 (03/01/ :08:18 CST) PCB: 6/F rev=6, DP Product Code=2982] h. DP Protocol Analyzer Gateware: [Version: Build Number: 1 (03/29/ :01:18 CST) PCB: 1/A rev=1, DP Product Code=2983] i. SDI Scope Gateware: [Version: Build Number: 32 (10/20/ :22:00) PCB: C] j. HDMI Video Generator Gateware: [Version: Build Number: 32 (06/19/ :36:00) PCB: 594b rev. B] k. HDMI Video Generator Gateware: [Version: Build Number: 32 (06/19/ :36:00) PCB: 594b rev. C] l. HDMI Protocol Analyzer Gateware: [Version: Build Number: 57 (05/22/2017) Gen: 3 PCB: 297b/D] m. HDMI Protocol Analyzer Gateware: [Version: Build Number: 43 (05/16/2017) Gen: 1 PCB: 594c/C] n. HDMI 2.0 HDMI 2.0 RX/TX Gateware: [Version: Build Number: 35 (03/19/2018) Gen: 5 PCB: 594d/A] o. HDMI 2.1 RX/TX Gateware: [Version: Build Number: 44 (04/11/2018) Gen: 5 PCB: 1200a/C] 2

3 p. Phy and Protocol Aux Channel Analyzer Gateware: [Version: Build Number: 12 (06/03/2016) PCB: 2/C] q. If the 980 is licensed for HDMI HDCP CTS 2.2 Compliance Test for Sinks (License 29): HDMI Sink CT: r. If the 980 is licensed for HDMI CTS 1.4b Compliance Test for Sinks (License 6): HDCP Src CT: Added the following features: HDMI 2.1 earc RX/TX Common Mode Tx & Rx Functionality (p/n =opt57, =opt58) (Differential mode audio functions will be available in a future release.) DisplayPort Compliance Test Package #3 (p/n =opt48) 1) Successful Link Training at All Supported Lane Counts and Link Speeds 2) Successful Link Training Upon HPD Plug Event 3) Successful Link Training with Request of Higher Differential Voltage Swing During Clock Recovery Sequence 4) Successful Link Training to a Lower Link Rate #1: Iterate at Maximum Voltage Swing 5) Successful Link Training to a Lower Link Rate #2: Iterate at Minimum Voltage Swing 6) Successful Link Training with Request of a Higher Pre-emphasis Setting During Channel Equalization Sequence 7) Successful Link Training at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence 8) Unsuccessful Link Training at Lower Link Rate #1: Iterate at Maximum Voltage Swing 9) Unsuccessful Link Training at Lower Link Rate #2: Iterate at Minimum Voltage Swing 10) Unsuccessful Link Training due to Failure in Channel Equalization Sequence (loop count > 5) 11) Successful Link Training with Simultaneous Request for Differential Voltage Swing during Clock Recovery & Channel Equalization Sequences 12) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Symbol Lock 13) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Clock Recovery Lock 14) Successful Link Re-training After IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock 15) Handling of IRQ HPD Pulse with No Error Status Bits Set 16) Lane Count Reduction and Increase 17) Video Time Stamp Generation 18) Audio Time Stamp Generation DisplayPort Compliance Test Package #4 (p/n =opt61) 1) Read One Byte from Valid DPCD Address 2) DPCD Receiver Capability Read (Read 12 Bytes from Valid DPCD Address) 3) Write One Byte to Valid DPCD Address 4) Write Nine Bytes to Valid DPCD Addresses 5) Write EDID Offset (One Byte I2C-Over-AUX Write) 6) Read One EDID Byte (One Byte I2C-Over-AUX Read) 7) EDID Read (1 Byte I2C -Over-AUX Segment Write, 1 Byte I2C-Over-AUX Offset Write,128 Byte I2C-Over-AUX Read) 8) Illegal AUX Request Syntax 9) Glitch Rejection 10) Interleaved EDID and DPCD Receiver Capability Read 11) Downstream Stop on MOT Reset 12) Downstream Stop on Timeout 3

4 13) Successful Link Training at All Supported Lane Counts and Link Speeds 14) Successful Link Training with Request of Higher Differential Voltage Swing During Clock Recovery Sequence 15) Successful Link Training to a Lower Link Rate Due to Clock Recovery Lock Failure During Clock Recovery Sequence 16) Successful Link Training with Request of a Change to Pre-Emphasis and/or Voltage Swing Setting During Channel Equalization Sequence 17) Successful Link Training at Lower Link Rate Due to Loss of Symbol Lock During Channel Equalization Sequence 18) Lane Count Reduction 19) Lane Count Increase 20) IRQ HPD Pulse Due to Loss of Symbol Lock and Clock Recovery Lock 21) IRQ HPD Pulse Due to Loss of Inter-lane Alignment Lock 22) Pixel Data Reconstruction 23) Main Stream Data Unpacking and Unstuffing Least Packed TU 24) Main Stream Data Unpacking and Unstuffing Most Packed TU 25) Main Video Stream Format Change Handling 26) Entering and Exiting Power Save Mode 27) Resumption of Main Link Activity After Extended Idle 28) Audio Startup and Format Change 29) Audio InfoFrame Packet 30) Audio Clock Recovery 31) Audio Stream Reception 32) Sink Organizationally Unique Identifier (OUI) 33) Sink Count 34) Sink Status 35) Symbol Error Count 36) Device Identifications 37) Number of Receiver Ports 38) Main Link Channel Coding HDMI 2.1 earc compliance tests : (p/n =opt59, =opt60) HFR earc Discovery With COMMA Width Margining HFR Command Behavior With Bit Time Margining HFR TX gets NACK indicating earc RX Busy HFR TX gets Common Mode Slow Response HFR earc Discovery With COMMA Response Margining HFR Command Behavior With Bit Time Margining HFR Behavior if no response to earc Discovery HFR earc RX gets Unexpected Device ID HFR earc RX gets new Opcode in the middle of a Command HFR earc RX gets Heartbeat Disconnect HFR earc RX gets HPD LOW during earc Discovery HFR earc RX gets HPD LOW after earc established HFR earc RX Receives RETRY indicating earc TX Error Detection HDMI 2.1 TX FRL Playback. The following formats are supported: (p/n =opt52) 4320p30dc p60dc 1080p60 4

5 2160p p120dc p p p p p60 The following enhancements, bug fixes, and changes were made: trac #2407 Fix DP 1.4 RX link training for sources with MAX pre-emphasis 0 trac #2405 Add 10b raw data file interpreter/decoder functionality trac #2394 DPCD? command max read size should not be limited to 16 bytes. Fixed. trac #2399 Verify and fix HSYNC/VSYNC polarity detection in HDMI timing analyzer trac #2415 Add EMP infoframe to the HDMI decode trac #2435 Add ACA to TX of HDMI2.1 card trac #2436 Link Training enhancements on HDMI2.1 TX (Non-adaptive, user controlled link training) trac #2416 Add EMP infoframe to the real-time fly-out window trac #2439 HDR Lab Clipping and other images have black values of zero instead of 64. Fixed. Software SKUs Newly Available with this Release option 52 HDMI 2.1 Generator playback mode option 57 HDMI 2.1 earc Tx Functional Test option 58 HDMI 2.1 earc Rx Functional Test option 59 HDMI 2.1 earc Tx Compliance Test option 60 HDMI 2.1 earc Rx Compliance Test option 61 DisplayPort Compliance Test Package 4 Errata 1. CEC Functionality on HDMI 18 Gbps RX/TX Analyzer receive port. Regarding the HDMI 2.0 RX/TX analyzer (this is the HDMI Gbps analyzer module that has 2 HDMI ports: Transmit and Receive): On this module, CEC is disabled by default on the HDMI Receive port. We expect this to be corrected in the next release. CEC functionality can be enabled temporarily (until the instrument is rebooted.) The following procedure will allow you to enable RX CEC functionality: 1. Launch the Windows External Manager (980 Manager) and connect to the From the Windows 980 Manager, select the Other GUI page. 3. Select the Command Console. 4. Select the Connect button. 5. Touch in the Command field to activate the touch screen keyboard. 6. Type the command discover and press Enter. 7. In the resulting list, locate the section that includes class: Quantum Data, Inc. HDMI 2.0 RX/TX. 8. Make note of the slot number indicated for this section. (For example, 3) 9. Again touch in the Command field to activate the touch screen keyboard. 10. Type the slot number from step 7 above and press Enter. (For example, 3 then press Enter.) 5

6 11. You should see a command prompt of #p2c-scope> 12. Touch in the Command field to activate the touch screen keyboard. 13. Type the command wb and then press Enter. (After the letters wb, the other visible characters are digits. Be sure to type the 3 spaces where shown.) 14. Verify that wb is echoed in the console window. 15. You may Disconnect and close the Command Console. 2. Difficulty connecting via Ethernet. Under some conditions, the 980B and 980R Advanced Test Platforms may exhibit difficulty in establishing an Ethernet connection. In this case, if a connection cannot be established after following the Quick Start Guide and common procedures for establishing a network connection, please follow this procedure: 1. Press the front button of the 980 ATP and select Shutdown. 2. After shutdown is complete, turn off the physical power switch beside the mains power cord inlet. 3. While the power switch is OFF, press the front button and hold for a few seconds. Repeat this a few times to assure that all motherboard and power supply capacitors are drained. 4. Make sure the Ethernet connector is connected to your network or PC before powering on the 980 ATP. On Gigabyte motherboards with 2 Ethernet connectors, use the bottom Ethernet connector on 980B, or on the 980R, the Ethernet connecter nearest the mains power inlet. 5. Power on the 980 ATP and allow it to fully boot. 6. Use the normal procedure to establish Ethernet TCP/IP connection with the External 980 Manager software. Support For support on the Quantum Data 980 or other Teledyne LeCroy PSG products, please send an to psgsupport@teledynelecroy.com Please include your full contact information and a detailed description of the problem, including product model number, serial number, firmware version, software version, etc. 6