Zynq System Architecture Design Lab Workbook Beta

Transcription

1 Zynq System Architecture Design Lab Workbook Beta

2 Zynq System Architecture Design Lab Workbook Beta Xilinx is disclosing this Document and Intellectual Property (hereinafter the Design ) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED AS IS" WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems ( High-Risk Applications ). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners.

3 Table of Contents Lab 1: Building a Zynq Extensible Processing Platform... 3 Lab 2: Integrating Fabric on the Zynq Extensible Processing Platform i

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5 Lab Workbook Building a Zynq Extensible Processing Platform Lab 1: Building a Zynq Extensible Processing Platform Cortex-A9 Processor and Zynq ZC702 Board Introduction This lab guides you through the process of using the PlanAhead software and Xilinx Platform Studio (XPS) to create a simple Zynq extensible processing platform. This process will require you to create an MHS file, top-level HDL, and ELFs. Objectives After completing this lab, you will be able to: Create an XPS processor system project using the PlanAhead software Design an embedded processor system in XPS using the Processor Configuration Wizard (PCW) Generate a top-level HDL in the PlanAhead software Export and launch the SDK tool from the PlanAhead software Add an SDK-generated software application as a software project to the SDK workspace Configure the processing system and download the software application from the SDK tool environment Procedure The purpose of this lab is to allow you to implement a processing system using an XPS-embedded system project. The XPS project will be the sole component in a PlanAhead software project. The processor system will be the top-level design structure of an ISE tool project. In this lab, you will use the Processor Configuration Wizard (PCW) in XPS to create a processor system consisting of the following processor IP: Cortex-A9 processor Zynq ZC702 board-supported I/O peripherals I 2 C 0 CAN 0 UART 1 SD 0 USB 0 Enet 0 Quad SPI (flash memory interfaces) This lab is separated into steps that consist of general overview statements that provide information on the detailed instructions that follow. Follow these detailed instructions to progress through the lab. This lab comprises of five primary steps: You will create a project in the PlanAhead software and configure the system using the Processor Configuration Wizard in XPS; analyze the created project; generate the top-level HDL in the PlanAhead software; launch the SDK tool from XPS, export to a new workspace, and add a new software project to the workspace; and, finally, generate the ELFs and download the software application to the evaluation board. 3

6 Building a Zynq Extensible Processing Platform Lab Workbook Note: If you are unable to complete the lab at this time, you can download the original lab files for this lab from These are the original lab files and do not contain any work that you may have previously completed. General Flow for this Lab Creating the Project Using Processor Configuring Wizard Step Begin the lab by opening a new PlanAhead software project from the ISE tool Select Start > All Programs > Xilinx ISE Design Suite > PlanAhead > PlanAhead to launch the PlanAhead software Click Create New Project and click Next. Figure 1-1: Creating a Project This will launch the New Project Wizard. 4

7 Lab Workbook Building a Zynq Extensible Processing Platform In the Project name field, enter PS_ZC702. In the Project location field, browse to the C:\training\sys_arch\labs\lab1 directory. Figure 1-2: Assigning the Project Name and Location Click Next to select the default options until you reach the Add Constraints dialog box. Select UCF and click Next In the Default Part dialog box, Select the board and project options listed below and click Next. Property Name Value Family Package Zynq-7000 CLG484 Speed Grade

8 Building a Zynq Extensible Processing Platform Lab Workbook Figure 1-3: Selecting the Evaluation Board Examine the project summary and then click Finish. Figure 1-4: Finishing the New Project Wizard The PlanAhead GUI will be launched Add a new embedded source file. This will automatically launch the XPS tool. Then you will use Processor Configuration Wizard (PCW) to create the embedded processor system In the Flow Navigator, click Add Sources ( ). The Add Sources wizard will be launched. 6

9 Lab Workbook Building a Zynq Extensible Processing Platform Select Add or Create Embedded Sources from the list of source types and click Next. Figure 1-5: Adding a New Processor Project Source Click Create File. 7

10 Building a Zynq Extensible Processing Platform Lab Workbook In the Module name field, enter system. Click OK. Figure 1-6: Creating a New Embedded Processor Project Source Click Finish. Xilinx Platform Studio (XPS) will be launched with a blank project Click Yes to add a Processing System7 instance to the system. Figure 1-7: Adding a Processing System Instance In the System Assembly View, double-click the processing_system7_0 IP instance Click Yes when prompted to switch to the ZYNQ tab Take a moment to view the architecture of the processing system (PS). 8

11 Lab Workbook Building a Zynq Extensible Processing Platform The green blocks in this diagram are configurable blocks Click any these blocks and you will see the configurable parameters of that block. Figure 1-8: Processor System Architecture 9

12 Building a Zynq Extensible Processing Platform Lab Workbook Click Import Zynq Configurations. Figure 1-9: Importing Zynq EPP Configurations Click OK to select the configuration template. Figure 1-10: Selecting a Configuration Template Click Yes to update the MHS file. This will configure the peripherals that are supported by the chosen board (ZC702). 10

13 Lab Workbook Building a Zynq Extensible Processing Platform The IOPs that are configured are displayed in different colors. Figure 1-11: IOPs Configured (Supported by the ZC702 Board) 11

14 Building a Zynq Extensible Processing Platform Lab Workbook Click the I/O Peripherals block to open the ZYNQ PS MIO Configuration dialog box. Select Show I/O Standard Options. Observe the enabled I/O peripherals (IOP) and the IO connections. Figure 1-12: Zynq PS MIO Configurations (Supported by the ZC702 Board) 12

15 Lab Workbook Building a Zynq Extensible Processing Platform De-select all the peripherals except UART 1, which is the only peripheral that will be used in this lab. Click Close. Figure 1-13: Selecting the UART 1 Peripheral To view how the tool has configured the memory, click the Memory Interfaces block in the ZYNQ tab. Select Advanced Configuration. Figure 1-14: DDR3 Memory Configuration 13

16 Building a Zynq Extensible Processing Platform Lab Workbook Note that because you selected Import Zynq Configuration in an earlier step, DDR3 memory (from the ZC702 board configuration) is selected Click OK. Question 1 Why is MIO selected for connecting these peripherals instead of EMIO? Analyzing the Created Project Step Examine the hardware design in the Graphical Design view. Under the Project tab in the Platform window (left side of display), study the created project files. Refer to the System Assembly View tab and the Ports tab to answer the questions in this step Select the Graphical Design View tab and browse the various components that are used in the design, using the mouse gestures to zoom in for closer examination. Hint: Click drag up and right to zoom out; click drag down and left to zoom in. Also try click drag down right to zoom an area and click drag left up to zoom to fit. o o The block diagram provides a graphical schematic of processing_system7_0. By default, you will initially see the PS processor with its IOP, clock, and resets. 14

17 Lab Workbook Building a Zynq Extensible Processing Platform Figure 1-15: Graphical Diagram View of the Generated Project Return to the System Assembly View and select the Ports tab and observe the expanded view similar to the figure below. o o o Notice that in the Ports view lists that none of the signals are connected except PS_REQUIRED_EXTERNAL_IO and MEMORY_0. These are typically signals that are specific to a peripheral. The formal port name of the peripheral is in the Name column; the actual net name is in the Net column. The direction column indicates the signal direction relative to the component (peripheral or processor). 15

18 Building a Zynq Extensible Processing Platform Lab Workbook Question 2 Figure 1-16: Ports Tab Why are some nets showing No Connection? Question 3 Examine the net names in the External Ports category at the top of the view. What do these signals represent? 16

19 Lab Workbook Building a Zynq Extensible Processing Platform Creating a Top-Level Wrapper Step 3 The embedded processor system is now a component in the PlanAhead software design In this step, you will create a top-level wrapper Select File > Exit to exit XPS. In the PlanAhead software project, observe that system.xmp has been added In the Sources tab, click Libraries to view the files under the Embedded Design Sources folder. Figure 1-17: Libraries Tab The added processor system in the project has UCF, MHS, and XDC files included. 17

20 Building a Zynq Extensible Processing Platform Lab Workbook Right-click the system component and select Create Top HDL. Figure 1-18: Creating the Top-Level Wrapper Expand the newly created system_stub component. You can double-click system_stub to examine the HDL code. This is where you could add additional components to the programmable logic design Close system_stub after you have finished examining it. 18

21 Lab Workbook Building a Zynq Extensible Processing Platform 3-2. Export the processor and launch SDK In the Hierarchy tab, select and double-click the system_i - system (system.xmp) component. This will launch XPS In XPS, select Project > Export Hardware Design to SDK. Deselect Include bitstream and BMM file. Figure 1-19: Export Processor Hardware and Launch SDK The actual exporting of the embedded processor hardware is transparent to the user. The SDK tool will launch. SDK creates a workspace environment consisting of project files, tool settings, and your software application. Once set, you cannot change the location of this workspace. If it is necessary to move a software application to another location or computer, use the Import and Export features built into SDK. A good location for the software workspace is the root directory of your PA/XPS tool project. While not a requirement, it is a good idea to keep the SDK-related files together Click Export & Launch SDK. 19

22 Building a Zynq Extensible Processing Platform Lab Workbook Browse to and select the C:\training\sys_arch\labs\lab1\PS_ZC702\PS_ZC702.srcs\sources_1\edk\system\SDK directory to specify a new SDK workspace. Figure 1-20: Setting up the Workspace Environment Path This directory was created when the Export Hardware Design command was performed Click OK. The SDK tool will be launched. 20

23 Lab Workbook Building a Zynq Extensible Processing Platform Close the Welcome screen. Figure 1-21: SDK Main Window 21

24 Building a Zynq Extensible Processing Platform Lab Workbook Adding the Software Application Step 4 Upon automatic launch when exporting embedded hardware, SDK creates a hardware platform project in the new workspace that you specified in the last step. On this platform you will build a First Stage Bootloader (FSBL) project, Board Support Package (BSP), and a software application. All of these projects will be members of the SDK workspace. In this step, you will create a software project by using one of the available projects ("hello world" program) that SDK supports. When creating a simple software application project, SDK can auto-create the BSP project. Also, SDK will automatically build the software application project and produce an Executable and Load Format (ELF) file You are now ready to add a Zynq device FSBL and a software application project. Although SDK supports multiple software projects, you will only be adding one. There are different types of software application projects, with the simplest being a Xilinx C project. In this type of project, a software designer will typically write code beginning with the main{} C function. You will add one of the readily available software applications as a Xilinx C project to SDK In SDK, select File > New > Xilinx C Project. Figure 1-22: Creating a C Application Project 22

25 Lab Workbook Building a Zynq Extensible Processing Platform Select Zynq FSBL from the Select Project Template area. Read the description and click Finish. Figure 1-23: Selecting the Zynq FSBL Application Select File > New > Xilinx C Project. 23

26 Building a Zynq Extensible Processing Platform Lab Workbook Select the Hello World project template to create a simple Hello World project. Keep the default project name of hello_world_0. Figure 1-24: Selecting the Hello World Project 24

27 Lab Workbook Building a Zynq Extensible Processing Platform Click Next to create a new board support package project. Keep the default project name. Figure 1-25: Creating the Board Support Package Click Finish. Follow the status info at the bottom right of SDK window to identify when the build completes. 25

28 Building a Zynq Extensible Processing Platform Lab Workbook The hello_world_0 application contains all the source files needed to build the object executable.elf file. The project will automatically build without errors. A successful build is indicated in the Console tab when the sizes of all of the program segments are displayed before the build complete message. Figure 1-26: Successful Software Application Build 26

29 Lab Workbook Building a Zynq Extensible Processing Platform The Project Explorer tab shows a tree structure for the software application under the hardware system. Although it may appear as if there are four software applications, there are only two: hello_world_0 and zynq_fsbl_0. The hello_world_bsp_0 project is the software platform and the system_hw_platform project is the hardware platform. Figure 1-27: Project Explorer Tab Double-click the helloworld.c application file to open it. Go through the program. Note the print statement that should be printed after the application is downloaded and executed. Besides opening source files, the software developer can use this view to open other resource files and set tool options for software applications and software platforms. 27

30 Building a Zynq Extensible Processing Platform Lab Workbook Downloading the Design Step 5 In this final step, you will use the ELF files, download the design into hardware, and operate the system Connect the ZC702 board to your machine. Open a terminal in SDK to view the output of the software application. You may need to change the assigned COM port based on your computer's configuration Connect the ZC702 board to your machine as shown below. Figure 1-28: ZC702 Development Board 28

31 Lab Workbook Building a Zynq Extensible Processing Platform Make sure that the USB cable is used to connect the USB UART port (J17) in the board to the machine and the Platform Cable USB connects the platform cable pins (J2) in the board to the machine Ensure that the jumper settings on the board (J20-J22, J25-J28) are as shown in the figure above Power up the ZC702 board Determine if a Terminal window is already open. A terminal tab would appear next to the Problems, Tasks, Console, and Properties tabs under the Edit window. Figure 1-29: Terminal Tab and Connect Icon If you do not see a Terminal tab, select Window > Show View > Terminal. Figure 1-30: Opening a Terminal Window Click the Connect icon to open the Terminal Settings dialog box. 29

32 Building a Zynq Extensible Processing Platform Lab Workbook Configure the settings as shown in the following figure. Figure 1-31: Terminal Settings Note: The COM port setting is specific to the computer being used and may need to be different than shown Click OK Select the Xilinx Tools > XMD Console to start the XMD debugger to download and run the program. In a shell, type the following commands in sequence: connect arm hw dow SDK/zynq_fsbl_0/Debug/zynq_fsbl_0.elf // download the bootloader file con // continue or start execution stop dow SDK/hello_world_0/Debug/hello_world_0.elf // downloads the application file con // run the hello world program // you should see "Hello World" displayed in the terminal stop 30

33 Lab Workbook Building a Zynq Extensible Processing Platform disconnect 64 //where 64 is the id of "arm" target Figure 1-32: XMD Console (1) 31

34 Building a Zynq Extensible Processing Platform Lab Workbook Figure 1-33: XMD Console (2) Close the XMD console. Disconnect the terminal Close SDK, XPS, and the PlanAhead software. Question 4 Where does the printf() routine output to? How would the output device be configured? Conclusion The Processor Configuration Wizard (PCW) can be used in XPS to create a project. Several files, including an MHS file representing the processor system, are created. The System Assembly View, representing the hardware system, provides hardware system parameter information. After the system has been defined, the netlist of the processor system can be created. The Xilinx Software Development Kit (SDK) enables you to create a software workspace environment that includes a bootloader for each processor in the hardware design and a software application project. In this lab, there was only a single processor in the design so only one software platform was needed. In addition, a single software project was added to the design. This was a simple lab to show you how the Zynq extensible processing platform can be built using PlanAhead, XPS, and SDK tools. Software development and the SDK tools are covered in detail in the Embedded Systems Software Design course. 32

35 Lab Workbook Building a Zynq Extensible Processing Platform Answers 1. Why is MIO selected for connecting these peripherals instead of EMIO? MIO is selected because in this lab connecting the I/O peripherals directly to the processor I/O pins is desired. EMIO is used to connect the peripherals to the programmable logic portion of the design. 2. Why are some nets showing No Connection? The Ports view illustrates all signal connections to a component that are part of a processor system. In some instances, not all signals are used for example, the interrupt line for IRQ_P2F_UART_1. In such cases, ports will default to the No Connection state. 3. Examine the net names in the External Ports category at the top of the view. What do these signals represent? The external ports represent those signals on the top level of the processor system component. These are the signals that interface the processor system to the rest of the world. 4. Where does the printf() routine output to? How would the output device be configured? The printf() function prints to STDOUT. This information would be found in the OS and Libraries Document Collection reference document under the software section (select C:\Xilinx\14.1\ISE_DS\EDK\sw\lib\bsp\standalone_v3_03_a\doc\standalone_v3_03_a.pdf) Most of the Xilinx software services follow normal C language practices. The output device that STDOUT talks to was configured when the Board Support Package (BSP) was built as the default device. In this lab, STDOUT was assigned to UART_

36 Building a Zynq Extensible Processing Platform Lab Workbook MHS File PARAMETER VERSION = PORT processing_system7_0_mio = processing_system7_0_mio, DIR = IO, VEC = [53:0] PORT processing_system7_0_ps_srstb = processing_system7_0_ps_srstb, DIR = IO PORT processing_system7_0_ps_clk = processing_system7_0_ps_clk, DIR = IO, SIGIS = CLK PORT processing_system7_0_ps_porb = processing_system7_0_ps_porb, DIR = IO PORT processing_system7_0_ddr_clk = processing_system7_0_ddr_clk, DIR = IO, SIGIS = CLK PORT processing_system7_0_ddr_clk_n = processing_system7_0_ddr_clk_n, DIR = IO, SIGIS = CLK PORT processing_system7_0_ddr_cke = processing_system7_0_ddr_cke, DIR = IO PORT processing_system7_0_ddr_cs_n = processing_system7_0_ddr_cs_n, DIR = IO PORT processing_system7_0_ddr_ras_n = processing_system7_0_ddr_ras_n, DIR = IO PORT processing_system7_0_ddr_cas_n = processing_system7_0_ddr_cas_n, DIR = IO PORT processing_system7_0_ddr_web_pin = processing_system7_0_ddr_web, DIR = O PORT processing_system7_0_ddr_bankaddr = processing_system7_0_ddr_bankaddr, DIR = IO, VEC = [2:0] PORT processing_system7_0_ddr_addr = processing_system7_0_ddr_addr, DIR = IO, VEC = [14:0] PORT processing_system7_0_ddr_odt = processing_system7_0_ddr_odt, DIR = IO PORT processing_system7_0_ddr_drstb = processing_system7_0_ddr_drstb, DIR = IO, SIGIS = RST PORT processing_system7_0_ddr_dq = processing_system7_0_ddr_dq, DIR = IO, VEC = [31:0] PORT processing_system7_0_ddr_dm = processing_system7_0_ddr_dm, DIR = IO, VEC = [3:0] PORT processing_system7_0_ddr_dqs = processing_system7_0_ddr_dqs, DIR = IO, VEC = [3:0] PORT processing_system7_0_ddr_dqs_n = processing_system7_0_ddr_dqs_n, DIR = IO, VEC = [3:0] PORT processing_system7_0_ddr_vrn = processing_system7_0_ddr_vrn, DIR = IO PORT processing_system7_0_ddr_vrp = processing_system7_0_ddr_vrp, DIR = IO BEGIN processing_system7 PARAMETER INSTANCE = processing_system7_0 PARAMETER HW_VER = 3.00.a PARAMETER C_DDR_RAM_HIGHADDR = 0x0FFFFFFF PARAMETER C_EN_EMIO_CAN0 = 0 PARAMETER C_EN_EMIO_CAN1 = 0 PARAMETER C_EN_EMIO_ENET0 = 0 PARAMETER C_EN_EMIO_ENET1 = 0 PARAMETER C_EN_EMIO_I2C0 = 0 PARAMETER C_EN_EMIO_I2C1 =

37 Lab Workbook Building a Zynq Extensible Processing Platform PARAMETER C_EN_EMIO_PJTAG = 0 PARAMETER C_EN_EMIO_SDIO0 = 0 PARAMETER C_EN_EMIO_SDIO1 = 0 PARAMETER C_EN_EMIO_SPI0 = 0 PARAMETER C_EN_EMIO_SPI1 = 0 PARAMETER C_EN_EMIO_SRAM_INT = 0 PARAMETER C_EN_EMIO_TRACE = 0 PARAMETER C_EN_EMIO_TTC0 = 1 PARAMETER C_EN_EMIO_TTC1 = 0 PARAMETER C_EN_EMIO_UART0 = 0 PARAMETER C_EN_EMIO_UART1 = 0 PARAMETER C_EN_EMIO_MODEM_UART0 = 0 PARAMETER C_EN_EMIO_MODEM_UART1 = 0 PARAMETER C_EN_EMIO_USB0 = 0 PARAMETER C_EN_EMIO_USB1 = 0 PARAMETER C_EN_EMIO_WDT = 1 PARAMETER C_EN_QSPI = 1 PARAMETER C_EN_SMC = 0 PARAMETER C_EN_CAN0 = 1 PARAMETER C_EN_CAN1 = 0 PARAMETER C_EN_ENET0 = 1 PARAMETER C_EN_ENET1 = 0 PARAMETER C_EN_I2C0 = 1 PARAMETER C_EN_I2C1 = 0 PARAMETER C_EN_PJTAG = 0 PARAMETER C_EN_SDIO0 = 1 PARAMETER C_EN_SDIO1 = 0 PARAMETER C_EN_SPI0 = 0 PARAMETER C_EN_SPI1 = 0 PARAMETER C_EN_TRACE = 0 PARAMETER C_EN_TTC0 = 1 PARAMETER C_EN_TTC1 = 0 PARAMETER C_EN_UART0 = 0 PARAMETER C_EN_UART1 = 1 PARAMETER C_EN_MODEM_UART0 = 0 PARAMETER C_EN_MODEM_UART1 = 0 PARAMETER C_EN_USB0 = 1 PARAMETER C_EN_USB1 =

38 Building a Zynq Extensible Processing Platform Lab Workbook PARAMETER C_EN_WDT = 1 PARAMETER C_EN_DDR = 1 PARAMETER C_FCLK_CLK0_FREQ = PARAMETER C_FCLK_CLK1_FREQ = PARAMETER C_FCLK_CLK2_FREQ = PARAMETER C_FCLK_CLK3_FREQ = PORT MIO = processing_system7_0_mio PORT PS_SRSTB = processing_system7_0_ps_srstb PORT PS_CLK = processing_system7_0_ps_clk PORT PS_PORB = processing_system7_0_ps_porb PORT DDR_Clk = processing_system7_0_ddr_clk PORT DDR_Clk_n = processing_system7_0_ddr_clk_n PORT DDR_CKE = processing_system7_0_ddr_cke PORT DDR_CS_n = processing_system7_0_ddr_cs_n PORT DDR_RAS_n = processing_system7_0_ddr_ras_n PORT DDR_CAS_n = processing_system7_0_ddr_cas_n PORT DDR_WEB = processing_system7_0_ddr_web PORT DDR_BankAddr = processing_system7_0_ddr_bankaddr PORT DDR_Addr = processing_system7_0_ddr_addr PORT DDR_ODT = processing_system7_0_ddr_odt PORT DDR_DRSTB = processing_system7_0_ddr_drstb PORT DDR_DQ = processing_system7_0_ddr_dq PORT DDR_DM = processing_system7_0_ddr_dm PORT DDR_DQS = processing_system7_0_ddr_dqs PORT DDR_DQS_n = processing_system7_0_ddr_dqs_n PORT DDR_VRN = processing_system7_0_ddr_vrn PORT DDR_VRP = processing_system7_0_ddr_vrp END 36

39 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform Lab 2: Integrating Fabric on the Zynq Extensible Processing Platform Cortex-A9 Processor and Zynq ZC702 Board Introduction This lab guides you through the process of adding additional IP to an existing processor system by using Xilinx Platform Studio (XPS). You will learn two methods of adding additional IP: using the IP Catalog tab and modifying an MHS file with a text editor. At the end of the lab, you will add the software object to the project and download the design to hardware by using XMD. Objectives After completing this lab, you will be able to: Add additional IP to a hardware design in XPS using the IP catalog and the System Assembly View Generate a netlist and bit file Create a blank software project in SDK and add a source file to it Generate an ELF software object file and download to hardware utilizing XMD Procedure The purpose of this lab is to extend the hardware design from the "Building a Zynq Extensible Processing Platform" lab, which included the Cortex -A9 processor and the following IP peripherals (IOPs): UART 1 Quad SPI (FLASH Memory Interfaces) In this lab, you will extend the modified hardware design by using both the System Assembly View (GUI) features of XPS to add the following IP to the existing processor system: GPIO for setting the LEDs output (via the System Assembly view [SAV]) You will also analyze the system.mhs file to identify the various sections of the hardware specifications of the embedded processor system. The starting point of this lab is a modified version of the ""Building a Zynq Extensible Processing Platform" lab. It includes a clock generator and reset module. These changes are done to allow you to add an IP to the embedded system without doing additional work. This lab is separated into steps that consist of general overview statements that provide information on the detailed instructions that follow. Follow these detailed instructions to progress through the lab. This lab comprises four primary steps: You will open the project; extend the hardware system designed in the ""Building a Zynq Extensible Processing Platform" lab; create a software application in SDK; and, finally, create the software object, generate the ELF files, and download and test the design in hardware. Note: If you are unable to complete the lab at this time, you can download the original lab files for this lab from These are the original lab files and do not contain any work that you may have previously completed. 37

40 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook General Flow for this Lab Opening the Project Step A modified working version of the ""Building a Zynq Extensible Processing Platform" lab design is provided as a starting point Select Start > All Programs > Xilinx ISE Design Suite > PlanAhead> PlanAhead to launch the PlanAhead software Click Open Project. Browse to the C:\training\sys_arch\labs\lab2 directory, select lab2.ppr, and click OK In Hierarchy window, double-click system.xmp to launch the project in XPS. Extending the Hardware System Step 2 XPS provides two methods for adding peripherals to an existing project. You will use only one method, the System Assembly View (SAV), to add and connect the GPIO peripheral for the LEDs. There is also the second method (manually editing the MHS file) The XPS System Assembly View (SAV) is a graphical representation of the text-based MHS file Select the Bus Interfaces tab to view the existing IPs in the design. 38

41 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform Select the IP Catalog tab in the left window and expand General Purpose IO to view the available cores under the corresponding entries. Figure 2-1: System Assembly View of the IP Catalog Double-click the AXI General Purpose IO core (version 1.01.b) in the IP Catalog and click Yes to add this IP to the design. The XPS Core Config dialog box will automatically appear. While you can configure the core now, you will perform this configuration later. This will demonstrate how you can later change a peripheral configuration Click Cancel In the Instantiate and Connect IP dialog box, select Select processor instance to connect to and click OK. Figure 2-2: Instantiate and Connect IP Dialog Box You made the default selection and the tools will automatically make the AXI connection. However, you could also have chosen to make the connections and settings manually. The new core will appear as a component in the System Assembly View tab. There will be several errors in the console because the core was not allowed to auto-configure. 39

42 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook Change the instance name of the peripheral to LEDs_8bit by clicking once in the Name column of the axi_gpio_0 component, typing the new name, and then clicking any other screen object. At this point, the peripherals should look like those in the figure below, although not necessarily in the same order. Figure 2-3: Bus Interfaces Tab after Adding and Renaming the axi_gpio_0 Peripheral Notice that the wire coming from the LEDs_8bit peripheral is attached to an AXI circle. This indicates that this component is connected to the AXI. As indicated in the previous step, this connection been automatically made by the tools when the GPIO was first added. When performed manually, this connection can be made by one of two ways: o o The quick connection method is executed by clicking the hollow shape. The more flexible method requires expanding the LEDs_8bit component and clicking in the Bus Name column next to the S_AXI port of the component and selecting the desired AXI interconnect. In this design, there is only a single AXI interconnect. Figure 2-4: Selecting axi_interconnect_ Select the Addresses tab. Expand processing_systems7_0 s Address Map to view the address map for this processor. You can manually assign the base address and size of your peripherals or have XPS generate the addresses for you. Notice that all of the peripherals in the tree have been assigned addresses already. However, also notice that LEDs_8bit is available in this list. It has been assigned an address. 40

43 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform LEDs_8bit is a member of this list. Figure 2-5: Adding the LEDs_8bit to the Address Map Verify that the memory size of the peripheral is 64K. Question 1 The 8-bit LED output does not require 64K of address space. Why do you think then that you are setting the space to so large a size? 2-2. In this step, you will create an external port to the processor system that can later be attached to the eight physical LEDs. The configuration of the GPIO that was deferred earlier will be performed. All of these items will be performed in the Ports tab of the SAV Select the Ports tab in the System Assembly View and expand the LEDs_8bit instance and the two sub-ports. Figure 2-6: Ports of Added Instances Right-click LEDs_8bit and select View PDF Datasheet. This document is the hardware description of the AXI_GPIO component. Everything you may want to know about this component will be contained in this document. 41

44 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook Click in the Net column of the GPIO_IO_O port of the LEDs_8bit instance and select New Connection as the net name from the Net column drop-down list. Figure 2-7: GPIO_out Port Connection Added to Instance XPS will automatically choose a net name (LEDs_8bit_GPIO_IO_O) based on the port name and instance name of the peripheral Change the net name axi_gpio_0_gpio_io to No Connection. Question 2 How do you know which GPIO port to use? Click in the Net column of the S_AXI_ACLK port of the LEDs_8bit instance and select processing_system7_0_fclk_clk0 as the net name from the Net column drop-down list. Figure 2-8: Selecting a Clock This is the lower speed of the processor clock that is commonly used for peripherals. 42

45 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform Right-click the LEDs_8bit instance and select Configure IP. Figure 2-9: Selecting Configure IP The same XPS Core Config dialog box that appeared when you originally added the component is launched. Note: You can also access the configuration dialog box for a peripheral instance by double-clicking anywhere in the instance listing. Notice that the peripheral can be configured for two channels. 43

46 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook Because you want to use only one channel, keep the Enable Channel 2 option de-selected. Figure 2-10: Configurable Parameters of the GPIO Instance 44

47 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform Select Channel 1 to view Channel 1-related configurable parameters. Enter 8 in the GPIO Data Bus Width box to match the width of the eight LEDs on the the board. Figure 2-11: Setting Configurable Parameters Click OK Expand External Ports (at the top of the Ports tab). Note that the LED ports are not listed there yet Click in the Net column of the GPIO_IO_O port of the LEDs_8bit instance and select Make External from the Net column drop-down list. 45

48 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook For the LEDs_8bit_GPIO_IO_O_pin net, verify that the Direction column drop-down list is set as an output (O). Figure 2-12: Making a Port External Note: The port will connect externally on the ZYNQ EPP and now appears in the External Ports Connections field with [7:0] as the range. 46

49 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform 2-3. In this step, you will make reset and clock connections to an AXI interconnect and processing system Select the Ports tab in the System Assembly View and expand the processing_system7_0 instance and the (BUS_IF) M_AXI_GP0 sub-port. Figure 2-13: Expanding the processing_system7_0 Instance Expand processing_system7_0, and for M_AXI_GP0_ARESETN, click in the Net column and select New Connection from the Net column drop-down list. The net will be named processing_system7_0_m_axi_gp0_aresetn. 47

50 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook For M_AXI_GP0_ACLK, click in the Net column and select processing_system7_0_fclk_clk0 from the Net column drop-down list. Figure 2-14: Selecting the clock (M_AXI_GP0_ACLK) Expand axi_interconnect_1, and for INTERCONNECT_ACLK, click in the Net column and select processing_system7_0_fclk_clk0 from the Net column drop-down list Expand axi_interconnect_1, and for INTERCONNECT_ARESETN, click in the Net column and select processing_system7_0_m_axi_gp0_aresetn from the Net column drop-down list. Figure 2-15: Final View of the Ports Tab (1) 2-4. The netlist for the embedded system should now be generated via PlatGen. After generating the netlist, you will be finished and can export to SDK In XPS, select Project > Clean All Generated Files to clean the PlatGen output files. This will delete any intermediate files from any previous execution of PlatGen. It is often a fix of weird and/or unexpected PlatGen errors In XPS, select File > Exit to close the XPS. 48

51 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform In the PlanAhead software, right click the system component in the Sources tab and select Create Top HDL. Note: Step to are the recommended PlanAhead software steps. There are some issues with the current version of build. You can skip these steps and go to step In the Flow Navigator, click Run Synthesis to run PlatGen and generate the processor system. This will take about three to four minutes Click OK to run implementation Edit the user constraints file to add the I/O pin locations and properties of the newly added component pins. Then generate the bitstream from the PlanAhead software In the Libraries tab, double-click system.ucf. You can also open the system.ucf file from the C:\training\sys_arch\labs\lab2\lab2.srcs\sources_1\imports\lab3\data directory. The code is in the system_lab3.ucf file in the C:\training\sys_arch\support\lab2 directory. You can copy-and-paste from this file into the system.ucf file after line Save and close the system.ucf file. Note: Bit generation in the PlanAhead software shows and error and terminates bit generation. This issue will be resolved in a future build release. To continue the lab, you can use a working bitstream (generated form XPS standalone) located in the C:\training\sys_arch\labs\lab2 directory Click Generate Bitstream to generate the bit file of the system. This will take about three to four minutes. 49

52 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook 2-6. Export the processor and launch SDK In the PlanAhead software, select File> Export. Figure 2-16: Exporting and Launching SDK The actual exporting of the embedded processor hardware is transparent to the user. The SDK tool will launch Click OK. 50

53 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform Verify that the SDK tool launches. Close the Welcome screen. Figure 2-17: SDK Main Window 51

54 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook Creating the Software Project Step 3 Upon automatic launch when exporting embedded hardware, SDK creates a hardware platform project in the new workspace that you specified in the last step. On this platform you will build a First Stage Bootloader (FSBL) project, Board Support Package (BSP), and a software application. All of these projects will be members of the SDK workspace. In this step, you will create a software project by using one of the available projects that SDK supports. When creating a simple software application project, SDK can auto-create the BSP project. Of the projects in the workspace (hardware platform, BSP, and software application), two of them will be automatically created, leaving little work for you. SDK will automatically build the software application project and produce an Executable and Load Format (ELF) file You are now ready to add a software application project. Although SDK supports multiple software projects, you will only be adding one. There are different types of software application projects, with the simplest being a Xilinx C project. In this type of project, the software designer writes code from the standpoint of beginning in the main {} C function. You will add the ready available software application as a Xilinx C project to SDK on the hardware peripheral drivers it sees in the hardware platform In SDK, select File > New > Xilinx C Project. Figure 2-18: Creating a C Application Project 52

55 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform Select Zynq FSBL from the Select Project Template area. Figure 2-19: Selecting the Zynq FSBL Application Click Finish Select File > New > Xilinx C Project. 53

56 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook Select the Empty Application project template to create a blank C project. Name the project peripheral_test_0. Figure 2-20: Selecting the Empty Application Template Click Next to create a new board support package project. Name the BSP project as peripheral_test_bsp_0 with the default settings Click Finish. 54

57 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform Right-click the src folder under peripheral_test_0 and select Import and select General > File System. Figure 2-21: Importing Files into the Project Click Next. 55

58 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook Browse to the C:\training\sys_arch\support\lab2 directory and select the gpio_header.c, testperiph.c, and xgpio_tapp_example.c files to import into the peripheral_test_0/src folder. Figure 2-22: Importing Files to the Local File System Click Finish. The peripheral_test_0 application contains all the source files needed to build the object executable.elf file. The project will automatically build without errors. A successful build is indicated in the Console tab when the sizes of all of the program segments are displayed before the build complete message. Figure 2-23: Successful Software Application Build The Project Explorer tab shows a tree structure for the software application under the hardware system. Although it may appear as if there are three software applications, there are only two: 56

59 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform peripheral_test_0 and zynq_fsbl_0. The peripheral_test_bsp_0 project is the software platform and the lab3_hw_platform project is the hardware platform. Figure 2-24: Opening testperiph.c Double-click the testperiph.c application file to open it. Go through the program. Question 3 Besides opening source files, the software developer can use this view to open other resource files and set tool options for software applications and software platforms. What will the testperiph.c program do? 57

60 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook Downloading and Running the Design Step 4 In this final step, you will use the ELF files, download the design into hardware, and operate the system Connect the ZC702 board to your machine. Open a terminal in SDK to view the output of the software application Connect the ZC702 board to your machine as shown below. Figure 2-25: ZC702 Development Board 58

61 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform Make sure that the USB cable is used to connect the USB UART port (J17) in the board to the machine and the Platform Cable USB connects the platform cable pins (J2) in the board to the machine Ensure that the jumper settings on the board (J20 J22, J25 J28) are as shown in the figure above Power up the ZC702 board Determine if a Terminal window is already open. A terminal tab would appear next to the Problems, Tasks, Console, and Properties tabs under the Edit window. Figure 2-26: Terminal Tab and Connect Icon If you do not see a Terminal tab, select Window > Show View > Terminal. Figure 2-27: Opening a Terminal Window Click the Connect icon to open the Terminal Settings dialog box. 59

62 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook Configure the settings as shown in the following figure. Figure 2-28: Terminal Settings Note: The COM port setting is specific to the computer being used and may need to be different than shown Click OK Select Xilinx Tools > XMD Console to start the XMD debugger to download and run the program. In the shell, type the following commands in sequence: connect arm hw dow lab2.sdk/sdk/sdk_export/zynq_fsbl_0/debug/zynq_fsbl_0.elf // download the bootloader file con // continue or start execution stop fpga -f system.bit -debugdevice devicenr 2 // download the bit file dow lab2.sdk/sdk/sdk_export/peripheral_test_0/debug/peripheral_test_0.elf // download the application file con // Run the periphal_test_0 program 60

63 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform stop // See the LEDs on the board and the Terminal display message disconnect 64 //where 64 is the id of "arm" target Figure 2-29: XMD Console (1) 61

64 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook Figure 2-30: XMD Console (2) Figure 2-31: Viewing in Terminal after Running the Program Enter the data to the address 0x (mrw command) in the XMD console and see the changes in the LEDs after entering each command: mwr 0x xffffff00 mwr 0x xffffff

65 Lab Workbook Integrating Fabric on the Zynq Extensible Processing Platform mwr 0x xffffff0f Figure 2-32: Memory Write Command Close SDK and the PlanAhead software. Conclusion Xilinx Platform Studio (XPS) provides the System Assembly View for graphical editing of the MHS file. The Configure IP dialog box for a given peripheral also provides a graphical method for editing component parameters. Manually editing the MHS file is always available as an alternative method. While giving the design engineer precise and flexible control of how the processor system is built, it requires knowledge of the system components and syntax of the MHS language. 63

66 Integrating Fabric on the Zynq Extensible Processing Platform Lab Workbook Answers 1. The 8-bit LED output does not require 64K of address space. Why do you think then that you are setting the space to so large a size? The choice of 64K is driven by the programmable logic fabric. The actual address space required by the AXI_GPIO peripheral is 16 bytes, decoded as four locations. Twenty-eight bits would be required for a full decode. 64K represents the decoding of 16 bits, or two layers of logic. Decoding more of the address bits will cause more layers of logic to form and make it more difficult for the tools to meet timing. Thirty-two bit addressing space represents 4 GB of memory, or 65,536 64K blocks; so be generous when allocating address space. 2. How do you know which GPIO port to use? From the data sheet for the peripheral, it is not entirely obvious how the AXI_GPIO peripheral is built. Table 1 illustrates the AXI_GPIO I/O signals. On page 4 of the data sheet, near the end of the table are the user-side signals. The GPIO_IO signal represents an IOB bound 3-state buffer that is automatically added into the design on the top level. This 3-state output and the three signals necessary to drive the 3-state buffer are all included in the Ports view. The datasheet does not consider the three other signals as part of the list of formal AXI_GPIO signals in the table. Because you are only using inputs, the 3-state driver is not needed. The GPIO_IO_I signal is used instead, which is the input to the AXI_GPIO peripheral. When this signal is used, the 3-state buffer will not be inserted. 3. What will the testperiph.c program do? The testperiph.c program calls the GpioOutputExample() function. This function will shift the data to each of the LED bits with its while loop in the main function. The print statement in the main function will be seen in the SDK Terminal when you run the program. 64

67 Running Linux on the Zynq Extensible Processing Platform

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69 Table of Contents Lab 1: Running Linux on the Zynq Extensible Processing Platform i

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71 Lab Workbook Running Linux on the Zynq Extensible Processing Platform Lab 1: Running Linux on the Zynq Extensible Processing Platform Cortex-A9 Processor and Zynq EPP ZC702 Board Introduction In this lab, you will use the Xilinx Software Development Kit (SDK) to create and debug a simple Linux software application project. The source for a "hello world" application is provided. The ZC702 board will automatically boot Linux from a provided SD card with the Linux kernel installed as part of the boot image. Using SDK, you will create a new workspace, import a hardware platform, then build and debug a Linux application. Objectives After completing this lab, you will be able to: Create an SDK software application project Import an existing Zynq EPP hardware platform Create and build a software project Open and use the Remote System Explorer (RSE) tool environment Download, debug, and run an application on development hardware Explore Linux operations on the Zynq EPP Access processor logic (PL) hardware from Linux Procedure This lab is separated into steps that consist of general overview statements that provide information on the detailed instructions that follow. Follow these detailed instructions to progress through the lab. This lab comprises four primary steps: You will create an SDK software workspace; add a software application to the workspace; explore Linux operation on the ZC702; and, finally, access hardware (LEDs on the board) from Linux. Note: If you are unable to complete the lab at this time, you can download the original lab files for this lab from These are the original lab files and do not contain any work that you may have previously completed. General Flow for this Lab 3

72 Running Linux on the Zynq Extensible Processing Platform Lab Workbook Creating an SDK Software Workspace Step 1 The first step in this lab is to create an SDK software workspace. The working directory of the SDK workspace for this lab and all subsequent labs is C:\training\sys_arch\labs. You will create the SDK workspace and software platform for the hardware in this directory. Once SDK is launched and a workspace is set up in this directory, you will not be able to move these directories The ZC702 board must be connected, powered, and Linux booted before the Remote System Explorer (RSE) tool is started. It takes about a minute for Linux to boot, so these steps will be completed first On the ZC702 board, make sure the power, serial USB, Ethernet, and USB Platform download cables are properly connected Make sure an SD card with a Linux image is present Power on the board. Linux will be booted by the time it is needed A new SDK workspace will be created and a hardware platform project will be placed into it Select Start > All Programs > Xilinx ISE Design Suite 14.1 > EDK > Xilinx Software Development Kit to launch SDK. The Workspace Launcher opens. SDK creates a workspace environment consisting of project files, tool settings, and your software application. Once set, you cannot change the location of this workspace. If it is necessary to move a software application to another location or computer, use the Import and Export facilities built into SDK. A good location for the software workspace is the root directory of your ISE tool project In the Workspace Launcher, browse to and select C:\training\sys_arch\labs\linux101 as the workspace directory and click OK. You will have to create the final target directory. Figure 1-1: Setting up the Workspace Environment Path 4

73 Lab Workbook Running Linux on the Zynq Extensible Processing Platform SDK must associate with a hardware system that has been previously exported. It needs hardware configuration information so that an appropriate software platform or board support package can be built Close the Welcome screen if it appears in SDK Select File > New > Xilinx Hardware Platform Specification. Figure 1-2: Selecting Xilinx Hardware Platform Specification 5

74 Running Linux on the Zynq Extensible Processing Platform Lab Workbook Enter linux_101 in the Project name field. Browse to C:\training\sys_arch\labs\lab1\PS_ZC702\PS_ZC702.srcs\sources_1\edk\system\SDK\SDK_ Export\hw, select the system.xml hardware project, and click Open. Figure 1-3: Selecting the hw Directory Figure 1-4: Creating a New Hardware Project system.xml was also created when you exported the hardware design to SDK. Essentially this is an XML version of the XPS project (system.xmp) and netlist (system.mhs) files Click Finish to create the hardware project. 6

75 Lab Workbook Running Linux on the Zynq Extensible Processing Platform The Hardware Platform Specification (system.xml file) is displayed. Figure 1-5: Newly Created Hardware Project SDK supports multiple hardware platform projects in the same workspace. Note: When you scroll lower in the system.xml file, you can display information about the IP by clicking the link to the datasheet for the IP. 7

76 Running Linux on the Zynq Extensible Processing Platform Lab Workbook Adding a Software Application Step 2 In this step, you will generate the software platform for the hardware and an empty software project. Then you will import C source files into the project and SDK will automatically build and produce an Executable and Load Format (ELF) file A Linux software application project will be created. The steps are slightly different than that used for a Standalone project, so that a different GNU tool chain is specified for building the project. This process will change as the SDK tools evolve for Linux Select File > New > Project. Figure 1-6: Creating a New Xilinx Project In the Select a Wizard dialog box, expand the C/C++ folder and select C Project. Click Next. Figure 1-7: Selecting C Project 8

77 Lab Workbook Running Linux on the Zynq Extensible Processing Platform Select the Xilinx ARM Linux Executable project type. Enter Hello_Linux in the Project name field and click Finish. Figure 1-8: Naming the C Project and Selecting a Project Type 2-2. Import the simple "hello world" application that has been provided In the Project Explorer tab, right-click the Hello_Linux project and select Import. 9

78 Running Linux on the Zynq Extensible Processing Platform Lab Workbook In the Select dialog box, expand General, select File System, and click Next. Figure 1-9: Importing Files into the Project In the From directory field, browse to the C:\training\sys_arch\Support directory and click OK Select hello_linux_101.c for import. 10

79 Lab Workbook Running Linux on the Zynq Extensible Processing Platform Use the default Into folder directory path, which copies the files into the current project. Figure 1-10: Importing Existing Source Files into the Application Click Finish In the Project Explorer tab, right-click the Hello_Linux project and select Build Project. Figure 1-11: Selecting Build Project The application is automatically built. The Console window shows the results of the build. 11

80 Running Linux on the Zynq Extensible Processing Platform Lab Workbook Make sure that the application is built without errors. Figure 1-12: Application Build Console Window 2-3. Use the Remote System Explorer (RSE) tool to download and debug the software application on the Linux platform Select Window > Open Perspective > Other to open a new SDK perspective. Figure 1-13: Selecting Open Perspective 12

81 Lab Workbook Running Linux on the Zynq Extensible Processing Platform Select Remote System Explorer and click OK. Figure 1-14: Selecting Remote System Explorer The new RSE perspective opens. Figure 1-15: RSE Perspective 13

82 Running Linux on the Zynq Extensible Processing Platform Lab Workbook In the Remote Systems tab, right-click Local and select New > Connection. Figure 1-16: Selecting New Connection In the Select Remote System Type dialog box, select SSH Only and click Next. Figure 1-17: Creating a New SSH RSE Connection In the Remote SSH Only System Connection dialog box, enter in the Host name and Connection name fields. 14

83 Lab Workbook Running Linux on the Zynq Extensible Processing Platform The Parent profile field can stay at its default, which will be different from what is shown below. Figure 1-18: Entering the Host and Connection Names Click Finish. The new connection is now present in the Remote Systems tab Browse the directory structure of the connection. 15

84 Running Linux on the Zynq Extensible Processing Platform Lab Workbook This is the Linux file system in the DDR3 RAM of the ZC702 board. The Local connection is the directory structure of the host machine. You can even drag-and-drop files between the two connections or other windows directory panes. Figure 1-19: Remote Systems Tab 16

85 Lab Workbook Running Linux on the Zynq Extensible Processing Platform 2-4. Create a Debug configuration. Debug and Run configurations associate an ELF object file to a target for execution. In this case, the target is a hardware board accessed over a network TCP/IP connection In the Project Explorer tab, right-click the Hello_Linux project and select Debug as > Debug Configurations. Figure 1-20: Selecting Debug Configurations 17

86 Running Linux on the Zynq Extensible Processing Platform Lab Workbook In the Create, Manage, and Run configurations dialog box, double-click Remote ARM Linux Application. Figure 1-21: Creating a Remote Linux Debug Configuration 18

87 Lab Workbook Running Linux on the Zynq Extensible Processing Platform Select from the Connection drop-down list. Figure 1-22: Selecting the IP Address In the Remote Absolute File Path for C/C++ Application field, enter /tmp/hello_linux.elf. 19

88 Running Linux on the Zynq Extensible Processing Platform Lab Workbook This will place and rename the Hello_Linux.elf file into the \tmp directory of the target. In this case, the filename remains the same, except for the capital letters. Figure 1-23: Setting the Remote File Path for the Application Click Apply. Click Debug to open the Debug perspective and start the debug session. During the course of accessing the remote platform for the first time, you will be prompted for a user ID and password Enter root in the User ID and Password fields. Figure 1-24: Entering ID and Password 20

89 Lab Workbook Running Linux on the Zynq Extensible Processing Platform Click Yes to confirm opening the Debug perspective. Figure 1-25: Confirming a Perspective Switch Figure 1-26: Debug Perspective 2-5. Perform several housekeeping tasks that will enable the proper display of STDOUT in the RSE console. This console has different view modes that are not needed and hide the desired program execution terminal view. This is expected to change as the SDK RSE tools evolve. Single step through the lines of the application. 21

90 Running Linux on the Zynq Extensible Processing Platform Lab Workbook In the upper right of the Console tab, click the Verbose console mode icon to turn off verbose mode. Figure 1-27: Verbose Console Mode In the upper right of the Console tab, click arrow next to the Display Selected Console icon and select the hello_linux.elf item. This is the terminal output of the application. Figure 1-28: Display Selected Console In the top of the Debug tab, click the Step Over (F6) icon to single step through the program. Figure 1-29: Step Over 22

91 Lab Workbook Running Linux on the Zynq Extensible Processing Platform Watch the execution of the program in the hello_linux.c tab. Figure 1-30: Single Stepping Through the Program When finished, click the Terminate icon. Figure 1-31: Terminating the Program Exploring Linux on the ZC702 Step 3 In this step, you will load and execute the Linux application built in the previous step Open a terminal window in SDK to the ZC702 board Select the Terminal 1 tab and click the Settings icon. Figure 1-32: Accessing the Terminal Settings 23

92 Running Linux on the Zynq Extensible Processing Platform Lab Workbook Enter the settings as shown below and click OK. Figure 1-33: Terminal Settings Click in the Terminal 1 tab and press <Enter> to wake up the terminal Enter ls to see a directory listing. Enter cd tmp to change directory to the application program. Enter ls again to see the directory listing. Enter./hello_linux.elf to execute the program. Figure 1-34: Linux Console Feel free to enter other Linux commands Enter the following commands to view the contents of the SD card. 24

93 Lab Workbook Running Linux on the Zynq Extensible Processing Platform cd.. mount /dev/mmcblk0p1 mnt ls /mnt Figure 1-35: Viewing the Directory on the SD Card Leave SDK open before proceeding to the next step. 25

94 Running Linux on the Zynq Extensible Processing Platform Lab Workbook Accessing Hardware from Linux Step 4 Typically, a custom device driver is used to access custom hardware in the programmable logic. This requires a special build of the kernel to add the device driver. It is possible to access custom hardware in Linux without a device driver by using the generic devmem command in Linux. While not the most efficient mechanism, it bypasses the need to rebuild the kernel Use the ChipScope Pro tool to download a bit file into programmable logic. This will allow access to the on board LEDs Select Start > All Programs > Xilinx ISE Design Suite 14.1 > ChipScope Pro > Analyzer to launch the ChipScope Pro Analyzer. Figure 1-36: ChipScope Pro Analyzer Click the icon to initialize the USB Platform download cable and initialize the JTAG chain Click OK to accept the JTAG findings. Figure 1-37: Devices on the JTAG Chain 26

95 Lab Workbook Running Linux on the Zynq Extensible Processing Platform Notice that the one Zynq device has two chains Select Device > DEV:! MyDevice (XC7Z020) > Configure to load the BIT file. Figure 1-38: Selecting Configure Click Select New File, browse to C:\training\sys_arch\support, select system.bit, and click Open. Figure 1-39: Selecting the BIT File Click OK. The BIT file will be downloaded into the part Use Linux commands to access board hardware (LEDs) Return to the Terminal 1 tab in SDK and enter the following commands. Watch the row of LEDs next to the row of three pushbuttons on the ZC702 board. Do not make any typos as the system may hang and you will have to start over. 27

96 Running Linux on the Zynq Extensible Processing Platform Lab Workbook devmem // Indicates the format of the command devmem 0x400a000c 32 0x0 // Set GPIO to be output ports devmem 0x400a xaa // GPIO data register, LEDs will light devmem 0x400a x55 devmem 0x400a xbc Figure 1-40: Using DEVMEM to Access Board Hardware 28