ZC706 Built-In Self Test Flash Application April 2015

Transcription

1 ZC706 Built-In Self Test Flash Application April 2015 XTP242

2 Revision History Date Version Description 04/30/ Recompiled for /24/ Recompiled for /08/ Recompiled for /09/ Recompiled for /16/ Recompiled for AR58941 fixed. Added AR /18/ Recompiled for Added AR /18/ Updated with patch from AR58347 in place of AR /23/ Recompiled for Converted to IPI. Added AR /19/ Recompiled for Vivado AR55581 and AR55431 fixed. 04/03/ Recompiled for AR53306 fixed. AR53593 fixed. 12/18/ Recompiled for /23/ Initial version. Added AR Copyright 2015 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the Information ) is provided AS-IS with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for your use of this Information. Xilinx reserves the right to make changes, at any time, to the Information without notice and at its sole discretion. Xilinx assumes no obligation to correct any errors contained in the Information or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE INFORMATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

3 Note: This presentation applies to the ZC706 Overview Xilinx ZC706 Board Software Requirements ZC706 Setup ZC706 BIST (Built-In Self Test) Run the BIST Design Run the USB Design Run the LwIP Ethernet Design Compile ZC706 BIST Design Creating a BOOT Image Programming the ZC706 QSPI Run the USB Design from SDK Run the LwIP Ethernet Design References

4 ZC706 Board

5 Vivado Software Requirements Xilinx Vivado Design Suite , Design Edition + SDK Combined installer

6 ZC706 Setup Set the JTAG Select Switch, SW4, to 01 If using a Platform Cable USB (II) JTAG Cable, set SW4 to 10 Note: Presentation applies to the ZC706

7 ZC706 Setup Connect a USB Type-A to Micro-B cable to the USB JTAG (Digilent) connector on the ZC706 board Connect this cable to your PC

8 ZC706 Setup Connect a USB Type-A to Mini-B cable to the USB UART connector on the ZC706 board Connect this cable to your PC

9 ZC706 Setup Set SW11 DIP Switches to Power on the ZC706 board for UART Drivers Installation

10 ZC706 Setup Install USB UART Drivers Refer to UG1033 for details on installing the USB to UART Drivers

11 ZC706 Setup Reboot your PC if necessary Right-click on My Computer and select Properties Select the Hardware tab Click on Device Manager

12 ZC706 Setup Expand the Ports Hardware Right-click on Silicon Labs CP210x USB to UART Bridge and select Properties

13 ZC706 Setup Under Port Settings tab Click Advanced Set the COM Port to an open Com Port setting from COM1 to COM4

14 ZC706 Setup Refer to UG1036 regarding Tera Term installation Board Power must be on before starting Tera Term Start the Terminal Program Select your USB Com Port Set the baud to

15 ZC706 Setup Unzip the ZC706 BIST Design Files ( C) ZIP file Available through It is recommended to unzip these design files to C:\ for SDK compatibility

16 ZC706 Setup Set the SW11 DIP switches to boot from QSPI: The ZC706 QSPI comes preloaded with the BIST Application Cycle power to start the BIST Application

17 ZC706 BIST BIST can also be loaded from the command line To do this, open a Windows prompt and type: cd C:\zc706_bist\ready_for_download zc706_bist.bat

18 ZC706 BIST View initial BIST screen

19 ZC706 BIST UART Test Type 1 to start the PS UART Test After each test, press any key to return to the main menu

20 ZC706 BIST IIC Test Type 2 to begin PS IIC Tests Completes seven different IIC tests

21 ZC706 BIST Timer Test Type 3 to begin PS Timer Test

22 Note: SCU / GIC means Snoop Control Unit / Generic Interrupt Controller ZC706 BIST SCU / GIC Test Type 4 to begin SCU / GIC Test

23 ZC706 BIST SCU / GIC Test Type 5 to begin Device Configuration Interface Test

24 ZC706 BIST Memory Test Type 6 to begin PS DDR3 Memory Test

25 ZC706 BIST Interrupt Test Type 7 to begin PS Interrupt Tests

26 ZC706 BIST Watchdog Timer Test Type 8 to begin PS Watchdog Timer Test

27 ZC706 BIST LED Test Type 9 to begin PL LEDs Test View the four PL GPIO LEDs blinking

28 ZC706 BIST GPIO Switch Test Set 4-position PL GPIO DIP Switch (SW12) Type A to begin PL GPIO DIP Switch Test Reads switch settings

29 ZC706 BIST GPIO Switch Test Type B to begin PL Push Button Test Reads pushbutton settings

30 Run the USB Design

31 Run the USB Design Set SW11 DIP Switches to Cycle board power to clear the BIST program

32 Caution This procedure will format a disk drive Make sure you are formatting the ZC706 USB Flash and not your PC s hard drive Drive letters mentioned in this procedure will vary from PC to PC - Verify the drive letter before formatting Xilinx cannot take responsibility for lost data or damaged hard drives

33 Run the USB Design View your current set of disk drives

34 Run the USB Design Connect a USB Type-A to Micro-B cable to the USB ULPI connector on the ZC706 board Connect this cable to your PC Note: Presentation applies to the ZC706

35 Run the USB Design Download the USB ELF In a Windows prompt type: cd C:\zc706_bist\ready_for_download zc706_usb.bat

36 Run the USB Design An extra removable drive will appear In this case, G:

37 Run the USB Design Open the G: drive A Disk is not formatted message will appear If this is the correct drive, click Yes; if not, click No

38 Run the USB Design A format dialog for drive G: will appear The size should be 1.00 MB If this is the correct, click Start Close this dialog when done

39 Run the USB Design At this point, you can copy small files to G: and verify the operation of this drive Disconnect USB cable before running LwIP

40 Run the LwIP Ethernet Design

41 Note: The LwIP SDK project has AR60358 applied Run the LwIP Ethernet Design From the Windows Control Panel, open Network Connections Right-click on the Gigabit Ethernet Adapter and select Properties

42 Run the LwIP Ethernet Design Click Configure Set the Media Type to Auto for 1 Gbps then click OK

43 Run the LwIP Ethernet Design Reopen the properties after the last step Set your host (PC) to this IP Address:

44 Run the LwIP Ethernet Design Set SW11 DIP Switches to Cycle board power to clear the USB program

45 Run the LwIP Ethernet Design Connect an Ethernet cable to the Ethernet connector on the ZC706 board Connect this cable to your PC

46 Run the LwIP Ethernet Design Download the LwIP ELF In a Windows prompt type: cd C:\zc706_bist\ready_for_download zc706_lwip.bat

47 Run the LwIP Ethernet Design View LwIP echo server screen

48 Run the LwIP Ethernet Design From a Windows prompt on the PC Host, enter the command: ping Ping from PC host to ZC706 target

49 Compile ZC706 BIST Design

50 Compile ZC706 BIST Design Open Vivado Start All Programs Xilinx Design Tools Vivado Vivado Select Open Project

51 Compile ZC706 BIST Design Open the ZC706 Design: <Design Name>\zc706_bist\zc706_bist.xpr

52 Compile ZC706 BIST Design The design is fully implemented; you can recompile, or export to SDK To recompile, right-click synth_1, select Reset Runs then Generate Bitstream

53 Compile ZC706 BIST Design Once done, both the Synthesis and Implementation will have green check marks

54 Compile ZC706 BIST Design The BIST Design has been implemented with IP Integrator (IPI) Click Open Block Design

55 Compile ZC706 BIST Design All the IP Blocks used in the design can be seen in this view Click Open Implemented Design

56 Compile ZC706 BIST Design View Implemented Design

57 Compile ZC706 BIST Design Select File Export Export Hardware Click OK

58 Compile ZC706 BIST Design Select File Launch SDK Click OK

59 Compile ZC706 Software in SDK SDK Software Compile - Build ELF files in SDK

60 Creating a BOOT Image

61 Creating a BOOT Image As per AR51782, the FSBL has been modified to speed up QSPI access: To: u32 Prescaler = XQSPIPS_CLK_PRESCALE_8; u32 Prescaler = XQSPIPS_CLK_PRESCALE_2;

62 Creating a BOOT Image Select bist_app Select Xilinx Tools Create Zynq Boot Image

63 Creating a BOOT Image Create the BIST MCS Use the default BIF file path The file paths should be in this order: zynq_fsbl.elf system_wrapper.bit bist_app.elf If any of these files are missing, add them Set the Output path to: C:\zc706_bist\ready_for_d ownload\bist_app.mcs Click Create Image

64 Creating a BOOT Image With bist_app still selected, select Xilinx Tools Create Zynq Boot Image

65 Creating a BOOT Image Import the BIST BIF file The tool reloads your previous settings Set the Output path to: C:\zc706_bist\ready_for_d ownload\boot.bin Click Create Image

66 Creating a BOOT Image Two files are created: bist_app.mcs for programming the Flash BOOT.bin for use on an SD card

67 Programming the ZC706 QSPI

68 Programming the ZC706 QSPI Set SW11 DIP Switches to Cycle board power

69 Programming the ZC706 QSPI Select Xilinx Tools Program Flash

70 Note: Programming takes about 4 minutes Programming the ZC706 QSPI Select the bist_app.mcs as the image file Select qspi_dual_parallel Select Verify Click Program

71 Programming the ZC706 QSPI After programming is complete, set the SW11 DIP switches to boot from QSPI: 00010

72 Programming the ZC706 QSPI Push POR_B Button (SW2) Note: Presentation applies to the ZC706

73 Run the USB Design from SDK

74 Run the USB Design from SDK Set SW11 DIP Switches to Cycle board power

75 Run the USB Design from SDK Select hello_usb Under the green Run button, select Run As Launch on Hardware

76 Run the USB Design from SDK View your current set of disk drives

77 Run the USB Design from SDK An extra removable drive will appear In this case, G:

78 Run the USB Design from SDK Open the G: drive A Disk is not formatted message will appear If this is the correct drive, click Yes; if not, click No

79 Run the USB Design from SDK A format dialog for drive G: will appear The size should be 1.00 MB If this is the correct, click Start Close this dialog when done

80 Run the USB Design from SDK At this point, you can copy small files to G: and verify the operation of this drive

81 Run the LwIP Ethernet Design

82 Run the LwIP Ethernet Design Set SW11 DIP Switches to Cycle board power

83 Run the LwIP Ethernet Design Select lwip_echo_server Under the green Run button, select Run As Launch on Hardware

84 Run the LwIP Ethernet Design View LwIP echo server screen

85 Run the LwIP Ethernet Design From a DOS window on the PC Host, enter the command: ping Ping from PC host to ZC706 target

86 References

87 References IP Integrator Documentation Vivado Design Suite Tcl Command Reference Guide UG835 ug835-vivado-tcl-commands.pdf Designing IP Subsystems Using IP Integrator UG994 ug994-vivado-ip-subsystems.pdf 7 Series Configuration 7 Series FPGAs Configuration User Guide

88 Documentation

89 Documentation Zynq-7000 Zynq-7000 All Programmable SoC ZC706 Documentation Zynq-7000 AP SoC ZC706 Evaluation Kit ZC706 Getting Started Guide UG961 ug961-zc706-gsg.pdf ZC706 User Guide UG954 ug954-zc706-eval-board-xc7z045-ap-soc.pdf