Changes in timetable (changes in GREEN)
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1 Changes in timetable (changes in GREEN) Wk12: May25 29 HLAB5 PICOBLAZE assembly Wk13: Jun1 5 Still hand in assignment on Wk13 Jun5 C.O.B. Wks14 15 (Jun8 19) Hardware tests Exam on Jun 22 Project lab I will post the requirements for the hardware tests plus a FAQ about the project and the hardware test methodology 3213: Digital Systems & Microprocessors: L#20 21
2 PICOBLAZE (Ctd) (KCPSM_Manual.pdf)
3 PICOBLAZE KCPSM PicoBlaze 8 bit Embedded Microcontroller User Guide for Spartan II,...FPGAs (XAPP213.pdf on the web) 3213: Digital Systems & Microprocessors: L#20 21
4 PICOBLAZE KCPSM ARCHITECTURE 3213: Digital Systems & Microprocessors: L#18_19
5 PICOBLAZE KCPSM ARCHITECTURE 3213: Digital Systems & Microprocessors: L#18_19
6 PICOBLAZE KCPSM3 3213: Digital Systems & Microprocessors: L#18_19
7 How to use... Assembly code KCPSM MACRO KCPSM.exe > VHDL ROM ISE design flow 3213: Digital Systems & Microprocessors: L#18_19
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11 ROM_form.coe ROM_form.coe template used by core generator defines a Dual Port Block RAM for Virtex E/Spartan II in which the A port is read only and the B port is read/write PICOBLAZE code ROM 3213: Digital Systems & Microprocessors: L#20 21
12 <filename>.coe the last line of the template contains the key words... memory_initialization_vector= these used by Core Generator to identify that the data values follow, and the assembler will append the 256 values <filename>.coe 3213: Digital Systems & Microprocessors: L#20 21
13 <filename>.fmt In addition to.vhd and.coe files there are for info <filename>.fmt is a nicely formatted form of.psm Write your PSM program quickly and then use KCPSM to make a nice formatted version for you to adopt as KCSPM Assembler your own. 3213: Digital Systems & Microprocessors: L#20 21
14 <filename>.log Details about implementation how addresses and opcodes have been assigned : Digital Systems & Microprocessors: L#20 21
15 constant.txt / labels.txt These two files provide a list of the line labels and their associated addresses, and a list of constants and their values as defined by constant directives in the program file. These can be useful during the development of larger programs. 3213: Digital Systems & Microprocessors: L#20 21
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18 Program Syntax Instructions and the first operand must be separated by at least one space. Instructions with two operands must have a comma (,) separator. 3213: Digital Systems & Microprocessors: L#20 21
19 Three directives CONSTANT NAMEREG ADDRESS 3213: Digital Systems & Microprocessors: L#20 21
20 CONSTANT directive provides a way to assign a label to an 8 bit constant value Declare port addresses and particular values change the constant value once in the directive and its effect applied to multiple places in the program
21 NAMEREG directive provides a way to assign a new name to any of the 16 registers programs can refer to variables by name rather than as absolute register specifications easier to understand the meaning in the program help to prevent inadvertent reuse of a register and data corruption
22 ADDRESS directive force the assembly of the following instructions commencing at a new address value useful for separating subroutines into specific locations vital for handling interrupts specified as a 2 digit hexadecimal value in the range 00 to FF address FF
23 ADDRESS directive (ctd) 3213: Digital Systems & Microprocessors: L#20 21
24 Interrupt Handling By default the interrupt input is disabled. Enabling Interrupts ENABLE INTERRUPT. Disabling Interrupts DISABLE INTERRUPT. ISRs automatically disable the interrupts Use RETURNI to return also includes option to ENABLE of DISABLE What happens during an interrupt? program counter is pushed onto the stack values of the CARRY and ZERO flags are preserved (restored by RETURNI). The interrupt input is automatically disabled. Finally the program counter is forced to address FF (memory location) from which the next instruction is executed. 3213: Digital Systems & Microprocessors: L#20 21
25 Basics of Interrupt Handling Since the interrupt will force control to address FF > need to ensure that a JUMP vector to a suitable ISR is located at this FF address Otherwise program control rolls over to zero! (WHY?) ISRs can be located anywhere in code. ISR performs required task then executes RETURN1 Example:
26 Interrupt Service Routine A AA Code B0 B0 B1 B2 B3 FF FF ;Interrupt example ; CONSTANT waveform_port, 02 CONSTANT counter_port, 04 CONSTANT pattern_ , AA NAMEREG sa, interrupt_counter ; start: LOAD interrupt_counter[sa], 00 LOAD s2, pattern_ [aa] ENABLE INTERRUPT ;bit0 will be data ;reset int count ;start pattern Main program delay loop where most time is spent ; E202 drive_wave: OUTPUT s2, waveform_port[02] 0007 LOAD s0, 07 ;delay size 6001 loop: SUB s0, 01 ;delay loop 9505 JUMP NZ, loop[05] 32FF XOR s2, FF ;toggle waveform 8103 JUMP drive_wave[03] Interrupt Service routine ; (here located at address B0 onwards) ADDRESS B0 4A01 int_routine : ADD interrupt_counter[sa], 01 ;increment counter EA04 OUTPUT interrupt_counter[sa], counter_port[04] 80F0 RETURNI ENABLE ; ADDRESS FF ;set interrupt vector 81B0 JUMP int_routine[b0] Interrupt vector set at address FF causes jump to ISR
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28 (Digilent BASYS UG129.pdf) 3213: Digital Systems & Microprocessors: L#20 21
29 Why cover KCPSM3? Digilent Basys board uses a XC3S100 FPGA (SPARTAN 3E) KCPSM3 implementation in VERILOG thus we can design the top module! Also more powerful core than KCPSM assembly language virtually identical Thus we can look at working examples! but not perfect (I am still learning) 3213: Digital Systems & Microprocessors: L#20 21
30 KCPSM3 PICOBLAZE (c.f. KCPSM) 16 byte wide general purpose data registers (same) 1K instructions of programmable on chip program store, automatically loaded during FPGA configuration (c.f. 256) Byte wide Arithmetic Logic Unit (ALU) with CARRY and ZERO indicator flags (same) 64 byte internal scratchpad RAM (none) 256 input and 256 output ports for easy expansion and enhancement (sam Automatic 31 location CALL/RETURN stack (c.f. 15) Predictable performance, always two clock cycles per instruction, up to 200 MHz or 100 MIPS in a Virtex II Pro FPGA (same but faster FPGAs) Fast interrupt response; worst case 5 clock cycles (same) Optimized for Xilinx Spartan 3, Virtex II, and Virtex II Pro FPGA arch just 96 slices and 0.5 to 1 block RAM Assembler, instruction set simulator support (yes) 3213: Digital Systems & Microprocessors: L#20 21
31 3213: Digital Systems & Microprocessors: L#20 21
32 Interfacing External interface to top module here 3213: Digital Systems & Microprocessors: L#20 21
33 Example: Interrupts: 3213: Digital Systems & Microprocessors: L#20 21
34 Example: Interrupts: interrupts.psm CONSTANT waveform_port, 02 CONSTANT counter_port, 04 CONSTANT pattern_ , AA NAMEREG sa, interrupt_counter start: LOAD interrupt_counter, 00 LOAD s2, pattern_ ENABLE INTERRUPT ; drive_wave: OUTPUT s2, waveform_port LOAD s0, 07 loop: SUB s0, 01 JUMP NZ, loop XOR s2, FF JUMP drive_wave ; ADDRESS 3B0 int_routine: ADD interrupt_counter, 01 OUTPUT interrupt_counter, counter_port RETURNI ENABLE ; ADDRESS 3FF JUMP int_routine 3213: Digital Systems & Microprocessors: L#20 21
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36 Example: Interrupts Run./assemble.bat 3213: Digital Systems & Microprocessors: L#20 21
37 Example: Instantiations module inttop ( input wire clk, input wire rst, input wire interrupt, output reg [7:0] leds ); inter inter_inst (.address(address),.instruction(instruction),.reset(reset),.rst(rst),.clk(clk)); kcpsm3 kcpsm3_inst (.address(address),.instruction(instruction),.port_id(port_id),.write_strobe(write_strobe),.out_port(out_port),.read_strobe(read_strobe),.in_port(in_port),.interrupt(interrupt),.interrupt_ack(interrupt_ack),.reset(reset),.clk(clk)); 3213: Digital Systems & Microprocessors: L#20 21
38 Example: top module module inttop (input wire clk, input wire rst, input wire interrupt, output reg [7:0] leds ); wire [9:0] address; wire [17:0] instruction; wire [7:0] port_id; wire [7:0] out_port; reg [7:0] in_port; wire write_strobe; wire read_strobe; wire interrupt_ack; kcpsm3 kcpsm3_inst (.address(address),.instruction(instruction),.port_id(port_id),.write_strobe(write_strobe),.out_port(out_port),.read_strobe(read_strobe),.in_port(in_port),.interrupt(interrupt),.interrupt_ack(interrupt_ack),.reset(reset),.clk(clk)); inter inter_inst (.address(address),.instruction(instruction),.reset(reset),.rst(rst),.clk(clk)); Invariant clk) begin if (write_strobe) begin if (port_id == 8'h02) begin leds[7:4] <= out_port[ leds[3:0] <= 4'b1111; end else if (port_id == 8'h04) begin leds[3:0] <= out_port[ leds[7:4] <= 4'b0000; end else leds <= 8'h00; end end Output drive endmodule Multiplex waveform and interrupt counter output IMPROVE!
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42 Example: Does it work?? 3213: Digital Systems & Microprocessors: L#20 21
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