ASNTu2s PCB with Tiger Board USB to 7-Channel 3-Wire Interface Bridge Application Notes

Transcription

1 ASNTu2s PCB with Tiger Board USB to 7-Channel 3-Wire Interface Bridge Application Notes Table of Contents Tiger Board Description... 2 ASNTu2s Description... 2 Software Installation... 3 Bridge and GUI Operation... 4 SPI Operation... 6 ASNT8110A GUI Description... 8 ASNT8172 GUI Description... 9 ASNT6171 GUI Description ASNT6152 GUI Description REVISION HISTORY Rev

2 Tiger Board Description 1. The Tiger Board shown in Fig. 1 is a universal USB-controlled Master/Slave SPI/I2C/JPIO interface. For the current application, it is configured as a 7-channel SPI interface. It includes a SPARTAN-6 FPGA with support components, a micro-usb connector, as well as a 40-pin and 34-pin male connectors. The board measures approximately 3.2x2.4 inches. More details can be found on the Nano River Technology web site at specifically in the document. Fig. 1. Tiger Board 2. In the current configuration, the 34-pin male connector is used to deliver signals to the ASNTu2s PCB that serves as an adapter. ASNTu2s Description 1. The ASNTu2s v2.0 PCB shown in Fig. 2 is a 7-channel splitter and 3.3V-to-1.2V level converter for the SPI interface. It includes a set of bi-directional level converting ICs, a MOLEX connector (J0) for a 1.2V power supply, a 34-pin female connector, and seven 7-pin SATA connectors (J1-J7). There are also 4 bi-directional low-pass filters (LPFs) for optional cleaning of any DC control signals. The board measures approximately 3.2x2.4 inches. Rev

3 34-pin female connector +1.2V gnd Fig. 2. ASNTu2s v2.0 7-pin SATA connectors 2. The ASNTu2s PCB v2.0 allows for control of up to seven DC-coupled 1.2V 3-wire SPI channels through a USB port. The board delivers the same clock (clk) and data (di or d) signals to all seven SATA connectors. Seven enable signals (en1-en7) are delivered to connectors J1-J7 respectively. 3. The connector J1 provides access to the channel 1 output data signal (do1). The SATA connector mapping is shown in Table 1. Table 1. SATA Connector Mapping 4 LPFs Pin # gnd enx clk gnd di do1 for J1 or n/c for J2 to J9 gnd 4. The ASNTu2s v2.0 PCB also allows for filtering of up to four DC control signals using bi-directional LPFs with input/output connector pair J8_x/J9_x, where x=0,1,2,3. Any connector of the pair can be used as the filter input, while the other one serves as the corresponding output. Software Installation 1. Use the CD provided or Download the Tiger Board software for the required operation system (supported operation systems are Microsoft Windows XP with Service Pack 3 and newer) from Nano River Technology web site: 2. Install the Tiger Board software following instructions: 2.1. For Windows XP use the provided file WinXP_Installation_of_TigerBoard.pdf or the link For Windows 7 or newer use the provided file Win7_Installation_of_TigerBoard.pdf or the link 3. Double-click the file ASNTxxxx_setup.exe for each particular part and follow the instructions on the screen. Rev

4 Bridge and GUI Operation 1. The part is static sensitive. Please observe anti-static protection procedures! 2. Connect the Tiger Board to a computer using a USB cable. 3. Attach the ASNTu2s PCB to the Tiger Board as shown in Fig. 3. Fig. 3. ASNTu2s and Tiger Board Assembly 4. Switch on an external power supply unit and set it to a positive supply voltage with a value of +0.0V (negative output pin of the unit must be shorted to ground). 5. Connect the supply unit s output pins to the PCB s Molex connector as shown in Fig Connect the ASNTu2s channels to controlled PCBs following the GUI descriptions below. Note 1: The GUI will function correctly even if some PCBs are not connected. 7. Gradually increase the positive supply voltage to +1.35V. 8. Initiate the GUI by double-clicking the corresponding executable file. The GUI enters the Standard operational mode, and sends default data after its activation. The GUI may have several panels for control of multiple boards. Note 2: The GUI will operate in a Demo mode if the Tiger Board is not connected to the computer. The red note Board not connected. Demonstration Mode Only disappears when the USB port is connected. 9. Load a state or use the default one. To load a state from a file, click on "File" menu, then select "Load state" from the pull-down menu. Using Windows navigator, select a file to load. The new data will be sent automatically. 10. Modify the GUI controls as required. The controls can be manipulated as follows: Buttons can be clicked ON (checked) or OFF (empty) The arrows may be clicked (1-step change) or clicked-and-hold (constant change) The number in the windows can be directly typed in. Click Enter to confirm. 11. The GUI sends new data after any slider adjustment, arrow click, or data confirmation. 12. The current state of the GUI can be saved and then loaded back. To save the current state in a file, click on "File" menu, then select "Save state" from the pull-down menu. Using Windows navigator, select a directory and enter a file or select an existing file. 13. The GUI can also operate in Expert mode. To activate the Expert mode, click on "File" menu and select "Enter Expert Mode" from the pull-down menu. Rev

5 14. In Expert mode, the following additional options are available: Selection of certain pre-assigned operational frequencies for the interface. To change the interface operational frequency, click the Frequency arrow and select the desired value from the pull-down menu Assignment of the active channel number. To assign a different channel to a particular panel, click the corresponding Channel arrow, and select the desired value from the pull-down menu. Note 3: The controlled PCB should be connected to the assigned channel of the ASNTu2s Visual control of the clock polarity (CPOL) and phase (CPHA) parameters. For the current application, both parameters are set to 0. For more details see the EQ_3w_AN document Visual control of the sent and received data packets (Writing: and Reading: lines in the additional panel at the bottom of the GUI window). The transmission information (panel and channel number) precedes the Writing: and Reading: lines. Note 4: Data reading is delayed by one cycle compared to data writing. In case of the correct SPI operation, the previous writing (top line) should be equal to the current reading (bottom line). Note 5: Full received data is displayed for channel 1 only. For other channels, the Reading: line displays a special bit as described on p.20 of the Tiger Board API specification document To return to the Standard mode, click on "File" menu, then select "Enter Standard Mode" from the pull-down menu. Rev

6 SPI Operation The Serial Peripheral Interface Bus (SPI) is a synchronous serial data link that operates in full duplex mode. SPI devices communicate in master/slave mode where the master device initiates the data frame. The simplest SPI configuration is shown in Fig. 4. SCLK Serial Clock (output from master) MOSI Master Output, Slave Input (output from master) MISO Master Input, Slave Output (output from slave) SSn Slave Select (active low; output from master) Fig. 4. SPI Bus: Single Master and Single Slave A typical hardware setup uses shift registers to form an inter-chip circular buffer. If the system does not require reading from the slave, the MISO output can be used for functional test purposes as shown in Fig. 5. TEST Fig. 5. SPI 8-bit circular transfer Multiple slave devices are allowed with individual slave select lines SSn as shown in Fig. 6. Rev

7 SCL MOSI MOSI SCLK MOSI SCLK MOSI SCLK SPI Master SPI Slave SPI Slave SPI Slave SSn SSn SSn SSn1 SSn2 SSn3 Fig. 6. SPI with Three Slaves SPI can operate in different modes defined by clock polarity CPOL and clock phase CPHA parameters as shown in Table 2. Table 2. SPI Operational Modes CPOL CPHA The first clock edge is: Data is sampled by: 0 0 Rising the leading (first) clock edge 0 1 Rising the trailing (second) clock edge 1 0 Falling the leading (first) clock edge 1 1 Falling the trailing (second) clock edge The on-chip SPI module operates only in slave mode with CPOL=0 and CPHA=0, as shown in Fig. 7. SCLK SSn Sample Latch MOSI X X Byte 1 Byte N Fig. 7. SPI Transfer Mode Rev

8 ASNT8110A GUI Description 1. The ASNT8110A GUI is activated by double-clicking on the spiasnt8110a.exe file. 2. The default ASNT8110A GUI window for the Standard operational mode is shown in Fig. 8. It has a scroll bar and a display window with additional up/down arrows for the division coefficient assignment. It operates with channel 1 (connector J1) of the ASNTu2s PCB v.1.0 or any channel of the ASNTu2s PCB v.2.0. Fig. 8. ASNT8110A GUI Window in Standard Operational Mode 3. The GUI can also operate in Expert mode with the window shown in Fig. 9. Fig. 9. ASNT8110A GUI Window in Expert Operational Mode Rev

9 ASNT8172 GUI Description 4. The ASNT8172 GUI is activated by double-clicking on the spiasnt8172.exe file. 5. The default ASNT8172 GUI window for the Standard operational mode is shown in Fig. 10. It has 26 scroll bars with associated display windows and additional up/down arrows, as well as 10 switch buttons. It operates with channel 1 (connector J1) of the ASNTu2s PCB v.1.0 or any channel of the ASNTu2s PCB v.2.0. Fig. 10. ASNT8172 GUI Window in Standard Operational Mode 6. The GUI is intended for control of the ASNT tap FIR filter chip (see the AN_ASNT8172onASNT12_6 document). 7. There are the following controls: 7.1. A group of 18 scroll bars and 9 buttons arranged in 9 rows in the left-side part of the window. Each row corresponds to one tap and includes a tap number (Tap 1 through 9), a peak control bar (peak control, numbers from 0 to 63), a tap activation button (on), and a weight control bar (weight control, numbers from -63 to +63) A group of 6 scroll bars and 1 button in the right-side part of the window. The bars control currents of the output emitter followers (ef0-4, numbers from 0 to 63) and the pre-buffer (pbuf, numbers from 0 to 15), while the button switches the pre-buffer on or off Two scroll bars and one button at the bottom of the window. The button activates the on-chip replica with its gain controlled by the bar gain control (numbers from 0 to 7). The other bar (DAC control, numbers from 0 to 63) controls the performance of internal DACs The corresponding GUI control s are explained in Table 3. Rev

10 Table 3. ASNT8172 Data Transfer Protocol Byte GUI Range # # function 1 ontap1 Tap ON/OFF ON ondir1 Tap weight control weight control ±63 From 3 to 8 wc1 From 1 to 6 pk1 Tap peaking control peak control ontap2 Tap ON/OFF ON ondir2 Tap weight control weight control ±63 From 3 to 8 wc2 From 1 to 6 pk2 Tap peaking control peak control ontap3 Tap ON/OFF ON ondir3 Tap weight control weight control ±63 From 3 to 8 wc3 From 1 to 6 pk3 Tap peaking control peak control ontap4 Tap ON/OFF ON ondir4 Tap weight control weight control ±63 From 3 to 8 wc4 From 1 to 6 pk4 Tap peaking control peak control ontap5 Tap ON/OFF ON ondir5 Tap weight control weight control ±63 From 3 to 8 wc5 From 1 to 6 pk5 Tap peaking control peak control ontap6 Tap ON/OFF ON ondir6 Tap weight control weight control ±63 From 3 to 8 wc6 From 1 to 6 pk6 Tap peaking control peak control ontap7 Tap ON/OFF ON ondir7 Tap weight control weight control ±63 From 3 to 8 wc7 From 1 to 6 pk7 Tap peaking control peak control ontap8 Tap ON/OFF ON ondir8 Tap weight control weight control ±63 From 3 to 8 wc8 From 1 to 6 pk8 Tap peaking control peak control ontap9 Tap ON/OFF ON ondir9 Tap weight control weight control ±63 From 3 to 8 wc9 18 From 1 to 6 pk9 Tap peaking control peak control 0-63 Rev

11 Byte # GUI # function Range From 1 to 6 efi0 EF current control ef From 1 to 6 efi1 EF current control ef From 1 to 6 efi2 EF current control ef From 1 to 6 efi3 EF current control ef From 1 to 6 efi4 EF current control ef From 1 to 6 DACcmcrl DAC calibration DAC control offrep Replica activation onrep 8 not used From 1 to 3 ffegn Replica gain control gain control onpb_1 Pre-buffer activation pbuf From 5 to 8 onmaini Pre-buffer gain control The GUI can also operate in Expert mode with the window shown in Fig. 11. Fig. 11. ASNT8172 GUI Window in Expert Operational Mode Rev

12 ASNT6171 GUI Description 1. The ASNT6171 GUI is activated by double-clicking on the spiasnt6171.exe file. 2. The default GUI window is shown in Fig. 12. It can have up to three similar panels. Each panel operates with two channels of the ASNTu2s PCB v.2.0 and provides control of one chip. 3. To select the number of chips from 1 to 3, click the corresponding Number of chips arrow and select the desired value from the pull-down menu. a. b. Fig. 12. GUI Window in 1-Chip (a) and 3-Chip (b) Standard Operational Modes 4. Each chip incorporates two SPIs: Left and Right. The corresponding GUI control s are explained in Table 4 and Table 5. Rev

13 Table 4. Left SPI Data Transfer Protocol Byte # # order function GUI Range 1 X and Y channels Input buffers IBs crlgn gain control Gain Tap0 2 crlyi0 Tap0 YI buffer gain control YI Tap0 3 crlyq0 Tap0 YQ buffer gain control YQ Tap1 4 crlyi1 Tap1 YI buffer gain control YI Tap1 5 crlyq1 Tap1 YQ buffer gain control YQ Tap2 6 crlyi2 Tap2 YI buffer gain control YI Tap2 7 crlyq2 Tap2 YQ buffer gain control YQ Tap3 8 crlyi3 Tap3 YI buffer gain control YI Tap3 9 crlyq3 Tap3 YQ buffer gain control YQ 10 X and Y channels buffer5 s Buf crlg5 gain control Gain Tap4 11 crlyi4 Tap4 YI buffer gain control YI Tap4 12 crlyq4 Tap4 YQ buffer gain control YQ Tap5 13 crlyi5 Tap5 YI buffer gain control YI Tap5 14 crlyq5 Tap6 YQ buffer gain control YQ 15 crlyi6 Tap6 YI buffer gain control Tap6 Rev

14 Byte # # order function GUI YI Tap6 crlyq6 Tap6 YQ buffer gain control YQ Tap7 crlyi7 Tap7 YI buffer gain control YI Tap7 crlyq7 Tap7 YQ buffer gain control YQ Tap8 crlyi8 Tap8 YI buffer gain control YI Tap8 crlyqi8 Tap8 YQ buffer gain control YQ From 1 to 8 Not used X and Y channels buffer10 s Buf10 crlg10 gain control Gain Tap9 crlyi9 Tap9 YI buffer gain control YI Tap9 crlyq9 Tap9 YQ buffer gain control YQ Tap10 crlyi10 Tap10 YI buffer gain control YI Tap10 crlyq10 Tap10 YQ buffer gain control YQ Tap11 crlyi11 Tap11 YI buffer gain control YI Tap11 crlyq11 Tap11 YQ buffer gain control YQ Tap12 crlyi12 Tap12 YI buffer gain control YI Range Rev

15 Byte # # order function GUI Range crlyq12 Tap12 YQ buffer gain control crlyi13 Tap13 YI buffer gain control crlyq13 Tap13 YQ buffer gain control crlyi14 Tap14 YI buffer gain control crlyq14 Tap14 YQ buffer gain control Tap12 YQ Tap13 YI Tap13 YQ Tap14 YI Tap14 YQ Table 5. Right SPI Data Transfer Protocol Byte # # order crlpk crlxi0 crlxq0 crlxi1 crlxq1 crlxi2 crlxq2 function X and Y channels Input buffers peaking control Tap0 buffer gain control Tap0 buffer gain control Tap1 buffer gain control Tap1 buffer gain control Tap2 buffer gain control Tap2 buffer gain control GUI IBs Peak Tap0 Tap0 Tap1 Tap1 Tap2 Tap2 Range Rev

16 Byte # # order crlxi3 crlxq3 crlp5 crlxi4 crlxq4 crlxi5 crlxq5 crlxi6 crlxq6 crlxi7 crlxq7 crlxi8 crlxqi8 crlout crlp10 function Tap3 buffer gain control Tap3 buffer gain control X and Y channels buffer5 s peaking control Tap4 buffer gain control Tap4 buffer gain control Tap5 buffer gain control Tap6 buffer gain control Tap6 buffer gain control Tap6 buffer gain control Tap7 buffer gain control Tap7 buffer gain control Tap8 buffer gain control Tap8 buffer gain control Q and I output buffers gain control X and Y channels buffer10 s peaking control GUI Tap3 Tap3 Buf5 Peak Tap4 Tap4 Tap5 Tap5 Tap6 Tap6 Tap7 Tap7 Tap8 Tap8 OB Gain Buf10 Peak Range Rev

17 Byte # # order crlxi9 crlxq9 crlxi10 function Tap9 buffer gain control Tap9 buffer gain control Tap10 buffer gain control crlxq10 Tap10 buffer gain control crlxi11 Tap11 buffer gain control crlxq11 Tap11 buffer gain control crlxi12 Tap12 buffer gain control crlxq12 Tap12 buffer gain control crlxi13 Tap13 buffer gain control crlxq13 Tap13 buffer gain control crlxi14 Tap14 buffer gain control crlxq14 Tap14 buffer gain control GUI Tap9 Tap9 Tap10 Range Tap10 Tap11 Tap11 Tap12 Tap12 Tap13 Tap13 Tap14 Tap14 Note 10: By default, Right SPIs correspond to channels 1, 3, or 5 and Left SPIs correspond to channels 2, 4, or 6. Rev

18 5. The taps can be controlled symmetrically around a central tap. For that, set the number of the desired central tap for the desired line (e.g. Central tap 5 line 1) and then adjust the taps to the right from the central tap. The left-side taps will adjust automatically. An additional correction can be assigned to all left-side taps (e.g. Left mirror correction -2). 6. The GUI can also operate in Expert mode with an example of the 1-chip window version shown in Fig. 13. Fig. 13. GUI Window in Expert Operational Mode Rev

19 ASNT6152 GUI Description 7. The ASNT6152 GUI is activated by double-clicking on the spiasnt6152.exe file. 8. The default GUI window is shown in Fig. 14. a. b. Fig. 14. GUI Window in 1-Chip (a) and 2-Chip (b) Standard Operational Modes An input data bit mapping required for the chip is presented in Table 6. Table 6. ASNT6152 Data Transfer Protocol Byte # # order function GUI Range 1 EQ Controls e1ch1 Channel 1 Stage 1 EQ control Ch1: St1 2 EQ Controls e2ch1 Channel 1 Stage 2 EQ control Ch1: St2 3 EQ Controls e1ch2 Channel 2 Stage 1 EQ control Ch2: St1 4 EQ Controls e2ch2 Channel 2 Stage 2 EQ control Ch2: St2 5 Err.Det del Error Detector delay control Delay 6 1 MSB Feedback switch: 1 on, Err.Det. 0-1 on_fb 0 - off FB On OB Gain amp Output Buffer gain control to 8 2 nd MSB 7 1 MSB Error Detector switch: 1 on, Err.Det. On 0-1 on_ed 0 - off Err.Det eda Error Detector gain control to 8 2 nd MSB Ampl Rev

20 9. The GUI can also operate in Expert mode with the window shown in Fig. 15. Fig. 15. GUI Window in Expert Operational Mode REVISION HISTORY Revision Date Changes Corrected versions of GUI for ASNT8110A and ASNT Corrected SPI coding tables New versions of GUI for ASNT6171 and ASNT Added new GUI descriptions Updated Fig. 12 and Fig Corrected Table New version of the GUI. Updated Fig. 12 and Fig. 13. Updated GUI description Modified PCB layout (7 channels, 4 additional LPFs). Corrected Fig. 2. Corrected title. Corrected PCB description Corrected GUI window drawing First release Rev