ASNT1011A-PQA-Evaluation Board DC-17Gbps Digital Multiplexer 16:1 / Serializer Application Note

Transcription

1 Overview ASNT1011A-PQA-Evaluation Board DC-17Gbps Digital Multiplexer 16:1 / Serializer Application Note ASNT1011A-PQA is a low power and high-speed digital 16:1 multiplexer (MUX) / serializer IC. The function of the ASNT1011A-PQA is to multiplex sixteen parallel data channels running at a bit rate of fbit/16 into a high-speed serial bit stream running at fbit. It provides a high-speed output data channel for point-to-point data transmission over a controlled impedance media of 50Ohms. The transmission media can be a printed circuit board or copper coaxial cables. The functional distance of the data transfer is dependent upon the attenuation characteristics of the transportation media and the degree of noise coupling to the signaling environment. During normal operation, the serializer s low-speed input buffer (LS DIBx16) accepts external 16-bit wide parallel data words d00p/d00n-d15p/d15n through sixteen differential LVDS inputs, and delivers them to the multiplexer s core (MUX16:1) for serialization. A full rate clock must be provided by an external source to cep/cen which connect to the internal highspeed clock input buffer (HS CIB) where it is routed to the high speed clock output buffer (HS COB) and the internal divider-by-16 (/16). The divider provides signaling for MUX16:1, and produces a clock divided-by-16 (C16) for the low speed LVDS compliant clock output buffer (LVDS COB). The phase of clop/clon can be modified by 90 increments by pins phs1 and phs2, and the clock processing block (CLK Proc). By utilizing pin bitorder, the serializer can designate either d00p/d00n or d15p/d15n as the MSB thus simplifying the interface between ASNT1011A-PQA and a proceeding ASIC. The serialized words are transmitted as 2-level signals qcmlp/qcmln by a differential CML output buffer (Data OB). A full-rate clock is transmitted by HS COB in parallel with the high-speed data. The clock and data outputs are phase matched to each other resulting in very little relative skew over the operating temperature range of the device. Both output stages are back terminated with on-chip 50Ohms resistors. The board operates from a single +3.3V power supply. Evaluation board Operation ADSANTEC s evaluation board ASNT01_71 contains eight Emerson edge-mount female SMA connectors MFG PN: , thirty six vertical mount SMA connectors MFG PN: RSA-3350, 50Ohm transmission lines to the device, and power supply decoupling networks on the evaluation board. It measures approximately 5.36 x 8.0 inches without connectors. It utilizes a MOLEX connector MFG PN: to supply power. Figure 1 shows the evaluation board with its corresponding connections for operation. 1. Refer to Figure 1 for all referenced inputs/outputs. 2. Refer to Table 1 for all required switch positions. 3. Measure the resistance of all connector pins in reference to VCC, including the power supply, while making sure the board is grounded. The data/clock outputs and clock inputs should measure 50Ohms. Figure 2 shows the corresponding resistances for the described connections. Rev October 2015

2 Figure 1. Pin description Switch block SW1 SW2 Switch No. Name on the PCB On-chip name Required state of the Switch 1 /Vecl - open 2 /Vcml - open 3 PH1 phs1 4 PH2 phs2 See Table open 6 ML/DIG closed 7 (3-sw) - closed 8 closed 1 CHO/off - open 2 C/C2 - open 3 PLL/off - open open 5 12G/8G - open 6 DLY- /DLY+ - open 7 16b/8b - open 8 LVDS/other - open Table 1. Switches Rev October 2015

3 Figure 2. Ohmic check 4. Set a positive power supply to 0V, while placing its current limit at 250mA. Ramp the supply slowly up to +3.3V. The board should draw approximately 200mA. 5. Apply low speed AC coupled single-ended or differential data signals to inputs d00p/d00n to d15p/d15n. If any input is used single-ended, terminate the unused data input with a DC block, and a 50Ohms load. Note: LVDS Data Inputs d00p/d00n to d15p/d15n interface is LVDS, and using a 50Ohms source data may be used AC coupled to these inputs. This is acceptable for checking functionality, and will not damage anything. 6. Apply a high speed AC coupled single-ended or differential clock signal to cep/cen. If being used single-ended, terminate the unused clock input with a DC block, and a 50Ohms load. 7. Connect outputs qcmlp/qcmln single-ended or differential AC coupled to an oscilloscope with a 50Ohms termination. If connected single-ended, terminate the unused output with a DC block, and a 50Ohms load. Examine the data output signal on the scope. 8. Connect outputs chop/chon single-ended or differential AC coupled to an oscilloscope with a 50Ohms termination. If connected single-ended, terminate the unused output with a DC block, and a 50Ohms load. Examine the clock output signal on the scope. 9. Connect outputs clop/clon single-ended or differential AC coupled to an oscilloscope with a 50Ohms termination. If connected single-ended, terminate the unused output with a DC block, and a 50Ohms load. Examine the clock-divided-by-16 output signal on the scope. Rev October 2015

4 Phase Switch state value phs1 phs2 0º OFF OFF 90º OFF ON 180º ON OFF 270º ON ON Table 2. Low speed clock phase select Note: The outputs clop/clon interface is LVDS, and therefore what you observe is a distorted waveform due to using a LVDS signal connected to a 50Ohms terminated oscilloscope. This is acceptable for checking functionality, and will not damage anything. 10. To adjust the clock phase of the Divided by 16 Clock Output clop/clon outputs, refer to Table 2 for all possible phase outputs settings. Rev October 2015

5 Board Dimensions Revision History Revision Date Changes Title and Formatting Correction Added Board Dimensions Diagram Updated Formatting Initial Release Rev October 2015