Datasheet for Nios II Processor (nios2_r1c) v.3, July Processor Details GENERATION SYSID
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1 Processor Details NAME "cpu_r1" FREQ RESET_ADDR 0x0 EXCEPTION_ADDR 0x20 IMPLEMENTATION "small" ARCHITECTURE "altera_nios2" Instruction cache Data cache Little Endian HARDWARE_DIVIDE_PRESENT HARDWARE_MULTIPLY_PRESENT false PIN_N2 CLOCK_50 PIN_G26 KEY[0] reset_n GENERATION Tue Jul 24 19:23:25 MDT 2012 Files: Jul 25 23:28 nios2_r1c.pof Jul 23 21:41 nios2_r1c.ptf Jul 25 23:28 nios2_r1c.sof Jul 23 21:40 nios2_r1c.sopcinfo SYSID "altera_avalon_sysid" BASE 0x8890 (SYSID_BASE) SPAN 8 Boise State University Microprocessors (ECE330) 1
2 ONCHIP_MEMORY "altera_avalon_onchip_memory2" BASE 0x0 (ONCHIP_MEMORY_BASE) SPAN JTAG_UART LEDR "altera_avalon_jtag_uart" BASE 0x8800 (JTAG_UART_BASE) SPAN 8 IRQ 1 READ_DEPTH 64 READ_THRESHOLD 8 WRITE_DEPTH 8 WRITE_THRESHOLD 2 BASE 0x8810 (LEDR_BASE) DATA_WIDTH 18 PIN_AD12 PIN_AE12 PIN_AE13 PIN_AF13 PIN_AE15 PIN_AD15 PIN_AC14 PIN_AA13 PIN_Y13 PIN_AA14 PIN_AC21 PIN_AD21 PIN_AD23 PIN_AD22 PIN_AC22 PIN_AB21 PIN_AF23 PIN_AE23 LEDR[17] LEDR[16] LEDR[15] LEDR[14] LEDR[13] LEDR[12] LEDR[11] LEDR[10] LEDR[9] LEDR[8] LEDR[7] LEDR[6] LEDR[5] LEDR[4] LEDR[3] LEDR[2] LEDR[1] LEDR[0] Boise State University Microprocessors (ECE330) 2
3 LEDG BASE 0x8820 (LEDG_BASE) DATA_WIDTH 9 PIN_Y12 PIN_Y18 PIN_AA20 PIN_U17 PIN_U18 PIN_V18 PIN_W19 PIN_AF22 PIN_AE22 LEDG[8] LEDG[7] LEDG[6] LEDG[5] LEDG[4] LEDG[3] LEDG[2] LEDG[1] LEDG[0] SWITCH BASE 0x8830 (SWITCH_BASE) DATA_WIDTH 18 PIN_V2 PIN_V1 PIN_U4 PIN_U3 PIN_T7 PIN_P2 PIN_P1 PIN_N1 PIN_A13 PIN_B13 PIN_C13 PIN_AC13 PIN_AD13 PIN_AF14 PIN_AE14 PIN_P25 PIN_N26 PIN_N25 SW[17] SW[16] SW[15] SW[14] SW[13] SW[12] SW[11] SW[10] SW[9] SW[8] SW[7] SW[6] SW[5] SW[4] SW[3] SW[2] SW[1] SW[0] Boise State University Microprocessors (ECE330) 3
4 SEG7 BASE 0x8840 (SEG7_BASE) DATA_WIDTH 32 PIN_V13 PIN_V14 PIN_AE11 PIN_AD11 PIN_AC12 PIN_AB12 PIN_AF10 PIN_AB24 PIN_AA23 PIN_AA24 PIN_Y22 PIN_W21 PIN_V21 PIN_V20 PIN_Y24 PIN_AB25 PIN_AB26 PIN_AC26 PIN_AC25 PIN_V22 PIN_AB23 PIN_W24 PIN_U22 PIN_Y25 PIN_Y26 PIN_AA26 PIN_AA25 PIN_Y23 HEX0[6] HEX0[5] HEX0[4] HEX0[3] HEX0[2] HEX0[1] HEX0[0] HEX1[6] HEX1[5] HEX1[4] HEX1[3] HEX1[2] HEX1[1] HEX1[0] HEX2[6] HEX2[5] HEX2[4] HEX2[3] HEX2[2] HEX2[1] HEX2[0] HEX3[6] HEX3[5] HEX3[4] HEX3[3] HEX3[2] HEX3[1] HEX3[0] PIN_T3 PIN_R6 PIN_R7 PIN_T4 PIN_U2 PIN_U1 PIN_U9 PIN_R3 PIN_R4 PIN_R5 PIN_T9 PIN_P7 PIN_P6 PIN_T2 PIN_M4 PIN_M5 PIN_M3 PIN_M2 PIN_P3 PIN_P4 PIN_R2 PIN_N9 PIN_P9 PIN_L7 PIN_L6 PIN_L9 PIN_L2 PIN_L3 HEX4[6] HEX4[5] HEX4[4] HEX4[3] HEX4[2] HEX4[1] HEX4[0] HEX5[6] HEX5[5] HEX5[4] HEX5[3] HEX5[2] HEX5[1] HEX5[0] HEX6[6] HEX6[5] HEX6[4] HEX6[3] HEX6[2] HEX6[1] HEX6[0] HEX7[6] HEX7[5] HEX7[4] HEX7[3] HEX7[2] HEX7[1] HEX7[0] Boise State University Microprocessors (ECE330) 4
5 KEY1 BASE 0x8850 (KEY1_BASE) DATA_WIDTH 1 EDGE_ "FALLING" PIN_N23 KEY[1] KEY2 BASE 0x8860 (KEY2_BASE) DATA_WIDTH 1 EDGE_ "FALLING" PIN_P23 KEY[2] KEY3 BASE 0x8870 (KEY3_BASE) DATA_WIDTH 1 EDGE_ "FALLING" PIN_W26 KEY[3] Boise State University Microprocessors (ECE330) 5
6 PORTA BASE 0x8880 (PORTA_BASE) DATA_WIDTH 32 EDGE_ "ANY" DE2 PIN Port bit Hdr PIN_F26 PIN_P18 PIN_G24 PIN_G25 PIN_H24 PIN_J24 PIN_H26 PIN_K18 PIN_K21 PIN_K24 PIN_L20 PIN_J26 PIN_L24 PIN_L19 PIN_L25 PIN_L23 PIN_J25 PIN_L21 PIN_K23 PIN_K19 PIN_H19 PIN_H25 PIN_J23 PIN_H23 PIN_K22 PIN_G23 PIN_N18 PIN_F25 PIN_J21 PIN_F24 PIN_E26 PIN_D25 PORTA[31] PORTA[30] PORTA[29] PORTA[28] PORTA[27] PORTA[26] PORTA[25] PORTA[24] PORTA[23] PORTA[22] PORTA[21] PORTA[20] PORTA[19] PORTA[18] PORTA[17] PORTA[16] PORTA[15] PORTA[14] PORTA[13] PORTA[12] PORTA[11] PORTA[10] PORTA[09] PORTA[08] PORTA[07] PORTA[06] PORTA[05] PORTA[04] PORTA[03] PORTA[02] PORTA[01] PORTA[00] GND GND V 3.3 V Boise State University Microprocessors (ECE330) 6
7 // // // file N2_r1.v // Boise State University // ECE330L Processor 1: nios2_r1x.* (sof,pof,ptf) module N2_r1 ( input CLOCK_50, // 50Mhz Clock input [ 3:0] KEY, // I Push Button[3:0] input [17:0] SW, // I DPDT Switch[17:0] output [ 6:0] HEX0,HEX1,HEX2,HEX3, // O 7 Seg Dig output [ 6:0] HEX4,HEX5,HEX6,HEX7, // O 7 Seg Dig output [ 8:0] LEDG, // O LED Green[8:0] output [17:0] LEDR, // O LED Red[17:0] inout [31:0] PORTA // O External Header (JP1) ); wire [31:0] hex_display; parameter parameter CPU1 = 7'b , CPU2 = 7'b ; RevA = 7'b , RevB = 7'b , RevC = 7'b , RevD = 7'b ; defparam BRAND.Dig7 = CPU1; defparam BRAND.Dig6 = RevC; SEG7_top_display BRAND (.CLOCK_50 ( CLOCK_50 ),.reset_n ( reset_n ),.hex_display ( hex_display ),.HEX0( HEX0 ),.HEX1( HEX1 ),.HEX2( HEX2 ),.HEX3( HEX3 ),.HEX4( HEX4 ),.HEX5( HEX5 ),.HEX6( HEX6 ),.HEX7( HEX7 ) ); nios2_r1 Mynios (.clk ( CLOCK_50 ),.reset_n ( KEY[0] ),.out_port_from_the_seg7 ( hex_display ),.in_port_to_the_key1 ( KEY[1] ),.in_port_to_the_key2 ( KEY[2] ),.in_port_to_the_key3 ( KEY[3] ),.out_port_from_the_ledg ( LEDG ),.out_port_from_the_ledr ( LEDR ),.in_port_to_the_switch ( SW ),.bidir_port_to_and_from_the_porta ( PORTA ) ); endmodule Nios2 r1c processor top level module Boise State University Microprocessors (ECE330) 7
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