Microcomputer System Design

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1 Microcomputer System Design COE305 Lab.

2 What is a Microprocessor? A microprocessor is a multipurpose, clockdriven, register-based electronic device that reads binary instructions from a storage device called memory, accept binary data as input and processes data according to the instructions given and provides results as output.

3 The 8086/8088 Fairly old microprocessors, but still considered as a good way to introduce the Intel family. Both microprocessors use 16-bit registers and 20-bit address bus (supporting 1 MB memory), but: - The 8086 (1978): 16-bit external data bus - The 8088 (1979): 8-bit external data bus Still used in embedded systems (cost is less than $1)

4 2 Modes: 8/9 pins have Different Functions Depending On the mode Pin budget: 8086, Min mode: 20 Address 16 Data 20 Control & Status 3 Power Maximum mode Operation with a Math Coprocessor Minimum mode Basic Operation I/P Selects Min/Max Mode 59 Total > 40 pins available Use multiplexing

5 Clock and Reset Circuit Using 8284 chip

6 Clock Generator (8284) Provides the following functions: Generates Clock signals: - Generates a CLK signal for the Provides a CLK sync signal (OSC) for use by slave processors on a multiprocessor 8086 systems - Provides a TTL-level peripheral clock signal (PCLK) Provides synchronization for external input signals to the processor: The RESET input The READY input for wait state generation

7 Clock Generator (8284): Signals Clocks & Clock Synchronization Signals X1 and X2: Crystal Oscillator pins. Connect a crystal of the correct frequency between these two terminals to generate the clock signal. EFI: External frequency input. Signal can be used as the clocking source to the 8284A instead of the crystal oscillator. F/#C input: Selects external EFI input (1) or the crystal oscillator (0) as the clocking source for the 8284 CLK output: The clock signal produced for connecting to the CLK input on the At 1/3 rd of the crystal or EFI input frequency with 1:3 duty cycle: f clock = f xtal /3 = f EFI /3 OSC: Oscillator output. Same frequency as crystal or EFI. Connect to EFIs on other 8284s in multiprocessor systems (synchronized clocks) f osc = f xtal = f EFI PCLK output: peripheral clock signal at 1/6 th of the crystal or EFI input frequency (1/2 clock freq) with 1:2 duty cycle. Use to drive peripheral equipment in the system f pclk = f xtal /6 = f EFI /6 CSYNC input: Clock synchronization input. Should be used if EFI is used, otherwise must be grounded. XTAL or EFI 3 2 Crystal OSC: EFI To other µps PCLK to Per CLK to µp

Clock Generator (8284): Signals RESET Signals #RES Reset input: Active low. Usually connected to an RC circuit to provide automatic reset at power on. RESET output: Synchronized to Clk.

8 Clock Generator (8284): Signals RESET Signals #RES Reset input: Active low. Usually connected to an RC circuit to provide automatic reset at power on. RESET output: Synchronized to Clk. Connect to the 8086 RESET input. READY Signals #AEN1 and #AEN2 address enable inputs: Used with RDY1 and RDY2 inputs to generate the READY output. The READY output is connected to the READY input on the 8086/8088 µp to control memory wait states. #ASYNC input: for READY output synchronization. Selects 1 or 2 stages of synchronization for the RDY1 and RDY2 inputs. To µp

9 Functional Diagram of 8284

10 Typical Application of the 8284 for clock and Reset signal generation frequency, f f/3 Grounded when Xtal Osc is used R PCLK OSC f/6 f 2.5 MHz 15 MHz RESET Synced To CLK C RC circuit for automatic Reset on power up Manual Reset RC time constant large enough push button for 50 µs min Reset pulse Switch at worst trigger conditions 50 µs Minimum Effective Digital #RES Input

11 8086 Control Inputs From 8284 From 8284 VCC VCC GND GND GND GND Clock Reset MN/MX Ready Test Hold NMI INTR 8086

13 Demultiplexing A15,,A0 are multiplexed with Data lines D15,, D0. A19,, A16 are multiplexed with control signals. Addresses appear on the bus at T1 only and data appear on the bus from T2 to T4. Address can be demultiplexed by latching the address using a latch circuit.

14 74373 (Octal Latch)

15 74373 (Octal Latch)

16 Address and 8-Bit Data Bus

17 16-Bit Wide Memory 16-bit wide memory is organized in two separate 8-bit wide memory banks: - Low bank (even-numbered byte locations: 0, 2, 4, 6, ) low 8 bits of the data bus (D0-D7): LS By - High bank (odd-numbered byte locations: 1, 3, 5, 7, ) high 8 bits of the data bus (D8-D15): MS Byte Processor must be able to access any 16 or 8 bit locations Banks are selected by the microprocessor through bank selection (Bank Enable) signals On the 8086, these byte selection signals are - The #BLE (A0) signal selecting low bank - The #BHE signal selecting high bank

18 Address and 16-Bit Data Bus

20 = A0 Banks Bytes Words A19 A A Word address: A0 is Don t care (takes 0,1). Word address Starts with A1, with A0=0 Generally invalid for a word access. But if #BHE = 0, high byte is selected High Bank D15-D8 Word address: same 0 Invalid word access- Crossing word boundaries Same address from µp for Word or low byte. #BHE removes ambiguity Low Bank D7-D0 Blocks Enable with A0 (#BLE) Enable with #BHE High Byte Low Byte (MS Byte) (LS Byte)

21 80x86 Processor Data Bus Sizes Processor sx 80386dx class/ Pentium Data Bus Size

22 Address and 32-Bit Data Bus

PIN DIAGRAM. Richa Upadhyay Prabhu. NMIMS s MPSTME January 19, 2016

PIN DIAGRAM. Richa Upadhyay Prabhu. NMIMS s MPSTME January 19, 2016 PIN DIAGRAM Richa Upadhyay Prabhu NMIMS s MPSTME richa.upadhyay@nmims.edu January 19, 2016 Richa Upadhyay Prabhu (MPSTME) 8080 Microprocessor January 19, 2016 1 / 51 Pin Diagram of 8086 Richa Upadhyay