SAMPA DAQ-board Specification

Transcription

1 SAMPA DAQ-board Specification Arild Velure 1 January 26, Arild.Velure@cern.ch

2 Revision 0.1 Initial draft 0.2 Added user guide and developer guide, updated CnC registers, added DM registers, updated UART protocol 0.3 Added Linux and svn to development description, updated table 4.2 with new commands, added script patching to installation 1 of 18

3 Contents 1 User guide Installation and setup Prerequisites Installation of DAQ board Installation of SAMPA communicator program Installation of SAMPA analyzer Usage DAQ Board Usage of SAMPA communicator program Developers guide SVN structure Firmware development Structure of firmware tree Building Modifying modules Running simulations SAMPA communicator build SAMPA analyzer build SAMPA server build Linux Linux program development Interfaces UART Control Ethernet SSH HSMC connector to carrier board Misc interfaces Registers Command and control Data manager registers PLL registers of 18

4 Chapter 1 User guide This section describes the installation and use of the software and tools for the DAQ system. 1.1 Installation and setup The binaries can be located at Prerequisites Hardware needed: Altera/Arrow/Terasic SoCKit Evaluation Board (Terasic partnumber P0160) GB to 16 GB micro SD-card, if it is not provided with the SoCKit (bigger cards might work, but have not been verified) Software needed: Altera programmer (not needed if Quartus is installed) Altera Quartus (if any firmware development is to be done). Include "Quartus II software", "Cyclone V support" and "SoC Embedded Design Suite". The rest can be ignored. Free edition: Licensed edition: Mono (if using Linux) sudo apt-get install mono-complete libmon-system-windows-forms4.0-cil Win32DiskImager (if using Windows (dd replacement)) FTDI USB-UART driver (if it doesn t auto-install when plugged in) ROOT Data Analysis Framework Latest v5 build (Choose VC++ 10 (2010) MSI file at bottom of page for Windows pre-built files) Custom files and software needed: SAMPA_FPGA_test_board.jic Firmware for FPGA to be programmed with Altera programmer 3 of 18

5 SoCKit_SD.img Full image of SD card, includes Linux and bootloader SAMPA_communicator Configuration and control program for DAQ and SAMPA SAMPA_analyzer Root program for receiving data and analysis Update/patch files for SD image, if provided: SoCKit_bootloader.img Update of bootloader socfpga.dtb Device tree file, to be copied to readable partition on SD card zimage Linux kernel, to be copied to readable partition on SD card sampa_server Program running on DAQ that sends the data to the computer, to be stored in /sampa folder in Linux run_patch Patch script to be run on next boot (other files might accompany) Installation of DAQ board Install software before plugging in the hardware for the first time to avoid any issues with the drivers. Remember also to download the latest binaries for the system from Programming of the firmware for the FPGA: 1. Connect your computer to the SoCKit board by plugging the USB cable into the USB connector (J2) of SoCKit and power up the board. 2. Open the Quartus II programmer. 3. Click Hardware Setup. 4. If CV SoCkit [USB-1] does not appear under Currently Selected Hardware, select that option and click Close. If the CV SoCkit does not appear under hardware options list, please confirm if the driver has been correctly installed, and the USB cable has been properly connected between the SoCKit board and host computer and that the board is on. 5. Click Auto Detect and select the last option in the window that opens (5CSXFC6D6ES) 6. Select the 5CSXFC6D6ES in the list and click Change File to select the SAMPA_FPGA_test_board.jic file that you downloaded from the wiki and click Open. 7. Turn on the Program/Configure option that corresponds to the.jic file and click Start, which will automatically download the file into the SoCKit board. 8. After the downloading has been complete, turn the board off-and-on again and you should be able to see that by switching the rightmost switch on the board the corresponding led will also switch. Writing SD-card image to SD-card (Windows): 1. Connect the microsd card to the PC 2. Execute Win32DiskImager 3. Select the SoCKit_SD.img image file that you downloaded from the wiki 4. Select the microsd card device (check Windows Explorer if more than one device is selectable) 5. Click write to start writing the image file to the microsd card. Wait until the image is written successfully. Writing SD-card image to SD-card (Linux): 1. You need root privileges for the following 4 of 18

6 2. Navigate to the directory where the SoCKit_SD.img is located 3. Run "cat /proc/partitions" 4. Connect the microsd card to the PC 5. Run "cat /proc/partitions" again and look for the device that wasn t there before. We call it /dev/sdx here. 6. Run "dd if=sockit_sd.img of=/dev/sdx bs=512" 7. Run "sync" and the card can now be ejected Sometimes patches for the SD-card image will be distributed to avoid distributing the full image due to its size. 1. Write the SoCKit_bootloader.img to the SD-card in the same manner as explained above. 2. Mount the FAT partition on the card if on Linux or just open the disk if on Windows. 3. Copy the file socfpga.dtb, zimage, sampa_server, run_patch and others that are provided to the partition/disk with the normal copy procedure, overwriting the existing files. 4. Reinsert the SD-card in the board, the patch script will run on the next boot. More general help on setup and installation of the board can be found at and Guide.pdf Installation of SAMPA communicator program The SAMPA communicator handles the control and configuration of the DAQ-board and the SAMPA. The program is made in C#, but can be run in Linux through Mono without recompile. Windows does not need any installation unless the.net framework is missing aspx?id= To install Mono: 1. Run "apt-get install mono-complete libmon-system-windows-forms4.0-cil" 2. Check if you have access to serialports "ls -la /dev/ttys0;groups" 3. Run "sudo usermod -a -G GROUP_NAME MY_USER_NAME" 4. The program is run with "mono SAMPA_communicator.exe" Installation of SAMPA analyzer The SAMPA analyzer requires the ROOT Data Analysis Framework to run. Install version 5 and make sure ROOT is available in your path. On Linux run "make" in the project folder and the executable will be generated. The program is started with "sampa_analyzer ipaddress port threshold" where ipaddress and port is default and 1000 respectively and threshold is. 1.2 Usage DAQ Board Refer to figure 1.1 for the functionality of the different buttons, LEDs and connectors. Note that the board should be reset if you change from using an internal SAMPA and an external with the switch. 5 of 18

7 Programmer SerialCcom Ethernet ON/OFF CarrierCboardCconnection ResetCeverything ResetCLinuxCsystem DownC=CLinuxCterminalC-CUpC=CSAMPACcommunicatorC DownC=CExternalCSAMPAC-CUpC=CinternalCSAMPA Figure 1.1: Overview of DAQ board functionality Usage of SAMPA communicator program To use the program: 1. Connect the USB cable from the pc to the USB connector (J4) on the DAQ-board. 2. Wait until the drivers have installed and start the program. 3. Make sure the rightmost switch on the DAQ-board is up (led above is off) 4. Select the serialport to connect to in the drop-down list. The list only shows available connections and does a handshaking with the DAQ-board upon connection so there is no harm in trying the different ports until you find the right one. 5. When connected the bottom right text will read "Connection status: Open" 6. For editing the DAQ-board registers select the second tab and press the Read all button, this refreshes all register values in the program. 7. To change a value, edit the desired register and press Write changes. Only fields that have been edited will be updated. 8. For editing the SAMPA registers select the third tab. 9. Choose the desired ADC channel to change and click Read all. The chip id is the default unless this has been changed through the DAQ-board registers. 10. Apply the desired changes to the registers and press write changes. You can select broadcast to write the same value to all channels. 6 of 18

8 11. To change the PLL clock for the high-speed serial links and the SLVS/shiftregister test select tab four. 12. The changes are based on integer division of the VCO frequency of 320 MHz and are thus limited. Other VCO frequencies are possible by changing the input M nd N counters, but this would also possibly change the frequency of other clocks connected to the same PLL and should be verified in Qsys first. 7 of 18

9 (a) Select port used for DAQ-board (b) Read and write registers on DAQ-board, see chapter 4 (c) Read and write registers on SAMPA, see SAMPA specifications document (d) Change frequency of serial readout clock and SLVS/shiftregister clock Figure 1.2: SAMPA communicator interface 8 of 18

10 Chapter 2 Developers guide This section describes the building of the various software and firmware for the DAQ system. The code described can be browsed at or checked out with an svn client at Only source files are located in the repository. 2.1 SVN structure SAMPA digital docs testing FPGA Testboard Specifications SAMPA Specification MPW1 FPGA_interface_board SAMPA_emulator software SAMPA communicator SAMPA_analyzer SAMPA_server misc digital Contains the source and test code for the DSP of the SAMPA docs FPGA Testboard Specifications Contains the specification for the DAQ board docs SAMPA Specification MPW1 Contains the specification for the SAMPA digital part testing FPGA_interface_board Contains the firmware for the DAQ board testing SAMPA_emulator Contains the firmware for the SAMPA emulator which runs on a separate SoCKit and was used for testing before the SAMPA arrived testing software SAMPA communicator Contains the source for the SAMPA communicator testing software SAMPA_analyzer Contains the source for the SAMPA analyzer testing software SAMPA_server Contains the source for the SAMPA server 9 of 18

11 testing software misc Contains standalone example code for the communicator and server in C. In addition there is a SAMPA emulator program which generates data equivalent to what you would get from the DAQ board, but can be run locally on the computer and used for testing the analyzer. 2.2 Firmware development This section demonstrates how to compile the FPGA Hardware design for the DAQ-board. It requires Quartus and SOC Embedded Design Suite Structure of firmware tree.qpf Quartus project file.qsf Quartus settings file (pin constraints etc.).sdf Clock constraint file.tcl Module descriptions for use in Qsys hps.qsys Qsys system convert_to_jic.cof "Convert programming file" setup file soc_system_board_info.xml Additional settings to be added to devicetree SoCKit_bootloader.img Bootloader part of SD-card image update_preloader.sh Shell script for generating devicetree, preloader and uboot and store in SoCKit_bootloader.img update_preloader.bat Script for setting up paths before starting shell script above build.bat Script to run unattended compile program.bat Script to run conversion of sof-to-jic and programming automatically hdl Source files for modules hdl/tb Testbench for modules for use with questasim ip Ip modules from either Altera or other sources Building A more thorough description with pictures can be found at GSRD131CompileHardwareDesign. The build can be run unattended from the build.bat script, but at the moment this script takes an hour longer to compile as the flow is run multiple times to improve timing. 1. Launch Quartus and select File Open 2. Navigate to the project directory and open the SAMPA_FPGA_test_board.qpf file 3. Go to Tools Qsys to stat the Qsys tool 4. Select the hps.qsys file in the project root and click open 5. In Qsys select Generate Generate HDL 6. The configuration in the window that appears should look like figure Click Generate and a message window will appear 8. Once it says "Generate: completed with warnings" press close, you can also close Qsys now 9. In the task panel on the bottom left, change the flow from RTL simulation to Compile 10. In the task panel right-click Assembler and select Start 11. Once the process is complete select File Convert Programming Files 10 of 18

12 12. Click Open Conversion Setup Data and select the file convert_to_jic.cof 13. Click generate and close window when it is finished 14. Navigate to the project folder and run update_preloader.bat 15. When the script is done you should have available in the project folder socfpga.dtb Devicetree file which needs to be copied to the small readable partition on the SD-card An updated SoCKit_bootloader.img Which needs to be copied to the SD-card with Win32DiskImager or dd SAMPA_FPGA_test_board.jic Which needs to be programmed to the FPGA Figure 2.1: Generation of output files from Qsys Modifying modules In case any of the modules are changed an extra step is needed in the build process before selecting generate in Qsys 1. Right click the module that has been updated in the IP catalog on the left side and select Edit 2. Select the Files tab and click Analyze Synthesis Files 3. Close the window when it is complete and select finish. Select yes to save. 4. Select File Refresh System 5. Continue with the generation of the Qsys system Running simulations The simulations can not be done with the free version of Modelsim as it doesn t support simulation of both verilog and VHDL files at the same time. There are two sets of testbenches for the project, tb_cnc.vhd which tests the cnc and dm modules without them being connected to the bus and the tb_bus_test.vhd which connects the modules to a Bus Functional Module and includes the uart2bus module. The second option is 11 of 18

13 much slower to simulate and the configuration has to go through the uart which is also slow. The configuration of the bus system can be done with the bus_system.qsys Qsys project. To run the simulations run in the Modelsim command line "do run_sim_cnc.tcl" for the simulation without bus or "do run_sim_bus_test.tcl" for the one with bus support. 2.3 SAMPA communicator build The SAMPA communicator program can be built with either Visual Studio 2010 Express (free) or with Mono IDE. The project can be compiled like regular C# projects. Open the SAMPA_communicator.sln project file and select Build Build Sollution. The low-level functions for communicating with the DAQboard is contained in daq_write(address, data) and in daq_read(address, data) and the other functions are built upon these for communicating with the SAMPA, CNC, DM or PLL. 2.4 SAMPA analyzer build The SAMPA analyzer can be compiled on Linux by running "make" in the project folder. On Windows it s easiest to compile with the provided Visual C project. Just open the SAMPA_analyzer.sln project file and right-clicking the solution and selecting Build. 2.5 SAMPA server build The SAMPA server requires either the Linaro ARM toolchain installed (gcc-linaro-arm-linux-gnueabihf ) (with Cygwin for Windows) or just the Altera SOC Embedded Design Suite. Open the SOC Embedded Design Suite command shell and navigate to the project directory and run make. Transfer the sampa_server file to the DAQ-board through SFTP as explained earlier. 2.6 Linux The Linux system is based on the Yocto source package AYoctoUserManualDanny and the build description can be found at Documentation/AlteraSoCDevelopmentBoardYoctoGettingStarted. But the system has not yet been updated and is the same as provided by Terasic as there was no reason to do a rebuild. The kernel has been upgraded to 3.15 (rel_socfpga-3.15_ ) as that was the latest that supported the Altera FPGA bridge module at the time A startup init script can be found at /etc/init.d/sampa_server which starts the sampa_server and runs the patch job if it exists Linux program development To avoid copying over the SAMPA_server to the DAQ board for each recompile during development it is possible to set up a NFS mount point on the Linux system pointing to a folder on your local computer. For Linux on the local computer follow a tutorial like client_on_debian_wheezy to set up the nfs server. For Windows the only free nfs server is freenfse http: //sourceforge.net/projects/freenfs/files/current\%20version/embedded\%20system\%20version/ though it has a problem that it is not possible to browse the share from the DAQ board, but it is possible to read, write and execute files. For the DAQ bard, login to the Linux system and run mkdir /mnt/nfs;mount -t nfs -o nfsvers=3,nolock,rsize= :/ /mnt/nfs 12 of 18

14 Chapter 3 Interfaces This section describes the protocols and properties of the various interfaces for the FPGA testboard. 3.1 UART Control The FPGA testboard is currently controlled through UART communication. The testboard has a chip that provides a virtual UART over USB and it is connected to the usb port closest to the Ethernet port. Drivers are available from if they do not autoinstall. The settings for the UART port is: baud 8 bits 1 stop bits no parity no flow-control Since the board only has one UART, a switch has been configured for switching between talking to the internal bus or the Linux system. By pulling SW 0 down the UART will be connected to the Linux system, this also turns on LED 0. Pulling the switch up connects the UART to the internal bus needed for use with the "SAMPA communicator" program. To read from the bus system over the UART Send CMD_READ ( CMD_ACK)* ADDH ADDL Receive DATAHH DATAHL DATALH DATALL ACK* Figure 3.1: Format of UART read. See table 3.1 for CMD values. *The presence of the ACK is dependent on if the CMD_ACK is given. 3.2 Ethernet The DAQ-board is equipped with a gigabit Ethernet interface. It has reliably tested to work at a maximum DAQ PC speed of 670 Mbps with TCP and 690 Mbps with 1% packet loss/out of order packets for UDP. 13 of 18

15 Command Value Description CMD_NOP 0x00 No OPeration command, send ACK if requested CMD_READ 0x10 Read command CMD_WRITE 0x20 Write command CMD_ACK 0x01 Send ACK (0x5a) at end of response Table 3.1: CMD table for UART. Send CMD_WRITE ( CMD_ACK)* ADDH ADDL DATAHH DATAHL DATALH DATALL Receive 0 7 ACK* Figure 3.2: Format of UART write. See table 3.1 for CMD values. *The presence of the ACK is dependent on if the CMD_ACK is given. The interface has link-auto-negotiation and can thus work with a direct cable connection from computer to DAQ without any switch in between. The DAQ is configured to fetch an IP from the DHCP server upon bootup. If no DHCP server is found it resorts to the default IP-address of The default address can be changed by editing the /etc/networking/interfaces file on the DAQ system. The DAQ listens for connections on port 1000 and starts sending data once a connection is established. If needed the port can be changed by changing the OPTS value in the /etc/init.d/sampa_server script SSH The Linux system runs an SSH server on port 22 which is useful for uploading new files to the system through SFTP. Files should be kept in the /sampa folder. You can log in with root with no password. 3.3 HSMC connector to carrier board See table 3.2 for pin connections to the carrier boards. 3.4 Misc interfaces 14 of 18

16 FPGA pin DSP board ADC board Org. pin name HSMC pin HSMC pin Org. pin name ADC board DSP board FPGA pin PIN_H4 XCVR_TXp7 1 2 XCVR_RXp7 PIN_J2 PIN_H3 XCVR_TXn7 3 4 XCVR_RXn7 PIN_J1 PIN_M4 XCVR_TXp6 5 6 XCVR_RXp6 PIN_N2 PIN_M3 XCVR_TXn6 7 8 XCVR_RXn6 PIN_N1 PIN_P4 XCVR_TXp XCVR_RXp5 PIN_R2 PIN_P3 XCVR_TXn XCVR_RXn5 PIN_R1 PIN_T4 XCVR_TXp XCVR_RXp4 PIN_U2 PIN_T3 XCVR_TXn XCVR_RXn4 PIN_U1 PIN_V4 XCVR_TXp XCVR_RXp3 PIN_W2 PIN_V3 XCVR_TXn XCVR_RXn3 PIN_W1 PIN_Y4 XCVR_TXp XCVR_RXp2 PIN_AA2 PIN_Y3 XCVR_TXn XCVR_RXn2 PIN_AA1 PIN_AB4 XCVR_TXp XCVR_RXp1 PIN_AC2 PIN_AB3 XCVR_TXn XCVR_RXn1 PIN_AC1 PIN_AD4 XCVR_TXp XCVR_RXp0 PIN_AE2 PIN_AD3 XCVR_TXn XCVR_RXn0 PIN_AE1 PIN_AE29 SDA SCL PIN_AA28 JTAG_TCK JTAG_TMS JTAG_TDO JTAG_TDI PIN_AD29 CLKOUT CLKIN0 ADC_CLK clk10in PIN_J14 PIN_C10 header0 B0 D D1 B1 header1 PIN_H13 PIN_C9 header2 B2 D D3 B3 header3 PIN_H12 3.3v v PIN_A9 header4 B4 LVDS_TXp LVDS_RXp0 B5 header5 PIN_G12 PIN_A8 header6 B6 LVDS_TXn LVDS_RXn0 B7 header7 PIN_G11 3.3v v PIN_E8 header8 B8 LVDS_TXp LVDS_RXp1 B9 header9 PIN_K12 PIN_D7 ADCnDSP ADCnDSP LVDS_TXn LVDS_RXn1 EOC PIN_J12 3.3v v PIN_G7 MPW1_dout[0] LVDS_TXp LVDS_RXp2 MPW1_dout[1] PIN_G10 PIN_F6 MPW1_dout[2] LVDS_TXn LVDS_RXn2 MPW1_dout[3] PIN_F10 3.3v v PIN_D6 MPW1_dout[4] LVDS_TXp LVDS_RXp3 MPW1_dout[5] PIN_J10 PIN_C5 MPW1_dout[6] LVDS_TXn LVDS_RXn3 MPW1_dout[7] PIN_J9 3.3v v PIN_D5 MPW1_dout[8] LVDS_TXp LVDS_RXp4 MPW1_dout[9] PIN_K7 PIN_C4 MPW1_dout[10] LVDS_TXn LVDS_RXn4 MPW1_dout[11] PIN_K8 3.3v v PIN_E3 MPW1_dout[12] LVDS_TXp LVDS_RXp5 MPW1_selectIn PIN_J7 PIN_E2 MPW1_selectOut[0] LVDS_TXn LVDS_RXn5 MPW1_selectOut[1] PIN_H7 3.3v v PIN_E4 MPW1_selectOut[2] LVDS_TXp LVDS_RXp6 MPW1_enBC1 PIN_H8 PIN_D4 MPW1_enBC2 LVDS_TXn LVDS_RXn6 MPW1_enZSU PIN_G8 3.3v v PIN_C3 MPW1_dinOUTSIDE[0] LVDS_TXp LVDS_RXp7 MPW1_dinOUTSIDE[1] PIN_F9 PIN_B3 MPW1_dinOUTSIDE[2] LVDS_TXn LVDS_RXn7 MPW1_dinOUTSIDE[3] PIN_F8 3.3v v PIN_E7 MPW1_dinOUTSIDE[4] CLKOUT1p CLKIN1p MPW1_dinOUTSIDE[5] PIN_AA26 PIN_E6 MPW1_dinOUTSIDE[6] CLKOUT1n CLKIN1n MPW1_dinOUTSIDE[7] PIN_AB27 3.3v v PIN_E1 MPW1_dinOUTSIDE[8] LVDS_TXp LVDS_RXp8 MPW1_dinOUTSIDE[9] PIN_F11 PIN_D1 MPW1_numSerialOUT[0] LVDS_TXn LVDS_RXn8 MPW1_numSerialOUT[1] PIN_E11 3.3v v PIN_D2 MPW1_enTCFU LVDS_TXp LVDS_RXp9 serialout0_p PIN_B6 PIN_C2 LVDS_TXn LVDS_RXn9 serialout0_n PIN_B5 3.3v v PIN_B2 clk40in_p LVDS_TXp LVDS_RXp10 serialout1_p PIN_E9 PIN_B1 clk40in_n LVDS_TXn LVDS_RXn10 serialout1_n PIN_D9 3.3v v PIN_A4 clk320in_p LVDS_TXp LVDS_RXp11 serialout2_p PIN_E12 PIN_A3 clk320in_n LVDS_TXn LVDS_RXn11 serialout2_n PIN_D12 3.3v v PIN_A6 instr_serial_in LVDS_TXp LVDS_RXp12 serialout3_p PIN_D11 PIN_A5 instr_serial_out LVDS_TXn LVDS_RXn12 serialout3_n PIN_D10 3.3v v PIN_C7 hadd[0] LVDS_TXp LVDS_RXp13 trg PIN_C13 PIN_B7 hadd[1] LVDS_TXn LVDS_RXn13 hb_trg PIN_B12 3.3v v PIN_C8 hadd[2] LVDS_TXp LVDS_RXp14 Hrstb PIN_F13 PIN_B8 hadd[3] LVDS_TXn LVDS_RXn14 sync PIN_E13 3.3v v PIN_C12 si_p LVDS_TXp LVDS_RXp15 so_p PIN_H14 PIN_B11 si_n LVDS_TXn LVDS_RXn15 so_n PIN_G13 3.3v v PIN_B13 clk_p LVDS_TXp LVDS_RXp16 ext_trigger ext_trigger PIN_F15 PIN_A13 clk_n LVDS_TXn LVDS_RXn16 PIN_F14 3.3v v PIN_A11 IP_RX_EXT CLKOUT2p CLKIN2p OUTP_TX_EXT PIN_H15 PIN_A10 IN_RX_EXT CLKOUT2n CLKIN2n OUTN_TX_EXT PIN_G15 3.3v PSNTn(1) GND GND GND GND GND GND GND GND GND GND GND GND Table 3.2: HSMC connector pinout 15 of 18

17 Chapter 4 Registers 4.1 Command and control The registers for the command and control module, located at address 0x0000 from the UART or 0xFF from the HPS, is listed in table Data manager registers The registers for the data manager module, located at address 0x0040 from the UART or 0xFF from the HPS, is listed in table PLL registers The registers for the PLL reconfiguration module, located at address 0x0080 from the UART or 0xFF from the HPS, is given in It is recommended to use the calculator at to figure out the register values needed. 16 of 18

18 Register name Address Type Default Description SC_ADD [15:0] 0x00 RW 0x00 [4:0] Slow control: Register address RW 0x00 [9:5] Slow control: Channel address RW 0x00 [13:10] Slow control: Chip address RW 0x00 [14] Slow control: Broadcast RW 0x00 [15] Slow control: Write/ not read SC_DAT [19:0] 0x01 RW 0x00 [19:0] Slow control: Data to write SC_MASK [19:0] 0x02 RW 0x00 [19:0] Slow control: Mask for writing * CMD [31:0] 0x03 RW 0x00 [15:0] Commands, see table 4.2 RW 0x00 [31:15] Loop count for commands SC_RLT [19:0] 0x04 R 0x00 [12:0] Slow control: Response from SAMPA SC_ERR [1:0] 0x05 R 0x00 [0] Error: Timeout waiting for response from slow control R 0x00 [1] Error: Response from SAMPA not as expected LNK_STS [31:0] 0x06 R 0x00 [31:0] Ethernet link status * EVT_CFG [31:0] 0x07 RW 0x01 [1:0] Test signal output, see table 4.3 RW 0x00 [2] Enable SLVS testing RW 0x00 [3] Enable continuous readout of shiftregister RW 0x00 [31:3] Reserved * EVT_CNT [31:0] 0x08 R 0x00 [31:0] Reserved * EV_BL [31:0] 0x09 R 0x00 [31:0] Reserved * SMP_STS1 [30:0] 0x0A R Status of signals to and from SAMPA (updated every clock cycle) R [12:0] Test data output from SAMPA R [16:13] Serial out [3:0] R [18:17] Number of serial out R [19] Enable ZSU R [20] Enable BC2 R [21] Enable TCFU (deprecated) R [22] Enable BC1 R [25:23] Select test output R [26] Select ADC0 or test input R [30:27] Chip address SMP_STS2 [5:0] 0x0B R Status of signals to and from SAMPA cont. R [0] Slow control to SAMPA R [1] Slow control from SAMPA R [2] Reset_n R [3] Event trigger R [4] Heartbeat trigger R [5] Sync signal SMP_CFG [13:0] 0x0C RW SAMPA static signals, see SAMPA spec document for further details RW 0x02 [1:0] Number of serial out RW 0x00 [2] Enable ZSU RW 0x00 [3] Enable BC2 RW 0x01 [4] Enable TCFU RW 0x01 [5] Enable BC1 RW 0x03 [8:6] Select test output RW 0x01 [9] Select ADC0 or test input RW 0x01 [13:10] Chip address SLVS_ERR [15:0] 0x0D R 0x00 SLVS errors detected RAD_ERR [31:0] 0x0E R Errors detected in shiftregister test R 0x00 [15:0] Bit 0 errors R 0x00 [31:16] Bit 1 errors VER [31:0] 0x0F R SVN version build was based on in dec Table 4.1: Command and control registers. * Functionality not implemented 17 of 18

19 Value 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 Description Reset FPGA and SAMPA Reset SAMPA Send event trigger Send heartbeat trigger Send sync signal Run readout of shiftregister once (RAD) Reset errors in shiftregister count (RAD_ERR) Execute slow control command Reset HPS Table 4.2: Commands for command and control unit. Value 0x0 0x1 0x2 0x3 Description Constant zeros Sine wave, full wave, 512 samples pulse width Saw wave, full wave, 512 samples pulse width Triangle wave, full wave, 1024 samples pulse width Table 4.3: Test signals available for generation. Register name Address Type Default Description CNTRL [31:0] 0x00 RW 0x00 Control register RW 0x00 [0] Enable acquisition serial link 0 RW 0x00 [1] Enable acquisition serial link 1 RW 0x00 [2] Enable acquisition serial link 2 RW 0x00 [3] Enable acquisition mux output/adc RW 0x00 [4] Acquire data (one shot) RW 0x00 [15:5] Reserved RW 0x00 [31:16] Number of packets to acquire PKT0 [31:0] 0x01 R 0x00 [31:0] Packets written to memory from channel 0 PKT1 [31:0] 0x02 R 0x00 [31:0] Packets written to memory from channel 1 PKT2 [31:0] 0x03 R 0x00 [31:0] Packets written to memory from channel 2 PKT3 [31:0] 0x04 R 0x00 [31:0] Packets written to memory from test-input/adc FIFO0 [8:0] 0x05 R 0x00 [8:0] Number of 64 bit words in FIFO 0 FIFO1 [8:0] 0x06 R 0x00 [8:0] Number of 64 bit words in FIFO 1 FIFO2 [8:0] 0x07 R 0x00 [8:0] Number of 64 bit words in FIFO 2 FIFO3 [8:0] 0x08 R 0x00 [8:0] Number of 64 bit words in FIFO 3 HPS [31:0] 0x09 R Control register for sampa_server R 0x00 [0] Client connected (acquisition can start) R 0x00 [7:1] Reserved R [15:8] Version of sampa_server program ADC_STS [16:0] 0x0A R Status of ADC signals R [9:0] Status of ADC data pins R 0x00 [15:10] Reserved R [16] Status of ADCnDSP pin R 0x00 [17] Serial link 0 is acquiring R 0x00 [18] Serial link 1 is acquiring R 0x00 [19] Serial link 2 is acquiring R 0x00 [20] Mux output/adc is acquiring Table 4.4: Data manager registers. 18 of 18