Engr 303 Digital Logic Design Fall 2018

Transcription

1 Engr 303 Digital Logic Design Fall 2018 LAB 14 Single Cycle Computer You will implement the single cycle computer given in Figure 8-15 of the Chapter 8 handout. Implement these designs, compile, simulate, assign pins, download to hardware and test. Include all the design files and waveforms in your final report. Deliverables: 0) Instruction Memory 1) Single Cycle Computer Demonstration Requirement: Demonstrate Part 1, the final computer executing the given multiplication algorithm on the DE2 board. Part 0 Instruction Memory Implement the Instruction Memory verilog module shown below. This module outputs an instruction on IR bus for each corresponding Address input from the Program Counter (PC). This particular module simulates an assembly language program to perform multiplication. In a real system, such a program would be stored in RAM. Here, we are using verilog to implement the instruction memory as "hard-wired" gates. We would have to recompile the module to run a different "simulated assembly langauge" program. // A simulated assembly language program implemented as a hard-wired circuit. module InstructionMemory ( Address, IR ); input [7:0] Address; output [15:0] IR; reg [15:0] IR; // parameters rename things for readability // this makes it easier to write new programs parameter // See p469 // Register Instructions, Opcode, DR, SA, SB MOVA = 7'b , INC = 7'b , ADD = 7'b , SUB = 7'b , DEC = 7'b , AND = 7'b , OR = 7'b , XOR = 7'b , NOT = 7'b , MOVB = 7'b , SFTR = 7'b , SFTL = 7'b , LOAD = 7'b , ST = 7'b , // Immediate Instructions, Opcode, DR, SA, OP LDI = 7'b , Engineering 303 Lab 14 Folsom Lake College Page 1 of 8

2 ADI = 7'b , // Jump Branch Instructions, Opcode, AD, SA, AD BRZ = 7'b , BRN = 7'b , JMP = 7'b , // Registers R0 = 3'b000, R1 = 3'b001, R2 = 3'b010, R3 = 3'b011, // Numbers ZERO = 3'b000, ONE = 3'b001, TWO = 3'b010, THREE = 3'b011, FOUR = 3'b100, // NULL NULL = 3'b000; // The actual simulated assembly language "program" starts here // This program multiplies two given inputs A * B = P always@(address) begin case(address) 0: IR <= {LOAD, R0, NULL, NULL}; // load A 1: IR <= {LOAD, R1, NULL, NULL}; // load B 2: IR <= {LDI, R2, NULL, ZERO}; // set P to 0 3: IR <= {LDI, R3, NULL, FOUR}; // load jump address // Loop // if A = 0 then branch to done (binary 8) 4: IR <= {BRZ, 3'b001, R0, 3'b000}; 5: IR <= {ADD, R2, R2, R1}; // add B to P 6: IR <= {DEC, R0, R0, NULL}; // decrement A 7: IR <= {JMP, NULL, R3, NULL}; // jump to loop // Done 8: IR <= {ST, NULL, NULL, R2}; // output answer default IR <= 255; endcase end endmodule Waveform Testing. Use Table 8-8 and Figure 8-14 from the Chapter 8 handout to check the instructions. The first few are Load to R0, Load to R1, LoadImmediate the value 0 to R2, LoadImmediate the value 4 to R3... and so forth. You need to check the rest against the instruction memory "program". ENGR303 Engineering 303 Lab 14 Folsom Lake College Page 2 of 8

3 Part 1 Single Cycle Computer Implement the Single Cycle computer design shown at the end of this document. There will be no Data Memory. Instead, connect the signals that would go to the memory module to switches and LEDs instead. These signals will be our primary interface to the system. But we need more signals for testing. Because this is a complex design, we need to pull out some of the internal signals to verify that the system is functioning properly while testing. We call these testing signals "hooks". Pull out the signals using the following pin assignments: Signal Name BusA BusASS BusB BusBSS BusD BusDSS PCout PCoutSS IR K1 K0 MW DataIn ResetN Clock DE2 Connection none 2 seven segment displays HEX1 PIN_AB24,_AA23,_AA24,_Y22,_W21,_V21,_V20 HEX0 PIN_V13,_V14,_AE11,_AD11,_AC12,_AB12,_AF10 None 2 seven segment displays HEX3 PIN_W24,_U22,_Y25,_Y26,_AA26,_AA25,_Y23 HEX2 PIN_Y24,_AB25,_AB26,_AC26,_AC25,_V22,_AB23 None 2 seven segment displays HEX5 PIN_R3,_R4,_R5,_T9,_P7,_P6,_T2 HEX4 PIN_T3,_R6,_R7,_T4,_U2,_U1,_U9 None 2 seven segment displays HEX7 PIN_N9,_P9,_L7,_L6,_L9,_L2,_L3 HEX6 PIN_M4,_M5,_M3,M2,_P3,_P4,_R2 RED LEDs 15:0 _PIN_AE13,_AF13,_AE15,_AD15,_AC14,_AA13,_Y13,_AA14, _AC21, _AD21, _AD23, _AD22, _AC22, _AB21, _AF23, _AE23 GREEN LED 3 - PIN_V18 GREEN LED 2 PIN_W19 GREEN LED 0 PIN_AE22 Toggle switches 7:0 - PIN_C13, _AC13, _AD13, _AF14, _AE14, _P25, _N26, _N25 BLUE button 1 PIN_N23 BLUE button 0 PIN_G26 Waveform Testing 2 x 2 = 4. 2 times 2 is 4. The answer (4) shows up on the B bus and is indicated by MW going high. MS goes high for the STORE operation which would write the answer to Data Memory if we had one. Don't forget to make ResetN high or nothing will happen. The seven seg signals are not helpful for the simulation, but are VERY helpful for running on the DE2 board. Engineering 303 Lab 14 Folsom Lake College Page 3 of 8

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5 Single Cycle Computer (see detail the following views, as well as Mano text Figures 8-14, 8-15, 8-16) Engineering 303 Lab 14 Folsom Lake College Page 5 of 8

6 Single Cycle Computer Detail 1 Engineering 303 Lab 14 Folsom Lake College Page 6 of 8

7 Single Cycle Computer Detail 2 Engineering 303 Lab 14 Folsom Lake College Page 7 of 8

8 Single Cycle Computer Detail 3 Engineering 303 Lab 14 Folsom Lake College Page 8 of 8