MPLEMENTATION. Part 1: Implementation of the TOC on the DE2 Board using Verilog - Performed in Lab #1

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1 ERILOG ESCRIPTION AND MPLEMENTATION OF THE ASIC Part 1: Implementation of the TOC on the DE2 Board using Verilog - Performed in Lab #1 Part 2: Extend the TOC to Achieve a 4-Bit Processor - Done in Other Parts of Course (If Time Permits) 1

2 2

3 BLOCK DIAGRAM OF THE BASIC TOC 7-SEG DISPLAY REGR Switches for Control ALU REGA REGB Clock Switches for Data 3

4 DE2 IMPLEMENTATION OF THE BASIC TOC DE2-115 Board Inside FPGA 7-SEG DISPLAY REGR ALU Switches for Control LEDs for Unit Testing REGA REGB Clock Switches for Data 4

5 HE LAN Incrementally develop the Basic TOC Implemented in Laboratory 1 Following additions (in Lectures) will be added if time permits Add Accumulator Functionality Add Multiplexers and Memory Add Address Generator Unit Add Computer Control Unit (CCU) 5

6 ULTIMATE OBJECTIVE: A BASIC 8-BIT PROCESSOR IMPLEMENTED ON THE DE2 BOARD 6

7 LTERA S OARD 7

8 VERVIEW OF ESIGN FPGA Chip 8 7-Segments (HEX) Red LEDs Green LEDs 18 Slider Switches (SW[17:0]) 4 Push Buttons (KEY[3:0]) 8

9 TANDARD WITCH AMES 18 Slider Switches SW (Vector Name) SW[17], SW[16], SW[0] (Component Names) 4 Push Button Switches KEY (Vector Name) KEY[3], KEY[2], KEY[1], KEY[0] (Component Names) 18 Slider Switches (SW[17:0]) 4 Push Buttons (KEY[3:0]) 9

10 TANDARD AMES 18 Red, Light Emitting Diodes (LEDs) LEDR (Vector Name) LEDR[17], LEDR[16], LEDR[0] (Component Names) 8 Green, Light Emitting Diodes (LEDs) LEDG (Vector Name) LEDG[7], LEDG[6], LEDG[0] (Component Names) Red LEDs Green LEDs 10

of Digit n) HEXn[5] (5-segment of Digit n) HEXn[6] (6-segment of Digit n) HEXn[7] (Dec.

11 STANDARD HEXADECIMAL DISPLAY NAMES Eight 7-Segment Hexadecimal Display Digits HEX7, HEX6, HEX5,, HEX1, HEX0 (Vector Names) HEXn[0] (0-segment of Digit n) HEXn[1] (1-segment of Digit n) HEXn[2] (2-segment of Digit n) HEXn[3] (3-segment of Digit n) HEXn[4] (4-segment of Digit n) HEXn[5] (5-segment of Digit n) HEXn[6] (6-segment of Digit n) HEXn[7] (Dec. Point of Digit n) n = 0, 1,, 7; the Hexadecimal digit. Eight, 7-Segments Display Units Applying a low logic level to a segment will light it up and applying a high logic level turns it off. 11

12 IN ONNECTIONS Each peripheral has been pre-wired to specific pins of the FPGA chip Slider Switches SW[17], SW[16], SW[0] (PIN_Y23, PIN_AB28) Push Button Switches KEY[3], KEY[2], KEY[1], KEY[0] (PIN_R24,, PIN_M23) Red LEDs LEDR[17], LEDR[16], LEDR [0] (PIN_H15,, PIN_G19) Green LEDs LEDG[17], LEDG[16], LEDG [0] (PIN_F17,, PIN_E21) HEX Digits HEX0[6], HEX0[5], HEX0 [0] (PIN_H22,, PIN_G18) 12

13 IN SSIGNMENT Within the Quartus software, your Verilog programs may refer to the peripherals (such as the switches, LEDs, and 7-segments) directly by using their pin names. For example, the following is a Verilog statement that connects a wire named switch_0_wire to the pin that is connected to switch 0: assign switch_0_wire = PIN_AB28 Alternatively, you can refer to a peripheral using its standard name: For example: assign switch_0_wire = SW[0] But, you need to assign the pin numbers to the standard names before you can do this. This procedure is called pin assignment. The pin assignment procedure requires a pin-assignment file. Pin number to pin name assignment in file DE2_115.qsf 13

14 IN SSIGNMENT ILE Conveniently, Quartus provides a pin assignment file. It is called DE2_115.qsf Note that a different pin assignment file is provided for each different FPGA chip that is used in a particular DE2-115 board. You must ensure that the pin assignment file is the correct one for your board Go to: On this page ensure the FPGA part number is the same part number as the one on your DE2-115 board. It should be: Cyclone IV EP4CE115F29C7 Select and download the Quartus Setting File with Pin Assignments QSF file. 14

15 DE2-115 WEB SITE Ensure the FPGA part number is: Cyclone IV EP4CE115F29C7 Download the pin assignment file. 15

16 PIN ASSIGNMENT FILE LED pin assignments, etc. 16

MAKING THE PIN ASSIGNMENT IN QUARTUS Pin specification file may be imported into the Quartus II software When you have your project open, then you may assign the standard names of the

17 MAKING THE PIN ASSIGNMENT IN QUARTUS Pin specification file may be imported into the Quartus II software When you have your project open, then you may assign the standard names of the peripherals to pins on the FPGA. Your hardware description can use these names to interface to the peripherals. NOTE: you must import the pin assignments file for each new project you create. 17

18 INCREMENTAL DEVELOPMENT PROCEDURE We will practice the incremental development procedure. Split the Data Path Unit of the TOC into a number of subcircuits. Implement the TOC in an incremental fashion: Add the first component and test it Add the second component and test both of them Add the next component and test each one added to this point. Add the last component and perform a system test by testing all components. 18

19 TOC DIVISION SPLITTING THE TOC INTO FIVE INCREMENTAL DEVELOPMENT PHASES Five incremental phases Phase 1 REGA (Test Register A, output to LEDs) Phase 2 REGA and REGB (Test Registers A and B, output to LEDs) Phase 3 ALU (Test ALU with the Registers A and B, output to LEDs) Phase 4 REGR (Test Registers R with ALU, REGA, and REGB, output to LEDs) Phase 5 7-Segment Display (Test 7-Segment Display with REGR, ALU, REGA, and REGB, output to Hex display) 19

20 PHASE 1: REGA UNIT TESTING Red LEDs REGA A_R/Wn CLKn Switches for Control Slider/PB Switches DBUS Slider Switches Switches for Data 20

21 PHASE 2: REGA AND REGB UNIT TESTING Red LEDs Red LEDs REGA A_R/Wn CLKn REGB B_R/Wn CLKn DBUS Slider Switches Switches for Data 21

22 PHASE 3: REGA, REGB, & ALU UNIT TESTING Red LEDs ALU M S 3 S 2 S 1 S 0 Slider Switches Red LEDs Red LEDs REGA A_R/Wn CLKn REGB B_R/Wn CLKn DBUS Slider Switches Switches for Data 22

23 PHASE 4: REGA, REGB, ALU, & REGR UNIT TESTING Red LEDs REGR R_R/Wn CLK Red LEDs ALU M S 3 S 2 S 1 S 0 Slider Switches Red LEDs Red LEDs REGA A_R/Wn CLKn REGB B_R/Wn CLKn DBUS Slider Switches Switches for Data 23

24 PHASE 5: ALL COMPONENTS SYSTEM TESTING Red LEDs REGR 7-Segment Display CLK Red LEDs ALU M S 3 S 2 S 1 S 0 Slider Switches Red LEDs Red LEDs REGA A_R/Wn CLKn REGB B_R/Wn CLKn DBUS Slider Switches Switches for Data 24

25 PHASE 1: REGA UNIT TEST BLOCK DIAGRAM FPGA Wires RegAWn Wn Q3 D3 RegAQ[3] RegAQ[2] RegAQ[1] RegAQ[0] Q2 D2 Q1 RegA D1 Q0 D0 DBUS Clock Clockn LEDR[3] LEDR[2] LEDR[1] LEDR[0] RED LEDS DE2 Board Component SW[4] SW[3] SW[2] SW[1] SW[0] KEY0 Clock Assigned Names to FPGA Pins Slider Switches Push Button Switch DE2 Board Components 25

7-SEGMENT DISPLAY UNIT TESTING Switches SW[0] SW[1] SW[2] SW[3] SW[4] SW[5] SW[6] justwires[0] justwires[1] justwires[2] justwires[3] justwires[4] justwires[5] justwires[6]

26 7-SEGMENT DISPLAY UNIT TESTING Switches SW[0] SW[1] SW[2] SW[3] SW[4] SW[5] SW[6] justwires[0] justwires[1] justwires[2] justwires[3] justwires[4] justwires[5] justwires[6] HEX0[0] HEX0[1] HEX0[2] HEX0[3] HEX0[4] HEX0[5] HEX0[6] module SevenSegmentUnitTest (SW, HEX0); input [6:0] SW; output [6:0] HEX0; wire [6:0] justwires; assign justwires[6:0] = SW[6:0]; assign HEX0[6:0] = justwires[6:0]; endmodule The segments are active low, i.e., when the slider switch (SW) is in the bottom position (SW=0), the LED segment shines, and when the slider switch (SW) is in the top position (SW=1), the LED segment is dark. Found that the decimal pint (DP) pin is not specified in the pin assignment file DE2_115.qsf. 26

27 VERILOG DESCRIPTION OF REGAUNIT TEST BLOCK Top-level Module DIAGRAM: MODULAR Note: top level module FILE: TOC_REGA.v name is the same as the file name prefix. module TOC_REGA (SW, KEY, LEDR); input [4:0] SW; input [0:0] KEY; output [3:0] LEDR; wire [3:0] DBUS, RegAQ; wire RegAWn, Clock, Clockn; assign LEDR [3:0] = RegAQ [3:0]; assign Clock = KEY[0]; assign Clockn = ~Clock; assign RegAWn = SW[4]; assign DBUS[3] = SW[3], DBUS[2] = SW[2]; assign DBUS[1] = SW[1], DBUS[0] = SW[0]; reg4 AReg (DBUS, RegAWn, Clockn, RegAQ); endmodule Instantiates a reg4 FILE: TOC_REGA.v (Continued) module reg4 (D, Wn, Clock, Q); input [3:0] D; input Clock, Wn; output reg [3:0] Q; (posedge Clock) if (Wn==0) Q <= D; else Q <= Q; endmodule FPGA Assigned Names to FPGA Pins Wires RegAWn SW[4] Wn SW[3] Q3 D3 RegAQ[3] RegAQ[2] RegAQ[1] RegAQ[0] SW[2] Q2 D2 SW[1] Q1 RegA D1 Slider Switches SW[0] Q0 D0 DBUS KEY0 Clock Clockn Clock Note: reg4 is generically described. Push Button Switch Sub- Circuit LEDR[3] LEDR[2] LEDR[1] LEDR[0] RED LEDS DE2 Board Component DE2 Board Components 27

ANALYSIS: I/O OF TOP LEVEL MODULE Top level design file has inputs SW and KEY0; and outputs LEDR These inputs/outputs are connected to the pins on the FPGA which have been assigned the same names by

28 ANALYSIS: I/O OF TOP LEVEL MODULE Top level design file has inputs SW and KEY0; and outputs LEDR These inputs/outputs are connected to the pins on the FPGA which have been assigned the same names by the import assignments procedure. These FPGA pins are connected to the Slider Switch, Push Button, and Red LED Peripherals on the DE2 board. FILE: TOC_REGA.v TOC_REGA Circuit KEY[0] LEDR[3] LEDR[0] SW[4] SW[0] KEY[0] LEDR[3] LEDR[0] SW[4] SW[0] module TOC_REGA (SW, KEY, LEDR); input [4:0] SW; input [0:0] KEY; output [3:0] LEDR; 28

29 NALYSIS UB MODULE EG A template for a sub-circuit is designed and named as reg4. This sub-circuit has inputs D, Clock, and Wn; and output Q Note that these are names within the sub-module (sub-circuit) A template is not actually realized in the circuit, but just declared in the source code Naming within the module should be done generically, since your sub-module may be reused in a different application, for example, that is not a TOC. Wn Q3 D3 Q2 D2 Q1 RegA D1 Q0 D0 Clock module reg4 (D, Wn, Clock, Q); input [3:0] D; input Clock, Wn; output reg [3:0] Q; (posedge Clock) if (Wn==0) Q <= D; endmodule 29

ANALYSIS: INSTANTIATION OF REG4 AND CONNECTION TO REST OF CIRCUIT The following statement creates (realizes) a 4-bit

connected to various points of the circuit: input [4:0] SW; input [0:0] KEY; output [3:0] LEDR; wire [3:0] DBUS, RegAQ;

[3:0]; assign RegAWn = SW[4]; assign DBUS[3:0] = SW[3:0]; reg4 AReg (DBUS, RegAWn, Clockn, RegAQ); RegAWn SW[4] Wn SW[3] Q3

30 ANALYSIS: INSTANTIATION OF REG4 AND CONNECTION TO REST OF CIRCUIT The following statement creates (realizes) a 4-bit register reg4 AReg (DBUS, RegAWn, Clockn, RegAQ); This makes a 4-bit register and names the register AReg Wires are connected to various points of the circuit: input [4:0] SW; input [0:0] KEY; output [3:0] LEDR; wire [3:0] DBUS, RegAQ; //declaration wire RegAWn, Clock, Clockn; //declaration assign Clockn = ~Clock, Clock = KEY[0]; assign LEDR [3:0] = RegAQ [3:0]; assign RegAWn = SW[4]; assign DBUS[3:0] = SW[3:0]; reg4 AReg (DBUS, RegAWn, Clockn, RegAQ); RegAWn SW[4] Wn SW[3] Q3 D3 RegAQ[3] RegAQ[2] RegAQ[1] RegAQ[0] SW[2] Q2 D2 SW[1] Q1 RegA D1 SW[0] Q0 D0 DBUS KEY0 Clock Clockn Clock LEDR[3] LEDR[2] LEDR[1] LEDR[0] 30

31 VERILOG DESCRIPTION OF ALU 4-BIT, WITHOUT CARRY AND OVERFLOW module alu4 (ASIDE, BSIDE, S, F); input [3:0] ASIDE, BSIDE, S; output reg [3:0] F; (ASIDE, BSIDE, S) case (S) 0: F = 4'b0000; 1: F = BSIDE - ASIDE; 2: F = ASIDE - BSIDE; 3: F = ASIDE + BSIDE; 4: F = ASIDE ^ BSIDE; 5: F = ASIDE BSIDE; 6: F = ASIDE & BSIDE; 7: F = 4'b1111; default: F = 4'bzzzz; endcase ASIDE 4 4 F 4-BIT ALU BSIDE 4 S3 S2 S1 S0 endmodule 31

32 VERILOG DESCRIPTION OF ALU HOMEWORK: 4-BIT, WITH CARRY 4 Cout ASIDE F 4-BIT ALU BSIDE S3 S2 S1 S

33 VERILOG DESCRIPTION OF 7-SEGMENT DECODER HOMEWORK 7- Segment Decoder REGR 33

Laboratory Exercise 1

Laboratory Exercise 1 Switches, Lights, and Multiplexers The purpose of this exercise is to learn how to connect simple input and output devices to an FPGA chip and implement a circuit that uses these