TPZ013GV3 TSMC 0.13um Standard I/O Library. Databook

Transcription

1 TPZ013GV3 TSMC 0.13um Standard I/O Library Databook Version 220C May 11, 2007

2 Copyright 2007 Taiwan Semiconductor Manufacturing Company Ltd. All Rights Reserved No part of this publication may be reproduced in whole or part by any means without the prior written consent. NOTICE Taiwan Semiconductor Manufacturing Company Ltd. reserves the right to make changes in the contents of this document without notice. No responsibility is assumed by Taiwan Semiconductor Manufacturing Company Ltd. for any infringements of patents or other rights of the third parties that may result from its use. Taiwan Semiconductor Manufacturing Company Ltd. assumes no responsibility for any error that appears in this document.

3 Table of Contents Chapter 1 Introduction 1 Description... 1 Chapter 2 DC Information 2 DC Characteristics... 2 Recommended Operating Conditions... 2 Characterization Conditions... 4 Propagation Delay... 4 Transition Time... 5 Propagation Delay Calculation... 5 Chapter 3 Cell Categories 7 Chapter 4 Simultaneously Switching Output Driving Factors 9 Terminologies and Definitions... 9 Simultaneously Switching Output (SSO)... 9 Simultaneously Switching Noise (SSN)... 9 Driving Index (DI)... 9 Driving Factor (DF)... 9 DF values Chapter 5 Time to Valid State Following a Simultaneous Switching Event 11 Chapter 6 Cell Datasheets 12 Truth Table Section Cell Information Section Pin Capacitance Section Propagation Delay Section Chapter 7 Design Kits Support 14 Chapter 8 Contact Us 15 iii

4 Chapter 9 Datasheets 16 iv

5 Chapter 1 Introduction Description This Databook provides basic information about the TPZ013GV3 Staggered Universal Standard I/O library. The TPZ013GV3 I/O library is designed to optimize I/O performance with core voltage of 1.2V (typical case); I/O voltage of 3.3V (typical case) in the TSMC 0.13um Logic (1.2V/3.3V) process. Design engineers can refer to this book for cell availability, DC characteristics, design kits availability, cell logic function, and so on. The following table provides TPZ013GV3 I/O cell dimension. Table 1.1 Dimension of TPZ013GV3 I/O Cell Design Dimension I/O Height I/O Width Physical Dimension 190μm 30μm Note: Please obtain bonding pads from the TPB013GV bonding pad library. TPZ013GV3 Databook May

6 DC Characteristics Chapter 2 DC Information The following tables summarize the recommended operating conditions and electrical characteristics of TPZ013GV3 library. Recommended Operating Conditions Warning: Permanent damage could occur if the operation exceeds the ranges listed in Table 2.1. Table 2.1 Recommended Operating Conditions Min. Nom. Max. Units V DD Pre-Driver Voltage V V DDPST Post-Driver Voltage V T J Junction Temperature C V I MAX Maximum Input Voltage V TPZ013GV3 Databook May

7 Table 2.2 DC Characteristics Min. Nom. Max. Units V IL Input Low Voltage V V IH Input High Voltage V V T Threshold Point V + Schmitt Trig. Low to High V T Threshold Point V - Schmitt Trig. High to Low V T Threshold Point V Input Leakage V I I = I 3.3V or 0V - - ±10μ A I OZ Tri-state Output Leakage V O = 3.3V or 0V - - ±10μ A R PU Pull-up Resistor 44K 61K 92K Ω R PD Pull-down Resistor 33K 51K 89K Ω V OL Output Low Voltage V V OH Output High Voltage V I OL I OH Low Level Output OL (max) High Level Output OH (min) 2mA ma 4mA ma 8mA ma 12mA ma 16mA ma 24mA ma 2mA ma 4mA ma 8mA ma 12mA ma 16mA ma 24mA ma TPZ013GV3 Databook May

8 Characterization Conditions Timing information is characterized under four operating conditions: Worst-case, Typical-case, Best-case, and Low Temperature. Table 2.3 lists the details of each condition. Table 2.3 Characterization Conditions Type Condition Low Temperature VDDcore = 1.32V VDD IO = 3.6V Temperature = -40 C Process = Fast-Fast process Best case VDDcore = 1.32V VDD IO = 3.6V Temperature = 0 C Process = Fast-Fast process Typical case VDDcore = 1.2V VDD IO = 3.3V Temperature = 25 C Process = Typical-Typical process Worst case VDDcore = 1.08V VDD IO = 3.0V Temperature = 125 C Process = Slow-Slow process Propagation Delay Two different propagation delays, tp LH and tp HL, represent the state change delay for low to high and from high to low transitions. The propagation delay is measured from the 50% point of the input waveform to the 50% point of the output waveform as shown in Figure 2.1 TPZ013GV3 Databook May

9 I 50% O % tp HL 50% % Figure 2.1 The Propagation Delay Transition Time Characterization is based on a method; that is, the 10% and 90% points of the full output swing are used to define the rise and fall transition as illustrated in Figure 2.2. Please refer to the Synopsys.lib file for details. In 90% Out 10% Rise Transition Time Full Output Swing Figure 2.2 The Transition Time Propagation Delay Calculation The propagation delay is a non-linear function of the loads. Using the 5 x 6 lookup table of the Synopsys.lib file, three piece-wise linear functions are created to calculate propagation delays for various load conditions. Each linear function has a dedicated linear equation, and three linear equations are provided to model the delay. Each group equation in the table of propagation delay is based on values extracted from the third row of the 5 x 6 look-up table for your reference. Three groups of linear equations are defined as follows: Group 1: Based on the first and second points of the load index, if a cell has a load that is less than or equal to the second point of the load index, use the linear equation in Group 1 to calculate the propagation delay. Group 2: Based on the third and fourth points of the load index, if a cell has a load that is more than the second point and less than the fifth point of the load index, use the linear equation in Group 2 to calculate the propagation delay. TPZ013GV3 Databook May

10 Group 3: Based on the fifth and sixth points of the load index, if a cell has a load that is more than or equal to the fifth point of the load index, use the linear equation in Group 3 to calculate the propagation delay. A linear equation is formed in the following format: where D = D i + K*C load D = propagation delay (ns) D i = cell intrinsic (unloaded) delay (ns) K = delay factor (ns/pf) C load = value of output load (pf) TPZ013GV3 Databook May

11 Chapter 3 Cell Categories This chapter provides information about cell categories in the TSMC TPZ013GV3 library. Table 3.1 lists the functional description for each cell type. Table 3.1 Cell Descriptions Cell Type PCI33DGZ PCI33SDGZ PCI66DGZ PCI66SDGZ PDBxDGZ Functional Description 3-State Output 33 MHz PCI Buffer Pad with Input and Limited Slew Rate, 5V-Tolerant 3-State Output 33 MHz PCI Buffer Pad with Schmitt Trigger Input and Limited Slew Rate, 5V-Tolerant 3-State Output 66 MHz PCI Buffer Pad with Input and Limited Slew Rate, 5V-Tolerant 3-State Output 66 MHz PCI Buffer Pad with Schmitt Trigger Input and Limited Slew Rate, 5V-Tolerant CMOS 3-State Output Pad with Input, 5V-Tolerant PDBxSDGZ CMOS 3-State Output Pad with Schmitt Trigger Input, 5V- Tolerant PDDDGZ PDDSDGZ PDDWDGZ Input Pad with Pull-Down, 5V-Tolerant Schmitt Trigger Input Pad with Pull-Down, 5V-Tolerant Input Pad with Controllable Pull-Down, 5V-Tolerant PDDWxDGZ 3-State Output Pad with Input and Controllable Pull-Down, 5V- Tolerant PDDxDGZ PDDxSDGZ PDIDGZ PDISDGZ PDOxCDG PDTxDGZ PDUDGZ PDUSDGZ PDUWDGZ PDUWxDGZ PDUxDGZ CMOS 3-State Output Pad with Input and Pull-Down, 5V-Tolerant CMOS 3-State Output Pad with Schmitt Trigger Input and Pull- Down, 5V-Tolerant Input Pad, 5V-Tolerant Schmitt Trigger Input Pad, 5V-Tolerant CMOS Output Pad CMOS 3-State Output Pad, 5V-Tolerant Input Pad with Pull-Up, 5V-Tolerant Schmitt Trigger Input Pad with Pull-Up, 5V-Tolerant Input Pad with Controllable Pull-Up, 5V-Tolerant CMOS 3-State Output Pad with Input and Controllable Pull-Up, 5V-Tolerant CMOS 3-State Output Pad with Input and Pull-Up, 5V-Tolerant TPZ013GV3 Databook May

12 Cell Type PDUxSDGZ PDXOExDG PDXOxDG Functional Description CMOS 3-State Output Pad with Schmitt Trigger Input Pad and Pull-Up, 5V-Tolerant Crystal Oscillator with High Enable Crystal Oscillator PRBxDGZ CMOS 3-State Output Pad with Input and Limited Slew Rate, 5V- Tolerant PRBxSDGZ PRDWxDGZ PRDxDGZ PRDxSDGZ PROxCDG PRTxDGZ PRUWxDGZ PRUxDGZ PRUxSDGZ PVDD2POC PVDDxDGZ PVSSxDGZ PVDD1ANA PVDD2ANA PVSS1ANA PVSS2ANA PRCUT CMOS 3-State Output Pad with Schmitt Trigger Input and Limited Slew Rate, 5V-Tolerant CMOS 3-State Output Pad with Input, Controllable Pull-Down, and Limited Slew Rate, 5V-Tolerant CMOS 3-State Output Pad with Input, Pull-Down, and Limited Slew Rate, 5V-Tolerant CMOS 3-State Output Pad with Schmitt Trigger Input, Pull-Down, and Limited Slew Rate, 5V-Tolerant CMOS Output Pad with Limited Slew Rate CMOS 3-State Output Pad with Limited Slew Rate, 5V-Tolerant CMOS 3-State Output Pad with Input, Controllable Pull-Up, and Limited Slew Rate, 5V-Tolerant CMOS 3-State Output Pad with Input, Pull-Up, and Limited Slew Rate, 5V-Tolerant CMOS 3-State Output Pad with Schmitt Trigger Input, Pull-Up, and Limited Slew Rate, 5V-Tolerant Power-On Control Cell (Please place one and only one PVDD2POC cell in each digital domain) Power Pad Ground Pad The dedicated power supply to internal macro with core voltage The dedicated power supply to internal macro with I/O voltage The dedicated ground supply for PVDD1ANA The dedicated ground supply for PVDD2ANA The power-cut cell that can be used in between two digital domains with different supplied voltage or can be used to isolate the particular domain from others for noise concern TPZ013GV3 Databook May

13 Chapter 4 Simultaneously Switching Output Driving Factors Terminologies and Definitions Simultaneously Switching Output (SSO) SSO means that a certain number of I/O buffers switching at the same time with the same direction (H L, HZ L or L H, LZ H), which would result in noise on the power/ground lines because of the large di/dt value and the parasitic inductance of the bonding wire on the I/O power/ground cells. Simultaneously Switching Noise (SSN) SSN means the noise produced by the simultaneously switching output buffers. It would change the voltage levels of power/ground nodes, so-called Ground Bounce Effect. Ground Bounce Effect is tested at the device output by keeping one stable output at low 0 or high 1, while all other outputs of the device switch simultaneously. The noise occurred at the stable output node is called Quiet Output Switching (QOS). If the input low voltage is defined as Vil, the QOS of Vil is taken to be the maximum noise that the system can endure. Driving Index (DI) DI is the maximum copies of the specific I/O cell switching from high to low simultaneously without making the voltage on the quiet output 0 higher than V il when single ground cell is applied. We take the QOS of V il as a criterion in defining DI because 1 has more noise margin than 0. For example, in LVTTL specification, the margin of V ih (2.0V) to VD33 (3.3V) is 1.3V in typical corner, which is higher than the margin of V il (0.8V) to ground (0V). Driving Factor (DF) DF is the amount of how the specific output buffer contributes to the SSN on the power/ground rail. The DF value of an output buffer is proportional to di/dt, the derivative of the current on the output buffer. We can obtain DF as follows: DF = 1/DI TPZ013GV3 Databook May

14 DF values All circuit model parameters are listed below: Process: Fast, Fast Temperature: -40 Celsius degree Pre-driver Voltage: 1.32V Post-driver Voltage: 3.6V R, L, C Values: R vss, R vdd = R pin = 0.3 Ohms C vss, C vdd = C pin = 4 pf C load (for 2 ma I/O) = 33 pf C load (for 4 ma I/O) = 50 pf C load (for 8 ma I/O) = 75 pf C load (for 12 ma, 16 ma, 24 ma I/O) = 85 pf L load, L vdd = L pin = 5.2 nh / 7.8 nh / 10.5 nh Note 1: For R, L, and C reference, please refer to TSMC Standard I/O Library General Application Note which provides general information and is available to download at TSMC Online. Note 2: The DF tables are provided at the end of this databook for reference. TPZ013GV3 Databook May

15 Chapter 5 Time to Valid State Following a Simultaneous Switching Event Simultaneous Switching Output (SSO) noise amplitude decreases with time after the peak point passes. If a design with simultaneously switching outputs fails to meet the specifications mentioned in the simulation results section (because of pin count restrictions), designers should sample the data after a period of time to ensure the validity of the sampled data. These time-to-valid-state tables available at the end of this databook provide information about the timing of the state at which the SSO noise has declined to the acceptable value (V IL ), though the number of power/ground pads is not sufficient. We provide the tables that show the stable time for different driving capability I/O buffers with and without slew rate control in 5.2nH case, 7.8 nh case, and the 10.5nH case respectively. In all cases, only one pair of power/ground pads is used. Note: The Time-to-Valid-State tables are provided at the end of this databook for reference. TPZ013GV3 Databook May

16 Chapter 6 Cell Datasheets This chapter provides TSMC TPZ013GV3 datasheet contents. There are four sections included in each cell description: Truth table Cell information Pin capacitance Propagation delay Truth Table Section The truth table lists all possible combinations of input and output signals for the cell. Table 6.1 defines all the symbols used in the datasheet truth table. Table 6.1 Truth Table Symbols Symbol Definition 0 Logic Low 1 Logic High X Z Don t care High Impedance Cell Information Section The cell information section provides information about the number of pads required, internal power consumption, and driving capability. Pin Capacitance Section The pin capacitance table describes the typical loading at each pin of the cell (pf), corresponding to each driving strength. TPZ013GV3 Databook May

17 Propagation Delay Section The propagation delay table describes the approximate delay value of each pin for variable driving strength with different loading. Rise time and fall time are measured at each particular corner. TPZ013GV3 Databook May

18 Chapter 7 Design Kits Support The following design kits/packages are delivered in a standard library release Table 7.1 Deliverable Design Kits Abbreviation rln doc syn vlg vit mdt apf/apt sef gds ctc ibs spi lpe Description Release note Databooks Synopsys db and lib Verilog simulation model VHDL/Vital simulation model Mentor DFTadvisor and Fastscan model Apollo/Astro frame view, layout view and runset files Silicon Ensemble /SOC Encounter TM frame view, layout view and runset files GDSII layout views CeltIC CDB view IBIS kit Spice netlist Layout parasitic extracted spice netlist TPZ013GV3 Databook May

19 Chapter 8 Contact Us The TSMC standard I/O libraries are released under the supervision of the TSMC standard quality assurance (QA) procedure. If you find any errors or encounter any problems with the TPZ013GV3 library, please contact your library distributor or TSMC regional application engineers for immediate assistance. TPZ013GV3 Databook May

20 Chapter 9 Datasheets This chapter provides TSMC TPZ013GV3 datasheets for each cell. Please begin with the page after the example below for details. Cell Schematic Library Name Cell Description PCI33SDGZ 3-STATE OUTPUT 33MHz PCI BUFFER PAD WITH Schmitt Trigger INPUT AND LIMITED SLEW RATE, 5V-Tolerant TPZ013LODG3 TPZ013GV3 Databook May

21 Characterization Condition: Process = Typ, Voltage = Typ, Temp = 25 C Group equation for Propagation Delay calculation (Please refer to page 6 for details) TPZ013GV3 Databook May

22 PCI33DGZx in TPZ013GV3 Digital Library PCI33DGZx TPZ013GV3 Tri State Output 33MHz PCI Buffer Pad with Input and Limited Slew Rate, 5V Tolerant Truth Table INPUT OUTPUT OEN I PAD C 1 x x x Z x Cell Information No. Pad Req. Power (uw/mhz) PCI33DGZ Leakage Power Information (W) VDD VDDPST PCI33DGZ 1.27E E 08 PCI33DGZx 1

23 PCI33DGZx in TPZ013GV3 Digital Library Pin Capacitance (pf) C I OEN PAD PCI33DGZ Propagation Delay (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) *Cload *Cload *Cload PCI33DGZ *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PCI33DGZx 2

24 PCI33SDGZx in TPZ013GV3 Digital Library PCI33SDGZx TPZ013GV3 3 State Output 33MHz PCI Buffer Pad with Schmitt Trigger Input and Limited Slew Rate, 5V Tolerant Truth Table INPUT OUTPUT OEN I PAD C 1 x x x Z x Cell Information No. Pad Req. Power (uw/mhz) PCI33SDGZ Leakage Power Information (W) VDD VDDPST PCI33SDGZ 1.27E E 08 PCI33SDGZx 1

25 PCI33SDGZx in TPZ013GV3 Digital Library Pin Capacitance (pf) C I OEN PAD PCI33SDGZ Propagation Delay (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) *Cload *Cload *Cload PCI33SDGZ *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PCI33SDGZx 2

26 PCI66DGZx in TPZ013GV3 Digital Library PCI66DGZx TPZ013GV3 Tri State Output 66MHz PCI Buffer Pad with Input and Limited Slew Rate, 5V Tolerant Truth Table INPUT OUTPUT OEN I PAD C 1 x x x Z x Cell Information No. Pad Req. Power (uw/mhz) PCI66DGZ Leakage Power Information (W) VDD VDDPST PCI66DGZ 1.27E E 08 PCI66DGZx 1

27 PCI66DGZx in TPZ013GV3 Digital Library Pin Capacitance (pf) C I OEN PAD PCI66DGZ Propagation Delay (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) *Cload *Cload *Cload PCI66DGZ *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PCI66DGZx 2

28 PCI66SDGZx in TPZ013GV3 Digital Library PCI66SDGZx TPZ013GV3 Tri State Output 66MHz PCI Buffer Pad with Schmitt Trigger Input and Limited Slew Rate, 5V Tolerant Truth Table INPUT OUTPUT OEN I PAD C 1 x x x Z x Cell Information No. Pad Req. Power (uw/mhz) PCI66SDGZ Leakage Power Information (W) VDD VDDPST PCI66SDGZ 1.27E E 08 PCI66SDGZx 1

29 PCI66SDGZx in TPZ013GV3 Digital Library Pin Capacitance (pf) C I OEN PAD PCI66SDGZ Propagation Delay (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) *Cload *Cload *Cload PCI66SDGZ *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PCI66SDGZx 2

30 PDBxDGZx in TPZ013GV3 Digital Library PDBxDGZx TPZ013GV3 CMOS Tri State Output Pad with Input, High V Tolerant Truth Table INPUT OUTPUT OEN I PAD C 1 x x x Z x Cell Information No. Pad Req. Power (uw/mhz) Drive Capability (ma) PDB02DGZ PDB04DGZ PDB08DGZ PDB12DGZ PDB16DGZ PDB24DGZ Leakage Power Information (W) PDBxDGZx 1

31 PDBxDGZx in TPZ013GV3 Digital Library VDD VDDPST PDB02DGZ 1.27E E 08 PDB04DGZ 1.27E E 08 PDB08DGZ 1.27E E 08 PDB12DGZ 1.27E E 08 PDB16DGZ 1.27E E 08 PDB24DGZ 1.27E E 08 Pin Capacitance (pf) C I OEN PAD PDB02DGZ PDB04DGZ PDB08DGZ PDB12DGZ PDB16DGZ PDB24DGZ Propagation Delay (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) (< )pf ( )pf (> )pf *Cload *Cload *Cload PDB02DGZ *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload (< )pf ( )pf (> )pf PDBxDGZx 2

32 PDBxDGZx in TPZ013GV3 Digital Library *Cload *Cload *Cload PDB08DGZ PDB12DGZ *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDBxDGZx 3

33 PDBxDGZx in TPZ013GV3 Digital Library PDB16DGZ PDB24DGZ *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDBxDGZx 4

34 PDBxSDGZx in TPZ013GV3 Digital Library PDBxSDGZx TPZ013GV3 CMOS Tri State Output Pad with Schmitt Trigger Input, High V Tolerant Truth Table INPUT OUTPUT OEN I PAD C 1 x x x Z x Cell Information No. Pad Req. Power (uw/mhz) Drive Capability (ma) PDB02SDGZ PDB04SDGZ PDB08SDGZ PDB12SDGZ PDB16SDGZ PDB24SDGZ Leakage Power Information PDBxSDGZx 1

35 PDBxSDGZx in TPZ013GV3 Digital Library (W) VDD VDDPST PDB02SDGZ 1.27E E 08 PDB04SDGZ 1.27E E 08 PDB08SDGZ 1.27E E 08 PDB12SDGZ 1.27E E 08 PDB16SDGZ 1.27E E 08 PDB24SDGZ 1.27E E 08 Pin Capacitance (pf) C I OEN PAD PDB02SDGZ PDB04SDGZ PDB08SDGZ PDB12SDGZ PDB16SDGZ PDB24SDGZ Propagation Delay (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) (< )pf ( )pf (> )pf *Cload *Cload *Cload PDB02SDGZ *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDBxSDGZx 2

36 PDBxSDGZx in TPZ013GV3 Digital Library PDB04SDGZ PDB08SDGZ PDB12SDGZ (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDBxSDGZx 3

37 PDBxSDGZx in TPZ013GV3 Digital Library PDB16SDGZ PDB24SDGZ *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDBxSDGZx 4

38 PDDDGZx in TPZ013GV3 Digital Library PDDDGZx TPZ013GV3 Input Pad With Pull down, High V Tolerant Truth Table INPUT OUTPUT PAD C 1 1 Z Cell Information No. Pad Req. Power (uw/mhz) PDDDGZ Leakage Power Information (W) VDD VDDPST PDDDGZ 9.51E E 08 Pin Capacitance (pf) C PAD PDDDGZx 1

39 PDDDGZx in TPZ013GV3 Digital Library PDDDGZ Propagation Delay PDDDGZ (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) *Cload *Cload *Cload *Cload *Cload *Cload PDDDGZx 2

40 PDDSDGZx in TPZ013GV3 Digital Library PDDSDGZx TPZ013GV3 Schmitt Trigger Input Pad with Pull Down, High V Tolerant Truth Table INPUT OUTPUT PAD C 1 1 Z Cell Information No. Pad Req. Power (uw/mhz) PDDSDGZ Leakage Power Information (W) VDD VDDPST PDDSDGZ 9.51E E 08 Pin Capacitance (pf) C PAD PDDSDGZ PDDSDGZx 1

41 PDDSDGZx in TPZ013GV3 Digital Library Propagation Delay PDDSDGZ (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) *Cload *Cload *Cload *Cload *Cload *Cload PDDSDGZx 2

42 PDDWDGZx in TPZ013GV3 Digital Library PDDWDGZx TPZ013GV3 Input Pad with Enable Controlled Pull Down, High V Tolerant Truth Table INPUT OUTPUT REN PAD C x 0 0 x Z 0 1 Z x Cell Information No. Pad Req. Power (uw/mhz) PDDWDGZ Leakage Power Information (W) VDD VDDPST PDDWDGZ 1.16E E 08 Pin Capacitance (pf) C PAD REN PDDWDGZx 1

43 PDDWDGZx in TPZ013GV3 Digital Library PDDWDGZ Propagation Delay PDDWDGZ (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) *Cload *Cload *Cload *Cload *Cload *Cload PDDWDGZx 2

44 PDDWxDGZx in TPZ013GV3 Digital Library PDDWxDGZx TPZ013GV3 Tri State Output Pad with Input and Enable Controlled Pull Down, High V Tolerant Truth Table INPUT OUTPUT REN OEN I PAD C x 1 x 0 0 x 1 x x Z x Z x x x Cell Information No. Pad Req. Power (uw/mhz) Drive Capability (ma) PDDW02DGZ PDDW04DGZ PDDW08DGZ PDDW12DGZ PDDW16DGZ PDDW24DGZ PDDWxDGZx 1

45 PDDWxDGZx in TPZ013GV3 Digital Library Leakage Power Information (W) VDD VDDPST PDDW02DGZ 1.13E E 08 PDDW04DGZ 1.13E E 08 PDDW08DGZ 1.13E E 08 PDDW12DGZ 1.13E E 08 PDDW16DGZ 1.13E E 08 PDDW24DGZ 1.13E E 08 Pin Capacitance (pf) C I OEN PAD REN PDDW02DGZ PDDW04DGZ PDDW08DGZ PDDW12DGZ PDDW16DGZ PDDW24DGZ Propagation Delay (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) (< )pf ( )pf (> )pf *Cload *Cload *Cload PDDW02DGZ *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDDWxDGZx 2

46 PDDWxDGZx in TPZ013GV3 Digital Library PDDW04DGZ PDDW08DGZ PDDW12DGZ (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDDWxDGZx 3

47 PDDWxDGZx in TPZ013GV3 Digital Library PDDW16DGZ PDDW24DGZ *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDDWxDGZx 4

48 PDDxDGZx in TPZ013GV3 Digital Library PDDxDGZx TPZ013GV3 CMOS Tri State Output Pad with Input and Pull Down, High V Tolerant Truth Table INPUT OUTPUT OEN I PAD C 1 x x x Z Cell Information No. Pad Req. Power (uw/mhz) Drive Capability (ma) PDD02DGZ PDD04DGZ PDD08DGZ PDD12DGZ PDD16DGZ PDD24DGZ Leakage Power Information PDDxDGZx 1

49 PDDxDGZx in TPZ013GV3 Digital Library (W) VDD VDDPST PDD02DGZ 9.62E E 08 PDD04DGZ 9.62E E 08 PDD08DGZ 9.62E E 08 PDD12DGZ 9.62E E 08 PDD16DGZ 9.62E E 08 PDD24DGZ 9.62E E 08 Pin Capacitance (pf) C I OEN PAD PDD02DGZ PDD04DGZ PDD08DGZ PDD12DGZ PDD16DGZ PDD24DGZ Propagation Delay (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) (< )pf ( )pf (> )pf *Cload *Cload *Cload PDD02DGZ *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDDxDGZx 2

50 PDDxDGZx in TPZ013GV3 Digital Library PDD04DGZ PDD08DGZ PDD12DGZ (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDDxDGZx 3

51 PDDxDGZx in TPZ013GV3 Digital Library PDD16DGZ PDD24DGZ *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDDxDGZx 4

52 PDDxSDGZx in TPZ013GV3 Digital Library PDDxSDGZx TPZ013GV3 CMOS Tri State Output Pad with Schmitt Trigger Input and Pull Down, High V Tolerant Truth Table INPUT OUTPUT OEN I PAD C 1 x x x Z Cell Information No. Pad Req. Power (uw/mhz) Drive Capability (ma) PDD02SDGZ PDD04SDGZ PDD08SDGZ PDD12SDGZ PDD16SDGZ PDD24SDGZ Leakage Power Information PDDxSDGZx 1

53 PDDxSDGZx in TPZ013GV3 Digital Library (W) VDD VDDPST PDD02SDGZ 9.62E E 08 PDD04SDGZ 9.62E E 08 PDD08SDGZ 9.62E E 08 PDD12SDGZ 9.62E E 08 PDD16SDGZ 9.62E E 08 PDD24SDGZ 9.62E E 08 Pin Capacitance (pf) C I OEN PAD PDD02SDGZ PDD04SDGZ PDD08SDGZ PDD12SDGZ PDD16SDGZ PDD24SDGZ Propagation Delay (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) (< )pf ( )pf (> )pf *Cload *Cload *Cload PDD02SDGZ *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDDxSDGZx 2

54 PDDxSDGZx in TPZ013GV3 Digital Library PDD04SDGZ PDD08SDGZ PDD12SDGZ (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDDxSDGZx 3

55 PDDxSDGZx in TPZ013GV3 Digital Library PDD16SDGZ PDD24SDGZ *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDDxSDGZx 4

56 PDIDGZx in TPZ013GV3 Digital Library PDIDGZx TPZ013GV3 Input Pad, High V Tolerant Truth Table INPUT OUTPUT PAD C Cell Information No. Pad Req. Power (uw/mhz) PDIDGZ Leakage Power Information (W) VDD VDDPST PDIDGZ 1.27E E 08 Pin Capacitance (pf) C PAD PDIDGZ PDIDGZx 1

57 PDIDGZx in TPZ013GV3 Digital Library Propagation Delay PDIDGZ (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) *Cload *Cload *Cload *Cload *Cload *Cload PDIDGZx 2

58 PDISDGZx in TPZ013GV3 Digital Library PDISDGZx TPZ013GV3 Schmitt Trigger Input Pad, High V Tolerant Truth Table INPUT OUTPUT PAD C Cell Information No. Pad Req. Power (uw/mhz) PDISDGZ Leakage Power Information (W) VDD VDDPST PDISDGZ 1.27E E 08 Pin Capacitance (pf) C PAD PDISDGZ PDISDGZx 1

59 PDISDGZx in TPZ013GV3 Digital Library Propagation Delay PDISDGZ (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) *Cload *Cload *Cload *Cload *Cload *Cload PDISDGZx 2

60 PDOxCDGx in TPZ013GV3 Digital Library PDOxCDGx TPZ013GV3 CMOS Output Pad Truth Table INPUT OUTPUT I PAD Cell Information No. Pad Req. Power (uw/mhz) Drive Capability (ma) PDO02CDG PDO04CDG PDO08CDG PDO12CDG PDO16CDG PDO24CDG Leakage Power Information (W) VDD VDDPST PDO02CDG 1.76E E 08 PDO04CDG 1.76E E 08 PDOxCDGx 1

61 PDOxCDGx in TPZ013GV3 Digital Library PDO08CDG 1.76E E 08 PDO12CDG 1.76E E 08 PDO16CDG 1.76E E 08 PDO24CDG 1.76E E 08 Pin Capacitance (pf) I PAD PDO02CDG PDO04CDG PDO08CDG PDO12CDG PDO16CDG PDO24CDG Propagation Delay PDO02CDG (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload PDO04CDG PDO08CDG PDO12CDG PDO16CDG (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDOxCDGx 2

62 PDOxCDGx in TPZ013GV3 Digital Library PDO24CDG *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDOxCDGx 3

63 PDTxDGZx in TPZ013GV3 Digital Library PDTxDGZx TPZ013GV3 CMOS Tri State Output Pad, High V Tolerant Truth Table INPUT OUTPUT OEN I PAD 1 x Z Cell Information No. Pad Req. Power (uw/mhz) Drive Capability (ma) PDT02DGZ PDT04DGZ PDT08DGZ PDT12DGZ PDT16DGZ PDT24DGZ Leakage Power Information (W) VDD VDDPST PDT02DGZ 1.71E E 08 PDTxDGZx 1

64 PDTxDGZx in TPZ013GV3 Digital Library PDT04DGZ 1.71E E 08 PDT08DGZ 1.71E E 08 PDT12DGZ 1.71E E 08 PDT16DGZ 1.71E E 08 PDT24DGZ 1.71E E 08 Pin Capacitance (pf) I OEN PAD PDT02DGZ PDT04DGZ PDT08DGZ PDT12DGZ PDT16DGZ PDT24DGZ Propagation Delay (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) (< )pf ( )pf (> )pf *Cload *Cload *Cload PDT02DGZ PDT04DGZ *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload (< )pf ( )pf (> )pf PDTxDGZx 2

65 PDTxDGZx in TPZ013GV3 Digital Library PDT08DGZ PDT12DGZ PDT16DGZ PDT24DGZ *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDTxDGZx 3

66 PDTxDGZx in TPZ013GV3 Digital Library *Cload *Cload *Cload *Cload *Cload *Cload PDTxDGZx 4

67 PDUDGZx in TPZ013GV3 Digital Library PDUDGZx TPZ013GV3 Input Pad With Pull Up, High V Tolerant Truth Table INPUT OUTPUT PAD C 1 1 Z Cell Information No. Pad Req. Power (uw/mhz) PDUDGZ Leakage Power Information (W) VDD VDDPST PDUDGZ 1.80E E 08 Pin Capacitance (pf) C PAD PDUDGZx 1

68 PDUDGZx in TPZ013GV3 Digital Library PDUDGZ Propagation Delay PDUDGZ (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) *Cload *Cload *Cload *Cload *Cload *Cload PDUDGZx 2

69 PDUSDGZx in TPZ013GV3 Digital Library PDUSDGZx TPZ013GV3 Schmitt Trigger Input Pad with Pull Up, High V Tolerant Truth Table INPUT OUTPUT PAD C 1 1 Z Cell Information No. Pad Req. Power (uw/mhz) PDUSDGZ Leakage Power Information (W) VDD VDDPST PDUSDGZ 1.80E E 08 Pin Capacitance (pf) C PAD PDUSDGZ PDUSDGZx 1

70 PDUSDGZx in TPZ013GV3 Digital Library Propagation Delay PDUSDGZ (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) *Cload *Cload *Cload *Cload *Cload *Cload PDUSDGZx 2

71 PDUWDGZx in TPZ013GV3 Digital Library PDUWDGZx TPZ013GV3 Input Pad with Enable Controlled Pull Up, High V Tolerant Truth Table INPUT OUTPUT REN PAD C x 0 0 x Z 1 1 Z x Cell Information No. Pad Req. Power (uw/mhz) PDUWDGZ Leakage Power Information (W) VDD VDDPST PDUWDGZ 1.45E E 08 Pin Capacitance (pf) C PAD REN PDUWDGZx 1

72 PDUWDGZx in TPZ013GV3 Digital Library PDUWDGZ Propagation Delay PDUWDGZ (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) *Cload *Cload *Cload *Cload *Cload *Cload PDUWDGZx 2

73 PDUWxDGZx in TPZ013GV3 Digital Library PDUWxDGZx TPZ013GV3 Tri State Output Pad with Input and Enable Controlled Pull Up, High V Tolerant Truth Table INPUT OUTPUT REN OEN I PAD C x 1 x 0 0 x 1 x x Z x Z x x x Cell Information No. Pad Req. Power (uw/mhz) Drive Capability (ma) PDUW02DGZ PDUW04DGZ PDUW08DGZ PDUW12DGZ PDUW16DGZ PDUW24DGZ PDUWxDGZx 1

74 PDUWxDGZx in TPZ013GV3 Digital Library Leakage Power Information (W) VDD VDDPST PDUW02DGZ 1.55E E 08 PDUW04DGZ 1.55E E 08 PDUW08DGZ 1.55E E 08 PDUW12DGZ 1.55E E 08 PDUW16DGZ 1.55E E 08 PDUW24DGZ 1.55E E 08 Pin Capacitance (pf) C I OEN PAD REN PDUW02DGZ PDUW04DGZ PDUW08DGZ PDUW12DGZ PDUW16DGZ PDUW24DGZ Propagation Delay (Characterization Condition : Process= Typical, Voltage= Typical, Temp= 25 degree C) (< )pf ( )pf (> )pf *Cload *Cload *Cload PDUW02DGZ *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDUWxDGZx 2

75 PDUWxDGZx in TPZ013GV3 Digital Library PDUW04DGZ PDUW08DGZ PDUW12DGZ (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload (< )pf ( )pf (> )pf *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload *Cload PDUWxDGZx 3