October, Saeid Nooshabadi. Overview COMP3221. Memory Interfacing. Microprocessors and Embedded Systems

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1 Overview COMP 3221 Microprocessors and Embedded Systems Lectures 31: Memory and Bus Organisation - I October, 2003 Memory Interfacing Memory Type Memory Decoding D- Access Making D Access fast saeid@unsw.edu.au COMP3221 lec31-mem-bus-i.1 COMP3221 lec31-mem-bus-i.2 Review: Buses in a PC: Connect a few devices CPU Memory bus Memory PCI PCI: Internal (Backplane) I/O bus Ethernet SCSI SCSI: External I/O bus Data rates Memory: 133 MHz, 8 bytes 1064 MB/s (peak) (1 to 15 disks) PCI: 33 MHz, 8 bytes wide 264 MB/s (peak) Ethernet Local SCSI: Ultra3 (80 MHz), Area Wide (2 bytes) Ethernet: Network COMP3221 lec31-mem-bus-i MB/s (peak) 12.5 MB/s (peak) Review: Computers with Memory Mapped I/O I/O devices Accessed like memory COMP3221 lec31-mem-bus-i.4

2 Big Picture: A System on a Chip ARM System Architecture COMP3221 lec31-mem-bus-i.5 Integration of Core Processor and many subsystem microcells ARM7TDMI core Cache Embedded Co- Processors External Mem Low bandwidth I/O devices Timers I/O ports Need a Mechanism to access various memory units and I/O devices, uniquely, to avoid access conflicts COMP3221 lec31-mem-bus-i.6 ARM System Architecture with Multiple Masters Need a Mechanism to allow various Processing units to access the Memory Bus without causing conflict COMP3221 lec31-mem-bus-i.7 Clock control clock control co nfiguration coprocessor interface COMP3221 lec31-mem-bus-i.8 ARM Core Signals po wer wait eclk bigend irq interrupts ¼q isync initialization enin enout enouti abe ale bu s ape control dbe tbe busen highz busdis ecapclk dbgrq breakpt dbgack exec extern1 extern0 de bug dbgen rangeout0 rangeout1 dbgrqi commrx commtx opc cpi cpa cpb Vdd Vss ARM7TDMI core Din[31:0] Dout[31:0] D[31:0] bl[3:0] r/w mas[1:0] lock trans mode [4:0] abort Tbit tapsm[3:0] ir[3:0] tdoen tck1 tck2 screg[3:0] drivebs ecapclkbs icapclkbs highz pclkbs rstclkbs sdinbs sdoutbs shclkbs shclk2bs TRST TCK TMS TDI TDO me mory interface MMU interface st ate TAP information bo undary scan extension JTAG controls Memory

ARM Core Memory Signals Simple Memory 32 bit address 32 Bi-directional Data D[31:0] Separate Data in and out Din[31:0] & Dout[31:0] Bidirectional Data bus D[31:0] n and for requesting memory access

9 S Size: 2 n x 32 ROM Size: 2 m x 32 COMP3221 lec31-mem-bus-i.

3 ARM Core Memory Signals Simple Memory 32 bit address 32 Bi-directional Data D[31:0] Separate Data in and out Din[31:0] & Dout[31:0] Bidirectional Data bus D[31:0] n and for requesting memory access nr/w for read/ write indication mas[1:0] for data size identification: word 10, halfword 01 and byte 00. All activities controlled by. Internal clock is AND wait COMP3221 lec31-mem-bus-i.9 S Size: 2 n x 32 ROM Size: 2 m x 32 COMP3221 lec31-mem-bus-i.10 4 Ss write enabled separately Read enabled together 4 ROMs No write enable Read enabled together A[0]A[1] Simple Memory Decoder Control mas[0] mas[1] we0 we1 we2 we3 Controls the Activation of and ROM a[31]: 0 ROM a[31]: 1 It controls the byte write enables during write mas[1:0]: 00 Byte, 01 H-word, 10 Word It ensures that data is ready before processor continues. S/ROM Memory Timing Address should be stable during the falling edge S is fast, ROM is slow ROM needs more time. Slows the system Solutions? - Slow down the MCLK clock; loose performance - Use Wait states; more complex control r/w oe A B C COMP3221 A[31] lec31-mem-bus-i.11 ROMoe Oe COMP3221 lec31-mem-bus-i.12

4 ROM Wait Control State Transition Timing Diagram for for ROM Wait States ROM access requires 4 clock cycles access is fast ROM fast ROM1 ROM2 ROM3 wait ROM0e fast ROM1 ROM2 ROM3 COMP3221 lec31-mem-bus-i.13 COMP3221 lec31-mem-bus-i.14 Improving Performance Processor internal operations cycles do not need access to memory Mem. Access is much slower than internal operations. Use wait states for mem Accesses Internal = 1 internal operation Operations can run at max speed mreg = 0 memory access decode D Dynamic Features: much cheaper than S more capacity than S slower than S Widely used in Computer Systems ROM ROM1 ROM2 ROM3 COMP3221 lec31-mem-bus-i.15 COMP3221 lec31-mem-bus-i.16

5 D Organisation Two dimensional matrix Bits are accesses by: Accepting row and column addresses down the same multiplexed address bus First Row address is presented and latched by ras signal Next column COMP3221 lec31-mem-bus-i.17 A[n:0] address is presented and latched by cas signal ras latch latch cas decoder array of memory cells mux Data out Making D Access Fast Accessing data in the same row using casonly access is 2 3 times faster cas-only access does not activate the cell matrix If next accesses is within the same row, a new column address may be presented just by applying a cas-only access. Fact: Most processor addresses are uential (75%) If we had a way of knowing that that the next address is uential with respect with the current address (current address + 4), then we could only assert cas and make D access fast Difficulty? Detecting early in memory access cycle that the next address is in the same row. COMP3221 lec31-mem-bus-i.18 ARM Solution to cas-only Access ARM address register Instruction: ldr r1, [r2] from ALU exception vector swi 75% of next addresses are current address +4. address to memory signal (address + 4) COMP3221 lec31-mem-bus-i.19 address mux mov pc, lr incrementer from/to PC in register bank Sequential addresses flagged by signal The external mem device checks previous address and row boundaries to issue cas only or ras-cas Revised State Transition Diagram = 1: uential address = 0: non-uential = 1 internal operation mreg = 0 memory access de code ROM ROM1 ROM2 ROM3 COMP3221 lec31-mem-bus-i.20

6 D Timing Diagram Notice the pipelined memory access Address is presented 1/2 cycle earlier D Timing Diagram after an Internal Cycle During internal operations cycles, a memory access cycle can be set up in advance. This eliminates the wait (New Cycle) state wait ras cas D[31:0] COMP3221 lec31-mem-bus-i.21 A A+4 A+8 N cycle S cycle S cycle New Address Sequential Address ras cas A A+4 I or C cycle S cycle S cycle Internal or coprocessor cycle COMP3221 lec31-mem-bus-i.22 Memory Access Timing Summary Reading Material Steve Furber: ARM System On-Chip; 2nd Ed, Addison-Wesley, 2000, ISBN: Chapter 8. Notice the pipelined memory access Address is presented 1/2 cycle earlier COMP3221 lec31-mem-bus-i.23 COMP3221 lec31-mem-bus-i.24

7 Conclusion Memory interfacing can degrade performance Can improve performance by increasing the clock frequency and allocating differing clock cycles for each memory access type cas-only accesses in D are 2 to 3 times faster than ras cas accesses. COMP3221 lec31-mem-bus-i.25

Computer and Digital System Architecture

Computer and Digital System Architecture EE/CpE-810-A Bruce McNair bmcnair@stevens.edu 1-1/37 Week 8 ARM processor cores Furber Ch. 9 1-2/37 FPGA architecture Interconnects I/O pin Logic blocks Switch