ARM Processor Architecture (II)

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1 ARM Processor Architecture (II) Speaker: Lung-Hao Chang 張龍豪 Advisor: Prof. Andy Wu 吳安宇教授 Graduate Institute of Electronics Engineering, National Taiwan University Modified from National Chiao-Tung University IP Core Design course

2 2 Outline ARM processor core Memory hierarchy Software development Summary

3 3 ARM Processor Core

4 4 ARM7TDMI Processor Core Current low-end ARM core for applications like digital mobile phones TDMI T: Thumb, 16-bit compressed instruction set D: on-chip Debug support, enabling the processor to halt in response to a debug request M: enhanced Multiplier, yield a full 64-bit result, high performance I: EmbeddedICE hardware Von Neumann architecture 3-stage pipeline CPI ~ 1.9

5 ARM7TDMI Block Diagram SoC Design Laboratory SoC Consortium Course Material 03/17/ extern0 extern1 Embedded ICE scan chain 2 scan chain 0 opc, r/w, mreq, trans, mas[1:0] A[31:0] processor core other signals D[31:0] scan chain 1 Din[31:0] Dout[31:0] bus splitter JTAG TAP controller TCK TMSTRST TDI TDO

6 ARM7TDMI Core Diagram SoC Design Laboratory SoC Consortium Course Material 03/17/2004 6

7 7 SoC Consortium Course Material SoC Design Laboratory 03/17/2004 ARM7TDMI Interface Signals (1/5) mreq seq lock Dout[31:0] D[31:0] r/w mas[1:0] mode[4:0] trans abort opc cpi cpa cpb memory interface MMU interface coprocessor interface mclk wait eclk isync bigend enin irq ¼q reset enout abe Vdd Vss clock control configuration interrupts initialization bus control power ale ape dbe dbgrq breakpt dbgack debug exec extern1 extern0 dbgen bl[3:0] TRST TCK TMS TDI JTAG controls TDO Tbit state tbe rangeout0 rangeout1 dbgrqi commrx commtx enouti highz busdis ecapclk busen Din[31:0] A[31:0] ARM7TDMI core tapsm[3:0] ir[3:0] tdoen tck1 tck2 screg[3:0] TAP information drivebs ecapclkbs icapclkbs highz pclkbs rstclkbs sdinbs sdoutbs shclkbs shclk2bs boundary scan extension

8 8 ARM7TDMI Interface Signals (2/5) Clock control All state change within the processor are controlled by mclk, the memory clock Internal clock = mclk AND \wait eclk clock output reflects the clock used by the core Memory interface 32-bit address (A[31:0]), bidirectional data bus (D[31:0]), separate data out (Dout[31:0]), data in (Din[31:0]) \mreq indicates a processor cycle which requires memory access seq indicates that the memory address will be sequential to that used in the previous cycle mreq seq Cycle Use 0 0 N Non-sequential memory access 0 1 S Sequential memory access 1 0 I Internal cycle bus and memory inactive 1 1 C Coprocessor register transfer memory inactive

9 ARM7TDMI Interface Signals (3/5) SoC Design Laboratory SoC Consortium Course Material 03/17/ lock indicates that the processor should keep the bus to ensure the atomicity of the read and write phase of a SWAP instruction \r/w, a read or a write cycle mas[1:0], encode memory access size byte, half-word or word bl[3:0], externally controlled enables on latches on each of the 4 bytes on the data input bus MMU interface \trans (translation control), 0: user mode, 1: privileged mode \mode[4:0], bottom 5 bits of the CPSR (inverted) abort, disallow access State T bit, whether the processor is currently executing ARM or Thumb instructions Configuration Bigend, big-endian or little-endian

10 10 ARM7TDMI Interface Signals (4/5) Interrupt \fiq, fast interrupt request, higher priority \irq, normal interrupt request isync, allow the interrupt synchronizer to be passed Initialization \reset, starts the processor from a known state, executing from address Debug support EmbeddedICE, contains the breakpoint and watchpoint registers Processor registers may be inspected Debug interface dbgen, external hardware to enable debug dbgrq, asynchronous debug request breakpt, instruction-synchronous request

11 11 ARM7TDMI Interface Signals (5/5) Coprocessor interface \cpi, ARM has identified a coprocessor instruction cpa, tells ARM that there is no coprocessor present cpb, coprocessor busy and cannot begin executing the instruction \opc, whether a memory access is to fetch an instruction or a data Power 5V or 3V supply, depending on technology and the circuit design JTAG (Joint Test Action Group) Testing the circuitry on the chip itself ARM7TDMI characteristics Process 0.35 um Transistors 74,209 MIPS 60 Metal layers 3 Core area 2.1 mm 2 Power 87 mw Vdd 3.3 V Clock 0 to 66 MHz MIPS/W 690

12 12 Memory Access The ARM7 is a Von Neumann, load/store architecture, i.e., Only 32 bit data bus for both inst. And data. Only the load/store instruction (and SWP) access memory. Memory is addressed as a 32 bit address space Data type can be 8 bit bytes, 16 bit half-words or 32 bit words, and may be seen as a byte line folded into 4- byte words Words must be aligned to 4 byte boundaries, and half-words to 2 byte boundaries. Always ensure that memory controller supports all three access sizes

13 13 ARM Memory Interface Sequential (S cycle) (nmreq, SEQ) = (0, 1) The ARM core requests a transfer to or from an address which is either the same, or one word or one-half-word greater than the preceding address. Non-sequential (N cycle) (nmreq, SEQ) = (0, 0) The ARM core requests a transfer to or from an address which is unrelated to the address used in the preceding address. Internal (I cycle) (nmreq, SEQ) = (1, 0) The ARM core does not require a transfer, as it performing an internal function, and no useful prefetching can be performed at the same time Coprocessor register transfer (C cycle) (nmreq, SEQ) = (1, 1) The ARM core wished to use the data bus to communicate with a coprocessor, but does no require any action by the memory system.

Cached ARM7TDMI Macrocells EmbeddedICE & JTAG CP15 ARM

& data Virtual Address MMU Physical Address AMBA Interface

cache Full memory management unit supporting virtual

& data cache Write Buffer ARM720T As ARM 710T but with

14 Cached ARM7TDMI Macrocells EmbeddedICE & JTAG CP15 ARM Core Inst. & data Virtual Address MMU Physical Address AMBA Interface AMBA Address AMBA Data ARM710T 8K unified write through cache Full memory management unit supporting virtual memory Write buffer Inst. & data cache Write Buffer ARM720T As ARM 710T but with WinCE support ARM740T 8K unified write through cache Memory protection unit Write buffer SoC Design Laboratory SoC Consortium Course Material 03/17/

15 15 Processor Core V.S. CPU Core Processor Core The engine that fetches instructions and execute them E.g.: ARM7TDMI, ARM9TDMI, ARM9E-S CPU Core Consists of the ARM processor core and some tightly coupled function blocks Cache and memory management blocks E.g.: ARM710T, ARM720T, ARM74T, ARM920T, ARM922T, ARM940T, ARM946E-S, and ARM966E-S physical address MMU AMBA interface instruction & data cache write buffer virtual address instructions & data ARM7TDMI EmbeddedICE & JTAG CP15 AMBA address AMBA data ARM710T

16 ARM8 Higher performance than ARM7 By increasing the clock rate By reducing the CPI ARM8 Higher memory bandwidth, 64-bit wide memory Separate memories for instruction and data access ARM9TDMI ARM10TDMI Core Organization The prefetch unit is responsible for fetching instructions from memory and buffering them (exploiting the double bandwidth memory) It is also responsible for branch prediction and use static prediction based on the branch prediction backward: predicted taken forward: predicted not taken memory (doublebandwidth) addresses read data write data SoC Design Laboratory SoC Consortium Course Material 03/17/2004 prefetch unit PC instructions integer unit CPinst. CPdata coprocessor(s) 16

17 Pipeline Organization SoC Design Laboratory SoC Consortium Course Material 03/17/ stage, prefetch unit occupies the 1st stage, integer unit occupies the remainder (1) Instruction prefetch (2) Instruction decode and register read Prefetch Unit (3) Execute (shift and ALU) (4) Data memory access (5) Write back results Integer Unit

18 18 Integer Unit Organization coprocessor instructions instructions inst. decode PC+8 decode register read coproc data multiplier ALU/shifter execute write pipeline +4 mux write data address read data memory forwarding paths rot/sgn ex register write write

19 19 ARM8 Macrocell 8 Kbyte cache (doublebandwidth) copy-back tag copy-back data virtual address read data write data update TLB prefetch unit PC ARM8 integer unit CPinst. CP15 instructions CPdata ARM810 8K byte unified instruction and data cache Copy-back Double-bandwidth MMU Coprocessor Write buffer JTAG write buffer MMU physical address address buffer data in data out address Process 0.5 um Transistors 836,022 MIPS 86 Metal layers 3 Die area 76 mm 2 Power 500 mw Vdd 3.3 V Clock 0 to 72 MHz MIPS/W 172

20 20 StrongARM The first ARM processor to use a modified-harvard (separate instruction and data cache) architecture and now available from Intel Feature A 5-stage pipeline with register forwarding Single-cycle execution of all common instructions except 64-bit multiplies Instruction cache/copy-back data cache Write buffer Pseudo-static operation with low power consumption Process 0.35 um Transistors 2,500,000 MIPS 115/268 Metal layers 3 Die area 50 mm 2 Power 300/1000 mw Vdd 1.65/2 V Clock 100/233 MHz MIPS/W 380/268

21 21 StrongARM core pipeline organization next pc pc I-cache fetch pc + 8 branch offset I decode B, BL MOV pc + disp branch target r15 register read instruction decode immediate ¼elds +4 LDM/ STM mux postindex pre-index shift ALU & multiply reg shift forwarding paths execute SUBS pc rotate load/store address D-cache buffer/ data rot/sgn ex LDR pc register write write-back

22 StrongARM Processor (1/2) SA-1100 Intel SA-1 core 16-Kbyte instruction and 8-Kbyte data cache MMU read and write buffers 512-byte mini-data cache LCD (5) instruction MMU CPU core instruction cache system bus LCD control DMA control SA-1 core data cache write buffer bridge mini-cache data MMU read buffer memory & PCMCIA data (32) address (26) control MHz KHz clock PLL RTC osc. interrupt control RTC serial 0 serial 1 USB (2) SDLC (2) I/O pins (28) battery (3) reset (2) generalpurpose I/O power manager reset control SoC Design Laboratory SoC Consortium Course Material 03/17/2004 OS timer peripheral bus serial 2 serial 3 serial 4 IrDA (2) UART (2) Codec (4) 22

23 23 StrongARM Processor (2/2) SA-1100 die plot Photo courtesy of Intel Corp. SA-1100 characteristics Process 0.35 um Transistors 2,500,000 MIPS 220/250 Metal layers 3 Die area 75 mm 2 Power 330/550 mw Vdd 1.5/2 V Clock 190/220 MHz MIPS/W 665/450

24 24 ARM9TDMI Harvard architecture Increases available memory bandwidth Instruction memory interface Data memory interface Simultaneous accesses to instruction and data memory can be achieved 5-stage pipeline Changes implemented to Improve CPI to ~1.5 Improve maximum clock frequency

25 ARM9TDMI Organization next pc +4 I-cache fetch pc + 4 pc + 8 I decode r15 register read instruction decode immediate fields B, BL MOV pc SUBS pc +4 LDM/ STM mux postindex pre-index mul ALU shift reg shift forwarding paths execute byte repl. load/store address D-cache buffer/ data rot/sgn ex LDR pc register write write-back SoC Design Laboratory SoC Consortium Course Material 03/17/

26 ARM9TDMI Pipeline Operations (1/4) ARM7TDMI: Fetch Decode Execute instruction fetch Thumb decompress ARM decode reg read shift/alu reg write ARM9TDMI: instr uction fetch decode r. read shift/alu data memory access reg write Fetch Decode Execute Memory Write The ARM9TDMI pipeline is much tighter and does not have sufficient slack time to allow Thumb instructions to be first translate into ARM instructions and then decoded It has hardware to decode both ARM and Thumb instructions directly SoC Design Laboratory SoC Consortium Course Material 03/17/

27 ARM9TDMI Pipeline Operations (2/4) SoC Design Laboratory SoC Consortium Course Material 03/17/ Thumb instruction decompressor Translates a thumb instruction into its equivalent ARM instruction

28 ARM9TDMI Pipeline Operations (3/4) SoC Design Laboratory SoC Consortium Course Material 03/17/ always condition Rd #imm8 Thumb ma jor opcode, format 3: MOV/ CMP/ADD/SUB with immediate minor opcode denoting ADD & set CC de stination and source register zero shift immediate value Rd 0 Rd #imm8 ARM Example ADD Rd, #imm8 Thumb ADDS Rd, Rd, #imm8 ARM

29 29 ARM9TDMI Pipeline Operations (4/4) Coprocessor support Floating-point, digital signal processing, special-purpose hardware accelerator On-chip debugger Additional features compared to ARM7TDMI Hardware single stepping Breakpoint can be set on exceptions ARM9TDMI characteristics Process 0.25 um Transistors 110,000 MIPS 220 Metal layers 3 Core area 2.1 mm 2 Power 150 mw Vdd 2.5 V Clock 0 to 200 MHz MIPS/W 1500

30 30 Cached ARM9TDMI Macrocell ARM920T ARM9TDMI 16KB instruction cache, 16KB data cache Full Memory Management Unit, Write Buffer ARM922T ARM9TDMI 8KB instruction cache, 8KB data cache Full Memory Management Unit, Write Buffer ARM940T ARM9TDMI 4KB instruction cache, 4KB data cache Protection Unit

31 ARM920T CPU Core SoC Design Laboratory SoC Consortium Course Material 03/17/

32 32 ARM9E-S Family Overview ARM9E-S is based on an ARM9TDMI with the following extensions: Single cycle 32*6 multiplier implementation EmbeddedICE logic RT Improved ARM/Thumb interworking New 32*16 and 16*16 multiply instructions New count leading zero instruction New saturated math instructions ARM946E-S ARM9E-S core Instruction and data caches, selectable sizes Instruction and data RAMs, selectable sizes Protection unit AHB bus interface Architecture v5te

33 33 ARM10TDMI (1/2) Performance on the same IC process ARM10TDMI ARM9TDMI ARM7TDMI MHz on 0.25µm CMOS technology Increase clock rate 6-stage pipeline ARM10TDMI branch prediction addr. calc. data memory access data write instruction fetch decode r. read decode shift/alu multiply multiplier par tials add reg write Fetch Issue Decode Execute Memory Write

34 34 ARM10TDMI (2/2) Reduce CPI Branch prediction Non-blocking load and store execution 64-bit data memory transfer 2 registers in each cycle 4 read ports and 3 write ports

35 ARM1020T Overview Architecture v5t ARM1020E will be v5te CPI ~ stage pipeline Static branch prediction 32KB instruction and 32KB data caches hit under miss support 64 bits per cycle LDM/STM operations EmbeddedICE Logic RT-II Support for new VFPv1 architecture ARM10200 test chip ARM1020T VFP10 SDRAM memory interface PLL SoC Design Laboratory SoC Consortium Course Material 03/17/

36 36 ARM1136J(F)-S First Implementation of ARMv6 Architecture ARM1136J-S integer-only core ARM1136JF-S with integrated floating point High speed pipeline microarchitecture 8 stages System level flexibility Low Power Microarchitecture designed for low power Power management modes Availability Delivering to first licensees in December 2002 The ARM11 core has been developed and integrated in parallel with the ARM11 PrimeXsys Platform to ensure a fully compatible, high performance, extendable system solution

37 37 Memory Hierarchy

38 38 Memory Size and Speed Small Fast registers Expensive On-chip cache memory 2nd-level off chip cache Main memory Large capacity Slow Access time Hard disk Cheap Cost

39 39 Caches (1/2) A cache memory is a small, very fast memory that retains copies of recently used memory values. It usually implemented on the same chip as the processor. Caches work because programs normally display the property of locality, which means that at any particular time they tend to execute the same instruction many times on the same areas of data. An access to an item which is in the cache is called a hit, and an access to an item which is not in the cache is a miss.

40 40 Caches (2/2) A processor can have one of the following two organizations: A unified cache This is a single cache for both instructions and data Separate instruction and data caches This organization is sometimes called a modified Harvard architectures

41 Unified instruction and data cache SoC Design Laboratory SoC Consortium Course Material 03/17/ FF..FF 16 registers processor instructions address copies of instructions instructions and data address data copies of data cache instructions and data memory

42 Separate data and instruction caches copies of instructions address FF..FF 16 cache instructions address instructions instructions registers processor address data data address copies of data cache data memory SoC Design Laboratory SoC Consortium Course Material 03/17/

43 43 Cache Write Strategies Write-through All write operations are passed to main memory Write-through with buffered write All write operations are still passed to main memory and the cache updated as appropriate, but instead of slowing the processor down to main memory speed the write address and data are stored in a write buffer which can accept the write information at high speed. Copy-back (write-back) No kept coherent with main memory

44 44 Software Development

45 Main Components in ADS ANSI C compilers armcc and tcc ISO/Embedded C++ compilers armcpp and tcpp ARM/Thumb assembler - armasm Linker - armlink Project management tool for windows - CodeWarrior Instruction set simulator - ARMulator Debuggers - AXD, ADW, ADU and armsd Format converter - fromelf Librarian armar ARM profiler armprof C and C++ libraries ROM-based debug tools (ARM Firmware Suite, AFS) Real Time Debug and Trace support Support for all ARM cores and processors including ARM9E, ARM10, Jazelle, StrongARM and Intel Xscale SoC Design Laboratory SoC Consortium Course Material 03/17/2004 ADS: ARM Developer Suite 45

46 46 ARM C Compiler Compiler is compliant with the ANSI standard for C Supported by the appropriate library of functions Use ARM Procedure Call Standard (APCS) for all external functions For procedure entry and exit May produce assembly source output Can be inspected, hand optimized and then assembled sequentially Can also produce Thumb codes

47 47 ARM Linker Take one or more object files and combine them Resolve symbolic references between the object files and extract the object modules from libraries Normally the linker includes debug tables in the output file

48 48 ARM Symbolic Debugger A front-end interface to debug program running either under emulator (on the ARMulator) or remotely on a ARM development board (via a serial line or through JTAG test interface) ARMsd allows an executable program to be loaded into the ARMulator or a development board and run. It allows the setting of Breakpoints, addresses in the code Watchpoints, memory address if accessed as data address Cause exception to halt so that the processor state can be examined

49 49 ARM Emulator: ARMulator A suite of programs that models the behavior of various ARM processor cores and system architecture in software on a host system Can be operates at various levels of accuracy Instruction accurate Cycle accurate Timing accurate Benchmarking before hardware is available Instruction count or number of cycles can be measured for a program Performance analysis. Run software on ARMulator Through ARMsd or ARM GUI debuggers, e.g., AXD The processor core model incorporates the remote debug interface, so the processor and the system state are visible from the ARM symbolic debugger Supports a C library to allow complete C programs to run on the simulated system

50 50 ARM Development Board A circuit board including an ARM core (e.g. ARM9TDMI), memory component, I/O and electrically programmable devices It can support both hardware and software development before the final application-specific hardware is available

51 51 ARM Integrator A mother with some extensions to support the development of applications Provides core modules, logic modules (Xilinx Virtex FPGA, Alter APEX FPGA), OS, input/output resources, bus arbitration, interrupt handling

52 Summary (1/2) ARM Processor Family Processor family ARM6 ARM7 ARM8 ARM9 ARM10 StrongARM # of pipeline stages 3 3 5 5 6 5 Memory organization Von Neumann Von

52 52 Summary (1/2) ARM Processor Family Processor family ARM6 ARM7 ARM8 ARM9 ARM10 StrongARM # of pipeline stages Memory organization Von Neumann Von Neumann Von Neumann Harvard Harvard Harvard ARM11 8 Von Neumann/ Harvard Clock Rate MIPS/MHz 25 MHz 66 MHz MHz MHz MHz MHz MHz 1.2

53 53 Summary (2/2) Memory hierarchy Unified cache/separate instruction and data cache Write-through with buffered write Software Development CodeWarrior IDE armcc/tcc/armcpp/tcpp armasm armlink armprof AXD (ARM extended Debugger) armsd ARMulator ARM Integrator

54 54 References [1] [2] ARM System-on-Chip Architecture, Second Edition, edited by S.Furber, Addison Wesley Longman: ISBN [3] Architecture Reference Manual, Second Edition, edited by D. Seal, Addison Wesley Longman: ISBN [4]

Computer and Digital System Architecture

Computer and Digital System Architecture EE/CpE-810-A Bruce McNair bmcnair@stevens.edu 1-1/37 Week 8 ARM processor cores Furber Ch. 9 1-2/37 FPGA architecture Interconnects I/O pin Logic blocks Switch